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no jobs here ...atleast some interview questions
hi,no one is posting jobs here. :( .. atleast anyone post some interview questions for digital asic design pleaseee.rgds...
EDA Jobs, Promotions, Advertising :: 11 Nov 2009 10:30 :: gunwant :: Replies: 12 :: Views: 3776
how to get the rise energy and fall energy
nverter internal power.i can know the internal energy equation by primepower manual. (internal power = rise_energy + fall_energy)how to know the rise_energy and fall_energy data?i need to create a cell library....
ASIC Design Methodologies & Tools (Digital) :: 11 Nov 2009 6:13 :: Kazzam :: Replies: 6 :: Views: 261
question about standard cell library
hican anyone tell me which cell should we include in a cell library?thankselika...
ASIC Design Methodologies & Tools (Digital) :: 14 Sep 2009 20:17 :: srpatel9 :: Replies: 3 :: Views: 303
cmos combinational/seqential logic circuits
hi,when designing cmos circuits for stand cell library, why symmetric rise/fall transition time is important? is balanced rise/fall propagation delay of a single arc also required, and why? for multiple inputs circuits, do the propagation delays of d...
ASIC Design Methodologies & Tools (Digital) :: 09 Sep 2009 17:38 :: tomorrowglue :: Replies: 4 :: Views: 336
characterisation of standard cell library
hi,iam presently studying about characterisation of cell library.i down loaded a .13u library from www.vlsitechnology.org .a sample is given below//power characterisation for an input pin of and gatepower_lut_template(pwr_x2_676_5x10) {variable_1 : i...
ASIC Design Methodologies & Tools (Digital) :: 03 Sep 2009 16:16 :: tomorrowglue :: Replies: 1 :: Views: 231
vlsi interview questions
vlsi1. explain why & how a mosfet works.2. draw vds-ids curve for a mosfet. now, show how this curve changes (a) with increasing vgs (b) with increasing transistor width (c) considering channel length modulation3. explain the various mosfet capacitan...
ASIC Design Methodologies & Tools (Digital) :: 08 Jun 2009 12:17 :: ramana459 :: Replies: 7 :: Views: 3369
power calculation from library cell data
hello!i was looking the other day at a .lib file for some libraries used, trying to find out how power is calculated by power estimatiob tools out of the library data providedfor each cell.so, for each cell the library provides the following:internal...
ASIC Design Methodologies & Tools (Digital) :: 06 Mar 2009 14:29 :: Zorbas-E- :: Replies: 2 :: Views: 399
a lot interview questions with resposes
hi all,here is a nice collection of interview questions with reponses:cmos interview questions.1/ what is latch up?latch-up pertains to a failure mechanism wherein a parasitic thyristor (such as a parasitic silicon controlled rectifier, or scr) is in...
EDA Jobs, Promotions, Advertising :: 21 Jan 2009 9:03 :: sridhar540 :: Replies: 15 :: Views: 8813
slew propagation in cdb.
hi all,how cdb creates the characterization table for slew propagation.thanks...
ASIC Design Methodologies & Tools (Digital) :: 22 Jul 2008 22:38 :: gliss :: Replies: 4 :: Views: 228
layout of standard cell
hi.................... can any body tell me that how can i improve the area power and delay of standard cell like flip flops and latches. and what iss the responsebilities of standard cell library development engineer. plz help me...
ASIC Design Methodologies & Tools (Digital) :: 19 Apr 2008 5:17 :: srp :: Replies: 9 :: Views: 762
io libraries
io libraries...
PLD, SPLD, GAL, CPLD, FPGA Design :: 07 Feb 2008 13:35 :: master_picengineer :: Replies: 3 :: Views: 196
unit load
hi i m going to design a cell library at 0.18u technology. i want to know how to design a unit load. i designed the balanced inverter as unit load. but the rise and fall time at the output are not same. so i changed the width of pmos to make them equ...
ASIC Design Methodologies & Tools (Digital) :: 07 Feb 2008 12:23 :: onlymusic16 :: Replies: 1 :: Views: 120
standard cell 1x driving strength, gate sizing, delay
dear all,i m doing standard cell of library. different gates have different gate sizing that will satisfy systhsis request.for all types of driving strength in standard cell, i m no idea how to decide the normal(1x) condition.e.g.--------------------...
ASIC Design Methodologies & Tools (Digital) :: 31 Jan 2008 12:58 :: Chethan :: Replies: 16 :: Views: 660
input capacitance of combination gate
for one nand2 gate, i run simulation(use lx(m)) and get the capacitances of two input ports. after i check two different standardcell libraries, there are two different result.(pmos size of a and b are equal. nmos size of a and b are equal too)one , ...
ASIC Design Methodologies & Tools (Digital) :: 15 Jan 2008 4:09 :: rain_181914 :: Replies: 6 :: Views: 174
[help] power lookup table in synopsys .lib
can anybody tell me how to estimate the power consumption in synopsys .lib file?whats the unit, uw/mhz?eg: 0.18um inverterif i use c×vdd²×f to calculate the dynamic power, then 0.00200pf loading matches the result (0.00200p×1.8²×1mhz = 0.00648uw, whi...
ASIC Design Methodologies & Tools (Digital) :: 29 Nov 2007 11:06 :: onlymusic16 :: Replies: 5 :: Views: 861
digital cmos
1)exp various mosfet capacitance&their significance?2)exp sizing of inverter.3)give the expression for cmos switching power dissipation.4)what happens to delay if u increase the load capacitance.5)what happens if we increase the number of contacts or...
PLD, SPLD, GAL, CPLD, FPGA Design :: 06 Nov 2007 9:05 :: no_mad :: Replies: 1 :: Views: 138
vlsi interview questions needed !!!!!!!!
hi i am fresher in vlsi technology. i need to prepare for interview.what are the best sites to prepare for interviews.or which are the site where i can get some standard questions for interview along with answers ????...
ASIC Design Methodologies & Tools (Digital) :: 18 Oct 2007 11:32 :: vlsi_freak :: Replies: 8 :: Views: 1638
why nand gates are considered more than nor
hai every body,nand gates are more preferred than nor gates,becos in nand gates nmos connected in series.what is the logic behind this?santu...
ASIC Design Methodologies & Tools (Digital) :: 04 Sep 2007 9:13 :: kpsai26779 :: Replies: 11 :: Views: 405
can anybody check this issue for icfb?
the procedure :1) open a empty schematic, insert one instance: analoglib-> vpulse, fill in all the parameters as following: v3 (net5 net6) vsource type=pulse val0=0.0 val1=1 period=10u delay=1u \ rise=1n fall=1n width=5u 2) open th...
Analog IC Design & Layout :: 17 Aug 2007 8:37 :: analogdesk :: Replies: 1 :: Views: 342
cmos inverter design
hi allam a freshie and new to designing and have to design a cmos inverter from scratch...a full custom design ..cannot use standard cells...in other words i have to design an inverter and some other logic gates and incorporate them together to form ...
ASIC Design Methodologies & Tools (Digital) :: 29 Jul 2007 6:05 :: gliss :: Replies: 7 :: Views: 486
standard cell library achitecture
hi,recently i encounter the following problem when i want to design a standard libray under submicron soi technology.as follow1 how to ascertain unit drive strenth ,such as invx1?2 how to acquire the p/n width ratio of invx1?addtionally,whats the dif...
ASIC Design Methodologies & Tools (Digital) :: 14 Jul 2007 23:54 :: eternal_nan :: Replies: 4 :: Views: 375
standard cell&i/o library
how much loading is added when we simulate the standard cell and i/o? and how to decide the w and l of mosfets? what parameters do we care? fall time? rise time? setup time? hold time?...
Analog Circuit Design :: 19 Jun 2007 6:01 :: ronialeonheart :: Replies: 9 :: Views: 282
frequency doubler circuit
i want a frequency doubler circuit so that i can double frequency of a given square wave input.i want to solve this problem only in analog.so plzz suggest me a circuit for this....thanks a lot!!!...
Analog Circuit Design :: 12 Jun 2007 6:10 :: chody :: Replies: 14 :: Views: 1725
difference between clock buffer and ordinary buffer
what is the difference between clock buffer and ordinary buffer....
ASIC Design Methodologies & Tools (Digital) :: 31 May 2007 9:56 :: lever :: Replies: 7 :: Views: 471
perl applications in eda
hi to allas i had promised in: 1. h**p://www.edaboard.com/viewtopic.php?t=98320i start to collect useful perl scripts on eda here:please help to gain this topic-------------------------------------------------------------------------------------1. sp...
Software Problems, Hints and Reviews :: 12 Apr 2007 7:14 :: ankit12345 :: Replies: 17 :: Views: 3708
how to select cell in clock generation file?
hi, now i design a clock divider. i know how to write verilog code to simulation, but for tapout, we often write clock divider using gate cell. my question is how to select gate cells? is there any criteria?thanks!/david...
ASIC Design Methodologies & Tools (Digital) :: 11 Apr 2007 10:46 :: quan228228 :: Replies: 3 :: Views: 354
ans: clock generation
ans: clock generationsuppose u want to generate a clock from xor and delay cell, the xor and delay cell are not common for all technologies and processes.even if u do it by full custom design it may not work properly.the rise and fall delays are diff...
ASIC Design Methodologies & Tools (Digital) :: 25 Oct 2006 6:18 :: satya_422 :: Replies: 2 :: Views: 207
cadence schematic editor with 90n library
hi i am working with cadence tool. i am using schematic editor with the 90n technology, but while simulating i am getting failures. with the .18u and .25u the things are fine. can anyone help me in this regard. the log message is as follows:w *war...
Software Problems, Hints and Reviews :: 12 Sep 2006 0:01 :: spartacus2 :: Replies: 0 :: Views: 414
rise time and fall time of inverter
hiboth n-mos and p-mos widths are minimum widths(that means we cannot folde it to decrease the rise time ) thento maintain the equal rise time and fall time to the inverter what are the steps your going to tack ?thankssivakumar...
ASIC Design Methodologies & Tools (Digital) :: 11 Jun 2006 21:12 :: xugefu :: Replies: 10 :: Views: 537
need helps for designing 3t dram!!!
q:design a 3-transistor cmos dram cell. show that the read and write operation is functionally correct, capable of operating of at least 100 mhz, and consuming very minimal power.(input rise time (10%-90%) and fall time (90%-10%) should be at most 1 ...
Analog IC Design & Layout :: 22 Feb 2006 11:30 :: omsi :: Replies: 1 :: Views: 141
need helps for designing 3t dram!!!
q:design a 3-transistor cmos dram cell. show that the read and write operation is functionally correct, capable of operating of at least 100 mhz, and consuming very minimal power.(input rise time (10%-90%) and fall time (90%-10%) should be at most 1 ...
Analog IC Design & Layout :: 19 Feb 2006 13:31 :: ferrarimaker :: Replies: 0 :: Views: 111
pss and large transient plot for sc-cmfb ota
hello everybody, for my fully differential fold-cascode ota with sc-cmfb, according to the kens paper simulating switched-capacitor filters with spectrerf, i use pss and can achieve good common mode output voltage results when i let two input signals...
Analog IC Design & Layout :: 05 Jul 2005 10:08 :: ethan :: Replies: 0 :: Views: 171
how to simulate ota with sc cmfb by using pss, pac, pnoise?
hi there,this question is repeated here, since i havent found the specific answer in this forum yet.can i use common ways (dc, ac, noise) to simulate ota with sc cmfb, then later go to sc amplifier? i found i couldnt. i couldnt get the desired resul...
Analog IC Design & Layout :: 30 Jun 2005 16:11 :: ethan :: Replies: 4 :: Views: 840
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intel 3g cpu real work on 3ghz ???
/amd cpu design ? use cmos 0.13um process how to 3ghz clcok ? or real clock is 1.5ghz use rise/fall edge trig on alu?or use 750mhz dual clock * 2 edge on alu ?? i ever heard via cpu use static cmos cell in 0.13um process only 1ghz(pipeline statge =...
ASIC Design Methodologies & Tools (Digital) :: 07 May 2003 1:45 :: FFFFFF :: Replies: 2 :: Views: 536
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