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Charge Pump Simulation Cadence

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Hi, everybody, I build a shematic of charge pump in cadence, but I don't know how to check the pump current (Icp) as well as the mismatch between the charge and discharge current. May you tell me how to simulate this? Thanks a lot.
Hi i designed charge pump by using switch at drain topology...and i also connected loop filter to charge pump charge pump specifications are i=75u loop filter specifications r=5.4k c1=4pf c4 =0.4pf here i attached the schematic and waveforms..... (...)
Hello All, I have designed Series Parallel charge pump that is used in Power Management circuit to charge the battery. Details: It has variable input from < 1V Output voltage must be > 1.8V Question: I don't have load current fixed(assuming must be around 500uA). How do I calculate the power efficiency? 1. Do I fix a constant (...)
u need to simulate the average output current of the charge pump with the phase difference between the Fref and Ffeedback also u need to do it with frequency difference as well khouly
How to simulate phase noise of the divider and charge pump by spectre? I try to simulate it with similar setting as phase noise simulation of VCO. But the result look like incorrect. Anyone know how to simulate it?
I am making a design for charge pump and i want to know how can i plot (Iout) i.e. charge pump current, VS the phase difference between Vref and VFB??? another question how can i test the charge pump for having a good performance in a noisy system,i.e. what kind of (...)
Hello people I need to find the phase noise contributed by a phase/frequency detector + charge pump combination which are part of a frequency synthesizer. When the synthesizer is locked, both the inputs to the PFD are of the same frequency and hence the beat frequency is zero (albeit there will be reference feedthrough). But I cannot do a PSS/P
You do it so that you can asess how much of the phase noise is contributed by the charge pump to the output clock. amarnath
Hi I have made a Dickson-based charge pump that is harvested by RF signal. The output voltage and power efficiency will be different depending on how many stages you have. My question is how to simulate power efficiency in cadence. I have no problem to calculate the input power (average(vt*it) at Vinput side). However, I don't know (...)
I have designd a charge pump of PLL. And I simulated pnoise of Spectre of cadence. The result of charge pump output noise is larger than 100pA at 1KHz. I don't know what is reason about this? Below is my cirucit and simulation result. :cry: Can anyone help me ?Thank you very much
just measure the voltage on the capacitance and multiplied by C, that is the Q . you should add the .meas statemant in hspice list: .mear tran vcpo avg v(o) from=XXn to=XXn. .meas charge param='vcpo*C' where v(o) is the voltage on the capacitance . the plot is "charge stored in capacitor VS phase error" ,not "ΔQ VS. p_error " you can
You need to know the kn and kp of the transistors. From the kn and kp, calculate the W and L for your transistors according to the currents required for the charge pump.
For Behavior simulation of close loop charge pump based PLL, PFD & charge pump noise parameter should be defined. And I don't know how to simulate single block PFD or charge pump noise by SpectreRF. Who have experience about that pls help me.
in the book "PLL Performance, simulation, and Design" ,author always say the charge pump gain KΦ is xxmA,eg,1mA. in another book ,the KΦ is UB/4π for the PFD, pls tell me KΦ=1mA what's means?
if you want to design Power use chargepump see Ti or other datasheet , like AAT3110 you should know charge pump use 4 mos switch pmos or nmos ? --> please think again and how large device how large driving current ? and charge pump clock ? in gernerl use 500K ~ 1M and (...)
How to design the negative charge pump and positive charge pump? What is the important thing in the design? Which simulation need to do? Thanks.
how can a charge pump for a pll be represented in simulink
What needs to be taken care in layout when doing layout of charge pump PLL ? Thanks
can u please explain the phase offset in pfd-charge pump and how i measure in cadence tool..\ please give me any doc thesis and realted material regards\
Hi, How to measure the integrated phase noise due to a charge pump? Is a transient simulation required to be done with the PSS and pnoise simulation? If I am using a voltage source to bias the charge pump output (open loop) then how do I measure the noise component (voltage) at the (...)
in the Perrott PLL simulation file, there is detector( that is PFD + charge pump) noise, which affect PLL phase noise performance. Is there any one know how to simulate it in Spectre? thanks
Hello. I need to design a substrate charge pump to generate a negative substrate bias. The picture shows a simple substrate pump basic cell proposed in the Baker Li "CMOS Circuit Design, Layout and anyone tell me any formulas to design this circuit
Hello. I need to design a substrate charge pump to generate a negative substrate bias. I'm newbie in analog design... Can anyone recommend any books or references? Thanks in advance.
i wanted to know how to simulation the output impendance of a 1.5X charge pump? thanks all
who has papers about analyze of charge pump loop. I use the following circuit , I want to solve the issue: 1. How can i do ac simulation of loop, 2. how can i make up the small signal model of
Hi. I am designing a wireless sensor which is very similar with 13.56 Mhz passive RFID which must need a charge pump that harvests power from RF signal in order to feed the rest of components in a chip. My question is what kind of power (or voltage) you receive on the tag antenna as minimum, but still enough to operate the chip? It will def
: I have a question for a charge pump circuit The topology shown in FIg1. with NMOS can replace for the PMOS ? It seems no used with PMOS ? Thanks .
HI : I have a charge pump circuit like Fig. , from the simulation result it can pump up to the 12v , but in real measurement, i find the block cannot pump to the high voltage. The question is it really hard to find the bug on the wafer, anyone who have ever design the charge (...)
Hi, everybody, I build a shematic of charge pump in cadence, but I don't know how to check the pump current (Icp) as well as the mismatch between the charge and discharge current. May you tell me how to simulate this? Thanks a lot.
good day guys... In my charge pump converter simulation, I found out that few of my transistors (in my capacitor and switches network) are operating in saturation. I believe that it should only be just LINEAR or CUTOFF. What are the possible implications on this? Below is the circuit for the capacitor and switches network: im
This circuit is from a paper "charge pump with perfect current matching(IEEE)",there is an opamp to ensure the charge and discharge current matching,but I think the positive feedback factor is equal to that of the negative feedback,so my question is that how to make sure the circuit is stable?Thank you very
hi all, the attached picture comes from my simulation of a charge pump,I have several questions need your help. 1.How does the current glitch happen? 2.what is the effect to the Pll system? 3.How to reduce it? Thanks a
Hi, Can any one tell me how to simulate the differential charge pump noise? From this forum, I know how to get the single output charge pump current. But how to get the differential output noise. Thanks.
Is it oscillation (a loop stability problem) or is it just charge pump ripple? 1mV seems like you could pick up that noise almost anywhere.
I am designing a charge pump for PLL. The structure is similar to traditional one which is: cascode pmos as up current, cascode nmos as down current, the middle is switch. The output voltage is from 0.4V to 1.4V as VDD=1.8V. If I want to get the DC current mismatch( (Iup-Idn)) less than 1% at output voltage from 0.4 to 1.4V, the
I am having some difficulty simulating the PFD/CP noise. I have the output noise of the charge pump in PSS (after setting the phase difference b/w ref and feedback to 0). The transfer function from here to PLL output should be N/Kphi. But, I am getting unrealistic results if I do this. Any ideas on what I am doing wrong?
It's simply a case of sequencing switches so that the capacitors are first connected across the 5V supply, given time to charge up then disconnected and rejoined in series with the supply. RS232 (or more accurately 'V24') needs the higher voltage on it's communcation wires to work properly and the charge pump is there to make design easier. (...)
Hi i am designing charge pump for a PLL using tanner. i got the output. but i need to know how to measure current mismatch. In research papers , graph is plotted between output voltage versus output current. how to obtain simulation output , a graph between output voltage versus output current using tanner. Kindly help me.
I'm running a simulation of the doubler. The switching arrangement resembles an H-bridge. Your capacitors are labelled 500 nF. To get them to show charge-pump behavior, I reduced the frequency to 50 Bias voltag
The aim is for each capacitor to charge to almost the same voltage as the power supply. Once that is reached, they drop and rise a little during every cycle. The speed at which they drop and rise is governed by the RC time constant. If they show large voltage swings, then it means you will not get maximum output voltage. It means either: (a) the
:wink: Hi friends, i search a High Side driver with integrated charge pump for automotive. Can somebody give me some tips ?? Thank you very much Regards
For charge pump current, In market, many ICs using 5mA or 10mA. New ICs has embedded with new registers which can select the charge punp current to design for different loop time.
i want to design a charge pump pll,who can give me some papers?
Hi I have device with external charge pump and PLL circuits. The reference frequency is 20MHz. Waht cares have to be take to reduce phase noise and measure it. Madhukar
ther is a trade-off between transistor size and efficiency: larger transistors need more charge at their gate, thus there is a optimum value for the size. BTW, I think 75% efficiency is not so bad specially if it is low power! BEST!
Could anyone suggest me a the best charge pump for pll (wide swing and large output resistance ) in your viewpoint Thx
Is there any integrated charge pump available in the market? I need to build a special PLL using seperated phase detector and charge pump blocks. There are lots of PFDs from maxim, ON, ... But I couldn't find any charge pump block. The phase comparator frequency is about 1~10MHz.
I need to design a fully on chip 8x charge pump. But I am lack of experience in charge pump design, so I want to start from the 2x first. I designed for the simplest one 2x charge pump with 4 NMOS and 4 PMOS transistor, but I am not sure how can I sizing them. Do any one have experience (...)
REG71055 it says input range is 1.8v to 5.5v for Vout=5.5v I wonder what if the input is larger than 5.5v? will that still work for charge pump regulator? What will be the characteristics for chage pump regulator when vin is larger than Vout? thanks ahgu
Attached file is the schematic of that charge pump circuit. The author said that the charge pump conveter is composed of two voltage triplers work complementary with each other. But the circuit is not clear to see. Can anybody help me to analsysi this circuit? Thank you!