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Charge Pump Simulation Cadence

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6 Threads found on edaboard.com: Charge Pump Simulation Cadence
I dont have much knowledge about charge pump. Once I used it in a PLL circuit. It had an upper pmos current source with an UP switch and a lower nmos sink with a DN switch. The outout load was a capacitance resistance loop filter. That circuit worked fine in 400 MHz. You can search for it in the net as PLL charge pumps.
I have designd a charge pump of PLL. And I simulated pnoise of Spectre of cadence. The result of charge pump output noise is larger than 100pA at 1KHz. I don't know what is reason about this? Below is my cirucit and simulation result. :cry: Can anyone help me ?Thank you very much
Hi. I am designing a wireless sensor which is very similar with 13.56 Mhz passive RFID which must need a charge pump that harvests power from RF signal in order to feed the rest of components in a chip. My question is what kind of power (or voltage) you receive on the tag antenna as minimum, but still enough to operate the chip? It will def
I am making a design for charge pump and i want to know how can i plot (Iout) i.e. charge pump current, VS the phase difference between Vref and VFB??? another question how can i test the charge pump for having a good performance in a noisy system,i.e. what kind of (...)
My superviser asked me to find out the relationship of Capcitors, transister on a voltage doubler. I dont know how to do a simulation with different value of capcitance and the ratio of W/L for finding a optimize the power efficiency on circuit pump circuit? Can anyone teach me the method of it? Thank you very much
i want to simulate charge pump ,divider, pfd,which eda tool should i use?? which simulation engine should i use?