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Charge Pump Simulation Cadence

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13 Threads found on Charge Pump Simulation Cadence
I am making a design for charge pump and i want to know how can i plot (Iout) i.e. charge pump current, VS the phase difference between Vref and VFB??? another question how can i test the charge pump for having a good performance in a noisy system,i.e. what kind of (...)
Hello people I need to find the phase noise contributed by a phase/frequency detector + charge pump combination which are part of a frequency synthesizer. When the synthesizer is locked, both the inputs to the PFD are of the same frequency and hence the beat frequency is zero (albeit there will be reference feedthrough). But I cannot do a PSS/P
You do it so that you can asess how much of the phase noise is contributed by the charge pump to the output clock. amarnath
Hi. I am designing a wireless sensor which is very similar with 13.56 Mhz passive RFID which must need a charge pump that harvests power from RF signal in order to feed the rest of components in a chip. My question is what kind of power (or voltage) you receive on the tag antenna as minimum, but still enough to operate the chip? It will def
I have designd a charge pump of PLL. And I simulated pnoise of Spectre of cadence. The result of charge pump output noise is larger than 100pA at 1KHz. I don't know what is reason about this? Below is my cirucit and simulation result. :cry: Can anyone help me ?Thank you very much
My superviser asked me to find out the relationship of Capcitors, transister on a voltage doubler. I dont know how to do a simulation with different value of capcitance and the ratio of W/L for finding a optimize the power efficiency on circuit pump circuit? Can anyone teach me the method of it? Thank you very much
Hello all When i do pnoise of a charge pump of a pll, the output is dBc/Hz so, it is normalized to the carrier, right? What is the carrier here? i understand this simulation for oscillators as there is a sinsoid carrier i normalized w.r.t. it but for charge pump what is the carrier??????? (...)
Hi all, I want to design a type-2 pll which consists of PFD(general), charge pump, passive LPF (2order), LC tank VCO, Feedback Divider N. I know Icp=50uA, vco gain=40MHz/v, vco output frequency range is 150MHz-220MHz, Z(LFP)=(1+sRC2)/(C1+C2)s(1+sRC1C2/(C1+C2))), then R=10k C1=10nF, C2=39nF. I calculate: t1=79.6us; t2=390us;and Loop BW is 9
One of the best thing I found for PLL was spectreVerilog simulator included in cadence IC environment. But this is true only if you have complex PLL with large digital core. In such case you can replace analog components (VCO, PFD, charge pump ....) with veriloga model, and use verilog model for digital cell. This will allow you to evaluate (...)
Actually, just the frequency response of the loop filter is not usually enough. The VCO has another pole, besides the usual 1/s. Then if you have something between the charge pump/filter and the vco (V-I converter for example) its frequency response will have to be taken into account too. You can think those secondary effects are at high frequencie
i want to simulate charge pump ,divider, pfd,which eda tool should i use?? which simulation engine should i use?
hi everyone I have a question about measure input impedence of two port network with cadence SpectreRF. My network consist of capacitors and diodes(a dickson charge pump shown in attachment), you know diode's resistance isn't constant, it depends on the voltage drop on it in certain extent. So when i do SP analyse how can i config the (...)
digtal PLL: digital PFD+charge pump+LPF+VCO, most porpular now; all digtal PLL: digital PFD+digital low pass filter+DCO, it have high phase noise, for example, MT4409 from Zarlink; analog PLL: analog PFD+LPF+VCO.