195 Threads found on edaboard.com: Chipscope
I'm trying to use MIG for RAM controlling in ISE.
The problem is that I can't use use chipscope with systems where the program is running out of DDR/DDR2. There seems to be errors with running generated vio files using MIG for DDR2. Do you have any solution or any other source which helps me find which changes should I make in the source
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-02-2011 07:17 :: hastidot :: Replies: 0 :: Views: 474
Hi every one
I have generated MIG core as a DDR2 controller for Virtex5 FPGA.
I have also generated chipscope core for viewing waveforms.
I have also added these codes to imp-top module:
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-06-2011 01:26 :: willgh :: Replies: 2 :: Views: 989
I had the same problem in chipscope, not all signals appear in the list and I didn't find the answer.
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-21-2011 14:17 :: kirill :: Replies: 1 :: Views: 411
I am trying to debug my VHDL design using chipscope pro.
I am inserting the chipscope core after synthesis, but it shows a line " No ICON parameters listed for selected device family"
What does this mean????
Also I am referring "
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-09-2011 04:50 :: melexia :: Replies: 0 :: Views: 706
hi every one
i am a newbie and i have a problem with the chipscope.
i am using "Digilent JTAG USB Cable"
problem is that during debugging i cannot observe any signal names (from my program) in chipscope.
no waveform is observed only lines are shown
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-18-2011 08:16 :: Ummar :: Replies: 0 :: Views: 1468
1) What is the maximum speed at which we can watch Flip-flop value changing through chipscope ?
2) what is the maximum number of different signals we can watch through chipscope ?
3) What protocol does chipscope uses to communicate between ILA, ICON, VIO and system.
I have XUP Virtex 2 Pro board. Please suggest any (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-17-2012 02:27 :: rocking_vlsi :: Replies: 11 :: Views: 1104
The question may absurd. But I want to know.
How user design- chipscope-JTAG chain-System are interfaced each other.?
Can you explain operation between these blocks.
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-19-2012 02:59 :: rocking_vlsi :: Replies: 1 :: Views: 300
Using trigger in chipscope, can I make multiple triggers, and every run, choosing just one of them to be the active trigger, while disabling the others?
This way I don't need to compile all design when I want to change triggers.
Can it be done?
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-08-2012 07:37 :: yuvalkesi :: Replies: 2 :: Views: 454
Can we have two clocks for trigger signals to be monitored on chipscope?
What is the way to monitor multirate data with chipscope? I have a design with an output signal with high decimation (>1000). I want to monitor both the high sample rate signal as well as the decimated signal. Is there any way out as we can add only 1 .cdc into a project.
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-09-2012 05:11 :: ravics :: Replies: 1 :: Views: 364
chipscope Pro analyzer uses the TCP/IP protocol to connect to the cable. This error occurs because the socket specified in the "Server Host Settings" is being used by another application.
To work around this issue, change the socket setting as follows.
1. Open chipscope Analyzer.
2. Select JTAG Chain -> Server Host Setting
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-18-2012 01:57 :: tpetar :: Replies: 3 :: Views: 388
For those who used VIO core using chipscope i have some questions--
1- i running VIO using the old fashion way - generate ILA,ICON,AND VIO and connect them - there is any new way to do so from the .cdc file creating?
2 - i can toggle FPGA I/O directly or i can toggle just internal signals?
async_in / SYNC_IN - what it use for? w
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-25-2012 06:39 :: itmr :: Replies: 2 :: Views: 331
I have Xilinx ISE Project Navigator 13.2 (free version).
I run chipscope Pro Analyzer 13.2 and click on "Open cable/Search JTAG chain", it correctly detects my device (Atlys board),
then it tries to run the program xilinx/13.2/ise_ds/ise/bin/unwrapped/CSE_SERVER.EXE, my anti-virus pops up telling me that
the program is a VIRUS!!! :sho
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-29-2012 18:52 :: Elektronman :: Replies: 1 :: Views: 344
i have code to to calculate pulse width. my code is working fine. I added a chipscop pro to my of net connection window some net's are missing. I declared the output as pw : out STD_LOGIC_VECTOR(31 DOWNTO 0);
but in net connection window it is showing as below
pw_2 pw_2 FDE FDE
pw_3 pw_3 FDE FDE
pw_4 pw_4 FDE
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-10-2013 12:27 :: satya_kola :: Replies: 4 :: Views: 520
I could be wrong in my current sleep-is-for-tomorrow state, but ... as far as I know all you need is jtag for chipscope goodness. Didn't it go a little like this: jtag => bscan => icon => the rest of chipscope stuff? As in, as long as you can do a boundary scan with your jtag you are golden. A xilinx platform cable like ads_ee showed will certainly
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-21-2013 12:25 :: mrflibble :: Replies: 4 :: Views: 579
please help me
My design when configration it on the FPGA and read the results through the chipscope i do not show the correct results
Note that the results in post place and rout simulation are correct
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-22-2013 14:15 :: sarmad88 :: Replies: 1 :: Views: 315
can i store data coming to computer by chipscope to file beacuse i need this data as feedback to FPGA.
THANK YOU IN ADVANCE
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-09-2013 13:09 :: sarmad88 :: Replies: 0 :: Views: 265
As far as I'm aware of, chipscope isn't designed to use other host interface than JTAG. To sample a number of fixed data points and process the data in the FPGA logic fabric internally, you'll need to design a functionally equivalent yourself.
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-28-2013 06:56 :: FvM :: Replies: 2 :: Views: 270
I am having some problem in understanding signal acquisition from chipscope.
please see the following images. they are 125 MHz clocks and one is 200 MHz clock. What is evident is that clocks are not smooth or synchronized..i.e. the HIGH and LOW time increase and decrease.
Note that the sampling clock is 12 MHz (i guess so, please see
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-08-2013 14:09 :: syedshan :: Replies: 4 :: Views: 279
try to use ddr2 sdram on virtex_5 lx110t board. I generate the example design by using mig. Then i simulate the design with modelsim and it works. Then i wanted to see the signals on chipscope but first of all i had clock problem of trigger, as you know if there is a clock problem with trigger so it means something is problem with clock pins or clo
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-24-2013 11:28 :: grenader :: Replies: 6 :: Views: 539
The clock speed you provide will be fixed. But the performance of the design will change with a chipscope core will change, probably negatively, as it now needs more resources and routing than before. But the key point is whether it still meets your timing requirements.
If you dont have full timing specifications, or lots of asynchronous nets, the
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-30-2013 05:17 :: TrickyDicky :: Replies: 1 :: Views: 213
What process? are you trying to halt the FPGA? you cannot do that unless you design it in such a way.
I dont know why you dont want to use triggers. All chipscope is is a monitor - you need triggers to force a download from the continuous buffer on the FPGA to the PC.
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-26-2013 08:34 :: TrickyDicky :: Replies: 2 :: Views: 195
I'm trying to observe signals on waveform window in chipscope pro analyzer for viretex 7 FPGA on VC707 board. I get the message that "Waiting for Core to be armed, slow or stopped clock".
FYI, I've hooked up the design clock port *clk_BUFGP onto board ocsillator 200mhz SYSCLK_P pin at FPGA pin E19 . I have set the trigger port as the Reset sig
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-20-2014 22:09 :: asicdesigner2014 :: Replies: 0 :: Views: 295
I'm trying to map a design generated low frequency clock of khz range to clock port of ILA core in chipscope PRo (.cdc) file. When I program and run the bitstream in fpga, it flags the message "Waiting for Core to be armed, slow or stopped clock".
When I tie the clock port to on board system clock or DCM clock, it's fine.
Kindly advise how to hoo
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-25-2014 04:53 :: asicdesigner2014 :: Replies: 0 :: Views: 203
I am working on MGT Virtex-4 with a design in it. The design is pretty huge with hundreds of internal signals. Now I am trying to debug the design using chipscope.
I created *.cdc file and when I get into core inserter to capture the parameters of my design, the 'NetName' and the 'Source Instance' have quite different name (I guess while
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-02-2014 08:45 :: kaiserschmarren87 :: Replies: 7 :: Views: 363
I have not used multiple ICONs till now since I thought only i ICON and multiple ILAs.
But since you raised this question I could see some sort of solution which might help
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-17-2014 10:44 :: kaiserschmarren87 :: Replies: 14 :: Views: 345
fixed some bugs.
Software Links :: 01-15-2003 07:33 :: leonqin :: Replies: 0 :: Views: 1293
Any good document for guiding using chipscope? The user guide is too long...
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-15-2004 11:01 :: zcq :: Replies: 10 :: Views: 1532
did you compare identify with chipscope?
As far as i know both programs are quite
similar? Do you know the main differences?
Software Problems, Hints and Reviews :: 10-08-2003 12:39 :: 2heat :: Replies: 7 :: Views: 1917
I would suggest to take a look at the open .
Btw, the chipscope is very easy to use. They provide a eval license for quite long.(3 months if i'm not wrong).
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-05-2004 00:13 :: dll_embed :: Replies: 4 :: Views: 1941
chipscope is really easy to use!
Install and generate (use generate from menu) the ILA's you need instantiate in HDL code
After map place and route, download to FPGA and use chipscope analyzer and JTAG cable to connect
Best reagrds Konrad
Software Problems, Hints and Reviews :: 10-16-2004 09:46 :: konrad :: Replies: 2 :: Views: 1514
I think you can insert DFT ciricuit into FPGA to test your designed circuits. JTAG circuit inherently in FPGA is used to test FPGA and for debug purposes.
test for what?? well if u intend to check the circuit for functionality at different nodes in the circuit.. u can do that better by using software tools (like chipscope
ASIC Design Methodologies and Tools (Digital) :: 10-25-2004 20:39 :: eda_wiz :: Replies: 4 :: Views: 2305
Iam the old student of never had skillful(experienced) for guiding you in right path.They will just read it from the slide they prepared.Moreover they will tell you to study FPGA based material from the net.They will poor in teaching FPGA and chipscope PRO. Take ur own risk.If u plan to join in sandeepani.ALL THE BEST.Placement a
EDA Jobs :: 05-23-2011 08:10 :: mailtoindian :: Replies: 1 :: Views: 1314
Well guys ive simuated my codes n verilog and all i need is to transfer them on the sparten 2e kit. I need to know wot type of connector is need to interpase my sparten 2e kit and the PC.
it says we need some chipscope pro connector.
cud anyone help me on this,
ASIC Design Methodologies and Tools (Digital) :: 03-02-2005 06:25 :: arunragavan :: Replies: 1 :: Views: 771
Whay you do not use Xilinx chipscope, or @ltera SignalTap?
Please read more carefully topic ... :)
It is for PC interfaced oscilloscope, based on FPGA, but not for debugging FPGA internals ...
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-28-2005 09:56 :: dainis :: Replies: 11 :: Views: 2886
It depends on which development board you choose. I use the Parallel Cable IV, and do all my FPGA debugging in ModelSim. I've never had the urge to use chipscope or any in-circuit debugging.
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-14-2005 01:22 :: echo47 :: Replies: 2 :: Views: 935
ISE Webpack is a free subset of ISE Foundation series. It has support from Web only and lacks some parts like CoreGen, MXE, ISE simulator, chipscope etc and is for Educational purpose only. But it supports all the new Xilinx FPGAs.
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-29-2005 02:27 :: Sparc :: Replies: 5 :: Views: 843
try using chipscope ..
ASIC Design Methodologies and Tools (Digital) :: 11-24-2005 22:57 :: omara007 :: Replies: 2 :: Views: 804
I used to work with a software called Xilinx chipscope, which allows to debug preselected signals/variables/ports on FPGA in runtime after hardware implementation. By this software, person can create generate a memory block and place it in during design stage. Connect the inputs of this memory to the required signals to verifiy. Proceed with
ASIC Design Methodologies and Tools (Digital) :: 08-25-2006 21:51 :: mpatel :: Replies: 3 :: Views: 741
Select the core type you wanna generate using chipscope core generator...I did choose ILA... then this core along with your design goes into the FPGA using chipscope core inserter... Then you can view the waveforms on the chipscope logic analyser....
Select a input signal as trigger such that.. you get to watch other sign
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-31-2006 00:26 :: s3034585 :: Replies: 14 :: Views: 1305
Recently,i do STA for FPGA design by using PT. Our design is to implement a MCU in FPGA, which is prototype simulation for soc. I am the first time to do such work, but i found PT is not the best tool for FPGA. i will list the reason beneath
1. When i check the a sdf file in pt shell, i found a lots of missing in timing delay information.especi
ASIC Design Methodologies and Tools (Digital) :: 08-31-2006 05:37 :: richardhuang :: Replies: 1 :: Views: 1205
me too want to buy a low price evaluation kit,with chipscope pro.
or may be without chipscope pro also ok.
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-13-2006 10:26 :: samuraign :: Replies: 4 :: Views: 1058
For webpack you can get free license. And for other tools like chipscope, Modelsim XE you can evaluate only. If you format and reinstall it will work upto the duration specified.
Its better to make as a full version to avoid the time limit.
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-30-2006 06:21 :: soundar :: Replies: 1 :: Views: 456
u need chipscope which is provided with the board but an evaluation copy of 30 days only.
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-15-2006 04:02 :: rsrinivas :: Replies: 3 :: Views: 1355
I have Xilinx ISE 8.2 ,system generator8.2i,chipscope pro and i have SPARTAN3E FPGA.
I have written program for scalable FFT(64 to 1K point) program in MATLAB(R2006a).
Now i have to implement this into SPARTAN it possible to use Mcode blocks in simulink and convert this
into VHDL code by System Generator8.2.
In the program
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-19-2006 09:25 :: Ravi kumar :: Replies: 0 :: Views: 1479
Is there any solution for using PCI based LPT card with JTAG dongles (Wiggler, Raven) with Macraigor software, Xilinx JTAG cables with IMPACT, chipscope running on WinXP?
My new Motherboard do't have onboard LPT, and I added PCI LPT card, but this card have nonstandart I/O addresses ( 0x8800-0x8807 and 0x8480-0x8487).
WinXP not allow PCI LPT
PC Programming and Interfacing :: 01-01-2007 13:38 :: dainis :: Replies: 0 :: Views: 1302
1. Functional Simulation
2. Timing Simulation
3. Board debug using embedded logic/analyzers and scope(I mean chipscope Signal Tap)
4. Design documentation
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-24-2007 11:35 :: Iouri :: Replies: 2 :: Views: 619
I have some FPGA programming experience. I want to try out ASIC design but lack necessary tools and knowledge. To get started, where can I get some standard cell libraries that are compatible with synthesis tools from Mentor Graphics like Leonardospectrum, precision rtl etc.
Where can I get some P&R tools and layout editors? Also in
ASIC Design Methodologies and Tools (Digital) :: 03-29-2007 01:44 :: kishore2k4 :: Replies: 2 :: Views: 665
hi i am using chipscope for tapping the internal signals... it is pretty easy to use...
the only disadvantage is the ammount of data you can capture is limited... because it uses internal block rams...
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-26-2007 23:10 :: s3034585 :: Replies: 7 :: Views: 1292
this would be the best option. all ur timing information is included in simulation and u know to get @ what points it is failing. as told u need to check ur IOB clk points as well. try debugging using chipscope.
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-26-2007 00:25 :: rsrinivas :: Replies: 4 :: Views: 757
Now i am doing a project in ISE. In my project, there is a *.cdc file which I used to observe internal signals with chipscope later. The device I used is Vertex4.
Is there anyone encountered this problem when running ISE :
The project is successfully synthesized, then is the map process:
(information in the console)
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-21-2007 22:30 :: Alfred_zhang :: Replies: 5 :: Views: 1070