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139 Threads found on Chipscope
I have been trying to get a diagonal line to show up on my screen using a Virtex 5 (V5LX110T) board. It has an external ZBT SRAM chip which I am using as a Frame Buffer. So far, I have written a series of sequentially incrementing data values at sequential memory locations and have been able to read them back using chipscope. I can verify t
I have wriiten my 64 outputs into block ram. Now i need show these 64 outputs on the kit( virtx 2 pro ) for synthesis. is it possible to use chipscope pro to see the internal(intermediate) nodes? or can i use uart for this? can u send me code for uart ( that reads from block ram)?
Hi every one I have generated MIG core as a DDR2 controller for Virtex5 FPGA. I have also generated chipscope core for viewing waveforms. I have also added these codes to imp-top module: module imp_top( ... ... ... . . . icon i_icon(.CONTROL0(control)); ila i_ila(.CLK(clk0),.CONTROL(control),.TRIG0(trig0),.DATA(data)); assign d
////////////////////////////////////////////////////////////////////////////////// module try(clka //,wea,addra,dina,douta ); input clka; // input wea; // input addra; // input dina; // output douta; wire clka; wire wea; wire addra; wire dina; wire douta; ram u
hi Have you already tried with Logical Analizator chipscope?
hello, I need to input data to a ram .....first 64 bits are inputted to first location of the ram in the first clock cycle.... 2nd 64 bits are inputted to second location of the ram in the second clock cycle.... till 8th data at the 8th clockcyle? i had wrote a code for this in verilog.....but this code is not synthesisable........... here me
you can use textio to output to a file. Or just use the waveform viewer of your favourite simulator. If you need to check a signal while its running on an FPGA - you'll have to use chipscope (Xilinx) or SignalTap (Altera).
Hi there I'm trying to use MIG for RAM controlling in ISE. The problem is that I can't use use chipscope with systems where the program is running out of DDR/DDR2. There seems to be errors with running generated vio files using MIG for DDR2. Do you have any solution or any other source which helps me find which changes should I make in the source
Hi could you please post a VIO core example ? Another good tutorial on VIO:
Hi Any body has good tutorial on VIO core or any good Demonstration on VIO core usage .I Have tried the Xilinx chipscope video ...but some steps are still vague .... could you help on this matter .. Or target FPGA is Spartan 3 Xc3s400 pq208 .... Thanks in Advance for reply ... blooz
1 Pin Interface - Flexible FPGA Debug Interface UG029 - Xilinx UG029 chipscope Pro 11.1 Quixilica VENUS VXS-1
It will use some, but it will depend on how many signal you add into chipscope. Its generally quite small for LEs, but more BRAM is consumed for more signals/larger capture size.
I want to observe signals deep in my hierarchical design. For example lets say my design hierarchy is Top Level Module A Module B Module C Module D I am able to see signals at the top level using ICON and ILA cores that i have instantiated at the top level. But how to observe signals in Module D ? I instantiated new
Hi, I have a problem with setting up the input data onto chipscope debugger. Say, I want to implement a simple 1 bit adder : entity CLA_1bit is Port ( A : in std_logic ; B : in std_logic ; C : in std_logic ; S : out std_logic ; P : out std_logic ; G : out std_logic) ; end CLA_1bit; architecture Behavioral of CLA_
Hi I am Xilinx player for a long time, now gonna fpga prototyping on altera board. Want to know what's the tool name in QuartusII which equivalent to chipscope in Xilinx. Thanks.
Hi folks I would like to know the function of the chipscope ILA trigger and how to use it ?
I am using Nexys 2 Spartan XC3S 1600E board. I have to use Digilent Adept but since Adept 2.3 will not run in my 64-bit windows-7 I tried installing Adept 1.0. But Adept 1.0 does not have chipscope plugin. As expected the Adept 2.3 is not detecting my board (It shows 'unknown device'). Is there any way to use chipscope plugin with Adept (any
hello aman, you can find many guides on google explaining how to use chipscope.. i've attached one with this post.. i hope it will be helpful
I run the ise12.1 to get the bit file, then I generate the cdc file to invoke the core inserter. There is an error when the device is configured with the cdc file in the chipscope pro. The error message is "ERROR: Configuration file read error:" How to resolve this issue? Thanks!
What problems are you getting? Can you provide the output of chipscope? How about the out of the simulation? You're not giving us a lot to work with here. As your code is, its a pain to read. If you are gonna post it in public, add comments so there can be a general understanding.
You need not provide the pin number information while inserting the core. Insert the signals u need to tap, trigger, sampling clock, depth... compile the design again and then analyse thru chipscope analyser. Pls check the appropriate manual...
hi i want know how to calculate the delay and power in the vhdl code. i am completeeed my coding part and i saw my results in chipscope but i want how to calculate delay and power
hi how czn we get power report for the project. i am using vhdl code i am completed my coding part and i done using fpga in chipscope but i did not get power report how can i get power report
i am using Spartan 3E board and i am trying to interface its PHY. I want to transmit UDP packets to my pc using statemachine implemented MAC. I have seen the output on chipscope and it is fine but the problem is that i cannot transmit the packets . If i dont plug in the crossover cable in FPGA, i can see the activity light on RJ45 port meaning t
hi, i have been using chipscope for my project. but it gives waiting for upload when ever i trigger.please help
you can consult this file for reference.
than what is the use of spartan 3e kit..... How are those two even related? chipscope is tool to probe into signals which are internal to the FPGA. Spartan 3E kit is development board from Xilinx.
i guess u should be having a development board. In that case the easiest way will be defining a memory and storing your values to the memory and u can store the output values to another memory. You can use chipscope or Signal TAP to view your memory through JTAG Next case is u can include an UART code into your FPGA and get the values from your
Well! chipscope captures a maximum of 16000 one time and at many times its not synchronous or not capturing all instances....Good tool but it's hard to capture unperiodic behavior of a signal or it possible so?.
You need to generate ILA and ICON Verilog or VHDL blocks using Coregen and then build these into your project as well as your functional code. chipscope requires these blocks, as they sample the signals you are interested in and send the data to the chipscope software. r.b.
Hi, I want to know how chipscope manages with background tcl apis to program boards connected in daisy chain fashion using idcodes of each device and download bitfiles to all such devices Thanks in anticipation for your replies!
Hi Sir/Madam, Can someone share their method to avoid reg/wire bus optimization during FPGA synthesis? I want to maintain some of the reg/wire bus so that i can view the result using SignalTap/chipscope software. Thanks in advance for your help.
I've used the LAN9118 recently on a DSP (Tigershark) I recommend looking at the C-code from the SMSC website. There search for the Init() function. Are you using chipscope or similar to look at the signals? I'm afraid it's not obvious to design the interface entirely in VHDL Regards
ppl i do not know how to get started wid instantiating ICON, VIO.... cores using ISE9.2.... chipscope pro manual from xilinx doesnt help me.....can anyone help me out with a elaborative cookbook sort of thing...
hi, i m using chipcsope pro 10.1 for the signal analysis,though i have successfully monitored quite a few signals in the design, BUT when i insert the chip scope core using "chipscope pro core inserter" at the "modify connections" stage i m facing following problems 1- I do not find some signal that are present in design 2- Few source i
refer to chipscope documents for connection details, if u want to have clear idea about the chipscope pro refer to website there u view a video demo about usage of chipscope pro usage clearly.
Does using chipscope to drive inputs to FPGA solves this problem specially it has a core called VIO "virtual inpuy/output" Thank You Yes. VIO core has synchronous Inputs and Outputs ..
Dear all, 1. I want to insert chipscope blocks (ICON, ILA) directly into my design in Xilinx project navigator. (before synthesis) 2. I generated files from chipscope Core Generator (.edn, .vhd, .ncf) but I do not know how I can assign .edn file into project navigator. 3. I always used Mentor Graphics HDL Designer for design entry
For FPGA, I use an FPGA from xilinx. After finish my coding, ISE will synthesis it. iMPACT sw will be used to burn the .bit file into FPGA. We can look the system functionality by using chipscope sw as provided.
My Platform Cable USB II works just fine on my Win2k computer. I also have a Platform Cable USB and WinXP system. I can mix them around with no problems. I'm running ISE and EDK 10.1.03 tools. I haven't used chipscope, in case that's where your problem occurs. I haven't used FCPU-X.
Hello guys, I'M using chipscope pro 8.2 version. I have monitored the pin or buffer inside FPGA by assigning the ports and triggers and clks. Now when running "Analyse using chipscope", I can read the data from the desired registers as a time basis, that is I can only view a few set of samples (512 or 1024 upto 16384) which were selectable while we
Hi All, How to get the info of the IR length for non-xilinx devices which are present in the xilinx jtag chain. i need to use chipscope for probing one of the xilinx fpga. hence i need the IR lengths of all the devices in the jtag chain(there are a couple of non-xilinx devices in the jtag chain). Thanx in advance Rgds, Renjith
/.../how can I send data into this module and check its response/... create an extra top level where you connect a test data source to your design and - eventually - a kind of output checker; the test data source can be either some logic or a memory filled with test patterns; to check the response use chipscope [xilinx
when i use the chipscope generator, i connect the signals i want to view to the ila core, but when i view the signal waveform in chipscope, the signal names are ch0,ch1,~~~~ ,something like that in default, is there some way to change the signal name quick ? i don't want to rename them one by one! thanks in advance!
Make sure that the clock net (clock signal in the RTL) is chosen as the trigger clock in the chipscope. Also make sure that your clock is working on the board.
You might have good luck buying an inexpensive third-party USB-JTAG cable. However, such cables usually require their own special software, and probably won't work with whatever JTAG software you already have. That could be a disadvantage if your original software has unique features (such as chipscope debugging) that aren't provided in the third-p
Hi, I am using chipscope analyzer. after the trigger signal it shows the buffer has some data. but it is not full. Then I select Stop button. but It does not show buffered data. Is there anything I do not take into account?
Added after 15 minutes: even if you plot the data using chipscope the plot is on some fixed set of samples collected from a buffer of size you have choosen . so you can go by this way that you export the data of output waveform(file -> export command in c-scope) in unsigned or
Hi all, I am designing a DCT in xilinx. Is ISE enough or any other tools are required for the design . I mean system generator and chipscope pro. What for they are used? Thanks and Regards Deepak
Hi all. I'm trying to capture some data and clock signal of a design. Below is my code. wire control0; icon i_icon ( .control (control0)); ila i_ila ( . control(control0), . clk(clk), . trig0({data0, data1, data2,data3,data4,data5,data6,clk}) ); when i run the chipscope analyzer, I'm able to cap