173 Threads found on edaboard.com: Chipscope
I'm trying to use MIG for RAM controlling in ISE.
The problem is that I can't use use chipscope with systems where the program is running out of DDR/DDR2. There seems to be errors with running generated vio files using MIG for DDR2. Do you have any solution or any other source which helps me find which changes should I make in the source
PLD, SPLD, GAL, CPLD, FPGA Design :: 02.03.2011 07:17 :: hastidot :: Replies: 0 :: Views: 429
Hi every one
I have generated MIG core as a DDR2 controller for Virtex5 FPGA.
I have also generated chipscope core for viewing waveforms.
I have also added these codes to imp-top module:
PLD, SPLD, GAL, CPLD, FPGA Design :: 06.04.2011 01:26 :: willgh :: Replies: 2 :: Views: 945
I had the same problem in chipscope, not all signals appear in the list and I didn't find the answer.
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.05.2011 14:17 :: kirill :: Replies: 1 :: Views: 370
I am trying to debug my VHDL design using chipscope pro.
I am inserting the chipscope core after synthesis, but it shows a line " No ICON parameters listed for selected device family"
What does this mean????
Also I am referring "
PLD, SPLD, GAL, CPLD, FPGA Design :: 09.06.2011 04:50 :: melexia :: Replies: 0 :: Views: 657
hi every one
i am a newbie and i have a problem with the chipscope.
i am using "Digilent JTAG USB Cable"
problem is that during debugging i cannot observe any signal names (from my program) in chipscope.
no waveform is observed only lines are shown
PLD, SPLD, GAL, CPLD, FPGA Design :: 18.06.2011 08:16 :: Ummar :: Replies: 0 :: Views: 1383
1) What is the maximum speed at which we can watch Flip-flop value changing through chipscope ?
2) what is the maximum number of different signals we can watch through chipscope ?
3) What protocol does chipscope uses to communicate between ILA, ICON, VIO and system.
I have XUP Virtex 2 Pro board. Please suggest any (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 17.01.2012 02:27 :: rocking_vlsi :: Replies: 11 :: Views: 1004
chipscope inserts something much like a pre-designed code which based on your requirement, it will be used. Pre-compiled drivers\code for JTAG interface will be available ON-chip. So that when you add chipscope blocks, it can talk with JTAG interface. But frame your question more sharply, will try to reply narrow.
PLD, SPLD, GAL, CPLD, FPGA Design :: 19.01.2012 03:54 :: xtcx :: Replies: 1 :: Views: 276
Using trigger in chipscope, can I make multiple triggers, and every run, choosing just one of them to be the active trigger, while disabling the others?
This way I don't need to compile all design when I want to change triggers.
Can it be done?
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.02.2012 07:37 :: yuvalkesi :: Replies: 2 :: Views: 416
Can we have two clocks for trigger signals to be monitored on chipscope?
What is the way to monitor multirate data with chipscope? I have a design with an output signal with high decimation (>1000). I want to monitor both the high sample rate signal as well as the decimated signal. Is there any way out as we can add only 1 .cdc into a project.
PLD, SPLD, GAL, CPLD, FPGA Design :: 09.03.2012 05:11 :: ravics :: Replies: 1 :: Views: 339
chipscope Pro analyzer uses the TCP/IP protocol to connect to the cable. This error occurs because the socket specified in the "Server Host Settings" is being used by another application.
To work around this issue, change the socket setting as follows.
1. Open chipscope Analyzer.
2. Select JTAG Chain -> Server Host Setting
PLD, SPLD, GAL, CPLD, FPGA Design :: 18.05.2012 01:57 :: tpetar :: Replies: 3 :: Views: 301
For those who used VIO core using chipscope i have some questions--
1- i running VIO using the old fashion way - generate ILA,ICON,AND VIO and connect them - there is any new way to do so from the .cdc file creating?
2 - i can toggle FPGA I/O directly or i can toggle just internal signals?
async_in / SYNC_IN - what it use for? w
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.10.2012 06:39 :: itmr :: Replies: 2 :: Views: 301
I have Xilinx ISE Project Navigator 13.2 (free version).
I run chipscope Pro Analyzer 13.2 and click on "Open cable/Search JTAG chain", it correctly detects my device (Atlys board),
then it tries to run the program xilinx/13.2/ise_ds/ise/bin/unwrapped/CSE_SERVER.EXE, my anti-virus pops up telling me that
the program is a VIRUS!!! :sho
PLD, SPLD, GAL, CPLD, FPGA Design :: 29.10.2012 18:52 :: Elektronman :: Replies: 1 :: Views: 309
Are you getting errors about the constraints?
Make sure the clock you use for chipscope is able to sample the signals you are giving it.
You may have a timing problem.
PLD, SPLD, GAL, CPLD, FPGA Design :: 12.01.2013 07:45 :: asi123 :: Replies: 4 :: Views: 447
I could be wrong in my current sleep-is-for-tomorrow state, but ... as far as I know all you need is jtag for chipscope goodness. Didn't it go a little like this: jtag => bscan => icon => the rest of chipscope stuff? As in, as long as you can do a boundary scan with your jtag you are golden. A xilinx platform cable like ads_ee showed will certainly
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.02.2013 12:25 :: mrflibble :: Replies: 4 :: Views: 471
please help me
My design when configration it on the FPGA and read the results through the chipscope i do not show the correct results
Note that the results in post place and rout simulation are correct
PLD, SPLD, GAL, CPLD, FPGA Design :: 22.02.2013 14:15 :: sarmad88 :: Replies: 1 :: Views: 253
can i store data coming to computer by chipscope to file beacuse i need this data as feedback to FPGA.
THANK YOU IN ADVANCE
PLD, SPLD, GAL, CPLD, FPGA Design :: 09.03.2013 13:09 :: sarmad88 :: Replies: 0 :: Views: 204
As far as I'm aware of, chipscope isn't designed to use other host interface than JTAG. To sample a number of fixed data points and process the data in the FPGA logic fabric internally, you'll need to design a functionally equivalent yourself.
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.04.2013 06:56 :: FvM :: Replies: 2 :: Views: 229
fixed some bugs.
Software Links :: 15.01.2003 07:33 :: leonqin :: Replies: 0 :: Views: 1293
Any good document for guiding using chipscope? The user guide is too long...
PLD, SPLD, GAL, CPLD, FPGA Design :: 15.04.2004 11:01 :: zcq :: Replies: 10 :: Views: 1494
I didn't use the chipscope ,but I think the Identify is better than the chipscope.
The Identify supports most FPGA ,but ChipSope only supports Xilinx's
Software Problems, Hints and Reviews :: 09.10.2003 03:24 :: GoodMan :: Replies: 7 :: Views: 1866
I would suggest to take a look at the open .
Btw, the chipscope is very easy to use. They provide a eval license for quite long.(3 months if i'm not wrong).
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.07.2004 00:13 :: dll_embed :: Replies: 4 :: Views: 1891
chipscope is really easy to use!
Install and generate (use generate from menu) the ILA's you need instantiate in HDL code
After map place and route, download to FPGA and use chipscope analyzer and JTAG cable to connect
Best reagrds Konrad
Software Problems, Hints and Reviews :: 16.10.2004 09:46 :: konrad :: Replies: 2 :: Views: 1470
I think you can insert DFT ciricuit into FPGA to test your designed circuits. JTAG circuit inherently in FPGA is used to test FPGA and for debug purposes.
test for what?? well if u intend to check the circuit for functionality at different nodes in the circuit.. u can do that better by using software tools (like chipscope
ASIC Design Methodologies and Tools (Digital) :: 25.10.2004 20:39 :: eda_wiz :: Replies: 4 :: Views: 2197
Iam the old student of never had skillful(experienced) for guiding you in right path.They will just read it from the slide they prepared.Moreover they will tell you to study FPGA based material from the net.They will poor in teaching FPGA and chipscope PRO. Take ur own risk.If u plan to join in sandeepani.ALL THE BEST.Placement a
EDA Jobs :: 23.05.2011 08:10 :: mailtoindian :: Replies: 1 :: Views: 1283
Well guys ive simuated my codes n verilog and all i need is to transfer them on the sparten 2e kit. I need to know wot type of connector is need to interpase my sparten 2e kit and the PC.
it says we need some chipscope pro connector.
cud anyone help me on this,
ASIC Design Methodologies and Tools (Digital) :: 02.03.2005 06:25 :: arunragavan :: Replies: 1 :: Views: 694
Whay you do not use Xilinx chipscope, or Altera SignalTap?
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.07.2005 07:07 :: Johnson :: Replies: 11 :: Views: 2745
It depends on which development board you choose. I use the Parallel Cable IV, and do all my FPGA debugging in ModelSim. I've never had the urge to use chipscope or any in-circuit debugging.
PLD, SPLD, GAL, CPLD, FPGA Design :: 14.07.2005 01:22 :: echo47 :: Replies: 2 :: Views: 889
ISE Webpack is a free subset of ISE Foundation series. It has support from Web only and lacks some parts like CoreGen, MXE, ISE simulator, chipscope etc and is for Educational purpose only. But it supports all the new Xilinx FPGAs.
PLD, SPLD, GAL, CPLD, FPGA Design :: 29.07.2005 02:27 :: Sparc :: Replies: 5 :: Views: 791
try using chipscope ..
ASIC Design Methodologies and Tools (Digital) :: 24.11.2005 22:57 :: omara007 :: Replies: 2 :: Views: 778
I used to work with a software called Xilinx chipscope, which allows to debug preselected signals/variables/ports on FPGA in runtime after hardware implementation. By this software, person can create generate a memory block and place it in during design stage. Connect the inputs of this memory to the required signals to verifiy. Proceed with
ASIC Design Methodologies and Tools (Digital) :: 25.08.2006 21:51 :: mpatel :: Replies: 3 :: Views: 701
Select the core type you wanna generate using chipscope core generator...I did choose ILA... then this core along with your design goes into the FPGA using chipscope core inserter... Then you can view the waveforms on the chipscope logic analyser....
Select a input signal as trigger such that.. you get to watch other sign
PLD, SPLD, GAL, CPLD, FPGA Design :: 31.08.2006 00:26 :: s3034585 :: Replies: 14 :: Views: 1261
Recently,i do STA for FPGA design by using PT. Our design is to implement a MCU in FPGA, which is prototype simulation for soc. I am the first time to do such work, but i found PT is not the best tool for FPGA. i will list the reason beneath
1. When i check the a sdf file in pt shell, i found a lots of missing in timing delay information.especi
ASIC Design Methodologies and Tools (Digital) :: 31.08.2006 05:37 :: richardhuang :: Replies: 1 :: Views: 1116
me too want to buy a low price evaluation kit,with chipscope pro.
or may be without chipscope pro also ok.
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.09.2006 10:26 :: samuraign :: Replies: 4 :: Views: 985
For webpack you can get free license. And for other tools like chipscope, Modelsim XE you can evaluate only. If you format and reinstall it will work upto the duration specified.
Its better to make as a full version to avoid the time limit.
PLD, SPLD, GAL, CPLD, FPGA Design :: 30.11.2006 06:21 :: soundar :: Replies: 1 :: Views: 426
u need chipscope which is provided with the board but an evaluation copy of 30 days only.
PLD, SPLD, GAL, CPLD, FPGA Design :: 15.12.2006 04:02 :: rsrinivas :: Replies: 3 :: Views: 1282
I have Xilinx ISE 8.2 ,system generator8.2i,chipscope pro and i have SPARTAN3E FPGA.
I have written program for scalable FFT(64 to 1K point) program in MATLAB(R2006a).
Now i have to implement this into SPARTAN it possible to use Mcode blocks in simulink and convert this
into VHDL code by System Generator8.2.
In the program
PLD, SPLD, GAL, CPLD, FPGA Design :: 19.12.2006 09:25 :: Ravi kumar :: Replies: 0 :: Views: 1385
Is there any solution for using PCI based LPT card with JTAG dongles (Wiggler, Raven) with Macraigor software, Xilinx JTAG cables with IMPACT, chipscope running on WinXP?
My new Motherboard do't have onboard LPT, and I added PCI LPT card, but this card have nonstandart I/O addresses ( 0x8800-0x8807 and 0x8480-0x8487).
WinXP not allow PCI LPT
PC Programming and Interfacing :: 01.01.2007 13:38 :: dainis :: Replies: 0 :: Views: 1261
1. Functional Simulation
2. Timing Simulation
3. Board debug using embedded logic/analyzers and scope(I mean chipscope Signal Tap)
4. Design documentation
PLD, SPLD, GAL, CPLD, FPGA Design :: 24.01.2007 11:35 :: Iouri :: Replies: 2 :: Views: 584
I have some FPGA programming experience. I want to try out ASIC design but lack necessary tools and knowledge. To get started, where can I get some standard cell libraries that are compatible with synthesis tools from Mentor Graphics like Leonardospectrum, precision rtl etc.
Where can I get some P&R tools and layout editors? Also in
ASIC Design Methodologies and Tools (Digital) :: 29.03.2007 01:44 :: kishore2k4 :: Replies: 2 :: Views: 635
hi i am using chipscope for tapping the internal signals... it is pretty easy to use...
the only disadvantage is the ammount of data you can capture is limited... because it uses internal block rams...
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.04.2007 23:10 :: s3034585 :: Replies: 7 :: Views: 1239
this would be the best option. all ur timing information is included in simulation and u know to get @ what points it is failing. as told u need to check ur IOB clk points as well. try debugging using chipscope.
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.04.2007 00:25 :: rsrinivas :: Replies: 4 :: Views: 704
Now i am doing a project in ISE. In my project, there is a *.cdc file which I used to observe internal signals with chipscope later. The device I used is Vertex4.
Is there anyone encountered this problem when running ISE :
The project is successfully synthesized, then is the map process:
(information in the console)
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.05.2007 22:30 :: Alfred_zhang :: Replies: 5 :: Views: 1011
Hi ! i am looking for an easy tutorial or getting started guide for chip scope pro!
kindly help me
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.08.2007 08:15 :: Junaid Alam :: Replies: 2 :: Views: 2685
If you are referring to the Xilinx/Digilent Spartan-3E Starter Kit, then its USB port is connected only to the FPGA's JTAG configuration/debug port. Unfortunately, Xilinx refuses to provide documentation for their USB protocol, so you have to use Xilinx software, and the only software they provide that can do general-purpose JTAG communication is C
PLD, SPLD, GAL, CPLD, FPGA Design :: 04.10.2007 23:24 :: echo47 :: Replies: 2 :: Views: 1125
i got the following error when iam doin PAR using questasim,for simple ram implementation,i have instantited BRAM.
iam able to debug even with chipscope,urgent plz.
# Reading C:/QuestaSim_6.2b/tcl/vsim/pref.tcl
# // QuestaSim 6.2b Jul 31 2006
# // Copyright 2006 Mentor Graphics Corporation
# // All Rig
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.10.2007 07:45 :: vinodkumar :: Replies: 1 :: Views: 883
how can i by ise8.2i prepare in impact the slaveserial to transmit and recieve data
from spartan 3e board , so i can do it using chipscope and by usb , so how can
i prepare jtag for that ?
PLD, SPLD, GAL, CPLD, FPGA Design :: 06.10.2007 08:57 :: modeonz :: Replies: 2 :: Views: 736
hi,does any one using ,this core of chipscope,if so purpose of it,how to use for a simple counter example,plz provide me this info.
and i found chipscope insertion by generating cdc does not provide this option,is it coreect.
PLD, SPLD, GAL, CPLD, FPGA Design :: 12.10.2007 01:39 :: vinodkumar :: Replies: 0 :: Views: 606
Firstly try your best to Get every thing Right with the software tools
As for Debugging you decide the critical signals
especially at boundary of modules and bring them out all together once
The Best thing is Use software Like chipscope
to view everything you need to see in REAL Time
Hope this is easily availab
PLD, SPLD, GAL, CPLD, FPGA Design :: 20.11.2007 01:10 :: aajizattari :: Replies: 6 :: Views: 749
I would like to use the following evaluation board to run my
My intention was to use chipscope in combination with JTAG to
download the bitstream to the FPGA and then use chipscope to
analyse whats going on in the chip. Unfortunately the documentation
for this card doesnt n
PLD, SPLD, GAL, CPLD, FPGA Design :: 22.11.2007 11:19 :: grubby23 :: Replies: 8 :: Views: 1932
i am trying to use chipscope vio core.I've generated edn cores for icon and vio ips
but i am not being able to insert them into my design. i have instatiated the icon and vio core in the top level of my design. whenever i try to synthesize i get ? on icon and vio cores instance .I tried to add two edns in project but t
PLD, SPLD, GAL, CPLD, FPGA Design :: 07.02.2008 03:18 :: kvingle :: Replies: 3 :: Views: 512