195 Threads found on edaboard.com: Chipscope
Hi ! i am looking for an easy tutorial or getting started guide for chip scope pro!
kindly help me
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-27-2007 08:15 :: Junaid Alam :: Replies: 2 :: Views: 2737
If you are referring to the Xilinx/Digilent Spartan-3E Starter Kit, then its USB port is connected only to the FPGA's JTAG configuration/debug port. Unfortunately, Xilinx refuses to provide documentation for their USB protocol, so you have to use Xilinx software, and the only software they provide that can do general-purpose JTAG communication is C
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-04-2007 23:24 :: echo47 :: Replies: 2 :: Views: 1182
i got the following error when iam doin PAR using questasim,for simple ram implementation,i have instantited BRAM.
iam able to debug even with chipscope,urgent plz.
# Reading C:/QuestaSim_6.2b/tcl/vsim/pref.tcl
# // QuestaSim 6.2b Jul 31 2006
# // Copyright 2006 Mentor Graphics Corporation
# // All Rig
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-05-2007 07:45 :: vinodkumar :: Replies: 1 :: Views: 928
Your question is somewhat unclear.
Do you have the Xilinx/Digilent Spartan 3E Starter Kit?
You said "transmit and receive data", so are you trying to communicate through the board's USB port with a BSCAN macro and scan chain that you've put into the FPGA?
If that's correct, then you want JTAG, not Slave Serial.
I think the only user-acc
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-06-2007 09:31 :: echo47 :: Replies: 2 :: Views: 775
hi,does any one using ,this core of chipscope,if so purpose of it,how to use for a simple counter example,plz provide me this info.
and i found chipscope insertion by generating cdc does not provide this option,is it coreect.
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-12-2007 01:39 :: vinodkumar :: Replies: 0 :: Views: 678
Firstly try your best to Get every thing Right with the software tools
As for Debugging you decide the critical signals
especially at boundary of modules and bring them out all together once
The Best thing is Use software Like chipscope
to view everything you need to see in REAL Time
Hope this is easily availab
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-20-2007 01:10 :: aajizattari :: Replies: 6 :: Views: 778
I would like to use the following evaluation board to run my
My intention was to use chipscope in combination with JTAG to
download the bitstream to the FPGA and then use chipscope to
analyse whats going on in the chip. Unfortunately the documentation
for this card doesnt n
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-22-2007 11:19 :: grubby23 :: Replies: 8 :: Views: 2019
i am trying to use chipscope vio core.I've generated edn cores for icon and vio ips
but i am not being able to insert them into my design. i have instatiated the icon and vio core in the top level of my design. whenever i try to synthesize i get ? on icon and vio cores instance .I tried to add two edns in project but t
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-07-2008 03:18 :: kvingle :: Replies: 3 :: Views: 548
As mentioned in an earlier post, I need an asynchonous instead of a synchronous data memory. The design was working with the BRAM, but
the data was delayed by one cycle. So one would expect when adding
a synchronous memory with the right timing behaviour to get the
design fully working. So I used the core generator 7.1 and generated a dist
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-07-2008 15:25 :: grubby23 :: Replies: 0 :: Views: 457
I am designing a DCT in xilinx. Is ISE enough or any other tools are required for the design . I mean system generator and chipscope pro. What for they are used?
Thanks and Regards
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-21-2008 22:41 :: deepu_s_s :: Replies: 8 :: Views: 952
You might have good luck buying an inexpensive third-party USB-JTAG cable. However, such cables usually require their own special software, and probably won't work with whatever JTAG software you already have. That could be a disadvantage if your original software has unique features (such as chipscope debugging) that aren't provided in the third-p
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-06-2008 06:07 :: echo47 :: Replies: 9 :: Views: 4254
Rather than the number of lines, what is more important is the complexity of your design. More the complexity, more the test cases you need. Testing all the possilbe condtions using Modelsim can be very cumbersome. If you write a test bench or multiple test benches to test the various conditions, it would be more convenient and efficient. With a t
ASIC Design Methodologies and Tools (Digital) :: 06-06-2008 12:39 :: k_vlsi :: Replies: 6 :: Views: 1361
/.../how can I send data into this module and check its response/...
create an extra top level where you connect a test data source
to your design and - eventually - a kind of output checker;
the test data source can be either some logic or a memory
filled with test patterns;
to check the response use chipscope [xilinx
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-31-2008 06:46 :: j_andr :: Replies: 5 :: Views: 2249
How to get the info of the IR length for non-xilinx devices which are present in the xilinx jtag chain. i need to use chipscope for probing one of the xilinx fpga. hence i need the IR lengths of all the devices in the jtag chain(there are a couple of non-xilinx devices in the jtag chain).
Thanx in advance
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-06-2008 08:38 :: Renjith :: Replies: 2 :: Views: 1130
Does using chipscope to drive inputs to FPGA solves this problem specially it has a core called VIO "virtual inpuy/output"
Yes. VIO core has synchronous Inputs and Outputs ..
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-30-2009 13:06 :: omara007 :: Replies: 2 :: Views: 1991
I realyl need a USB based JTAG interface and I am really short of money right now so I can not purchase one.
I have a ULINK2 device at home and wonder if it is possible to use that with Xilinx?
I specially need to use it with EDK and chipscope
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-26-2009 11:15 :: farhada :: Replies: 4 :: Views: 2484
I have Xilinx's Spartan 3e Starter Kit which has onboard DDR memory.
I'd like to start using that memory, but have struggled to get a DDR controller working.
I've tried using Xilinx's Memory Interface Generator, and while the code compiles, the testbench is too complicated & requires an external function generator (which I do not have access
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-16-2009 03:32 :: keitheda :: Replies: 3 :: Views: 800
I am not sure if your PCB track that carries this signal is good...If possible check with the FPGA pin directly unless if it's ball grid. Or capture using chipscope and trace the signal. I'm sure the glicthes couldbe off the chip if your code is perfect!...
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-03-2010 00:26 :: xtcx :: Replies: 6 :: Views: 1563
Hi FPGA folks
I have purchased the XtremeDSP Starter Platform – Spartan-3A DSP 1800A Edition but I didn't order any download cables along with it. I would like to know my options for downloading the bitfile to the FPGA ? .. can I use a normal JTAG cable with one terminal being of USB interface (to be connected to the PC) and the other term
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-21-2009 14:55 :: omara007 :: Replies: 13 :: Views: 7593
My Platform Cable USB II works just fine on my Win2k computer. I also have a Platform Cable USB and WinXP system. I can mix them around with no problems. I'm running ISE and EDK 10.1.03 tools. I haven't used chipscope, in case that's where your problem occurs.
I haven't used FCPU-X.
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-02-2009 23:54 :: echo47 :: Replies: 4 :: Views: 2051
For FPGA, I use an FPGA from xilinx. After finish my coding, ISE will synthesis it. iMPACT sw will be used to burn the .bit file into FPGA. We can look the system functionality by using chipscope sw as provided.
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-07-2009 00:49 :: ewan :: Replies: 1 :: Views: 626
i do not know how to get started wid instantiating ICON, VIO.... cores using ISE9.2....
chipscope pro manual from xilinx doesnt help me.....can anyone help me out with a elaborative cookbook sort of thing...
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-02-2009 10:03 :: naizath12 :: Replies: 0 :: Views: 634
I've used the LAN9118 recently on a DSP (Tigershark)
I recommend looking at the C-code from the SMSC website. There search for the Init() function.
Are you using chipscope or similar to look at the signals?
I'm afraid it's not obvious to design the interface entirely in VHDL
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-04-2009 17:29 :: lucbra :: Replies: 6 :: Views: 2197
Can someone share their method to avoid
reg/wire bus optimization during FPGA synthesis?
I want to maintain some of the reg/wire bus so that i can view the result using SignalTap/chipscope software.
Thanks in advance for your help.
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-24-2009 05:12 :: cafukarfoo :: Replies: 1 :: Views: 719
Our client is expanding its product development team. We are looking for an enthusiastic
and skilled FPGA designer. The right person will be developing products and handling
live TV distribution. FPGA development works closely with the software and hardware
development teams, creating next generation products. Our client provid
EDA Jobs :: 10-11-2009 15:56 :: Samepoint :: Replies: 0 :: Views: 1428
Well! chipscope captures a maximum of 16000 one time and at many times its not synchronous or not capturing all instances....Good tool but it's hard to capture unperiodic behavior of a signal or it possible so?.
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-19-2010 02:20 :: xtcx :: Replies: 6 :: Views: 638
i guess u should be having a development board. In that case the easiest way will be defining a memory and storing your values to the memory and u can store the output values to another memory. You can use chipscope or Signal TAP to view your memory through JTAG
Next case is u can include an UART code into your FPGA and get the values from your
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-23-2010 12:23 :: sudhirkv :: Replies: 8 :: Views: 2559
than what is the use of spartan 3e kit.....
How are those two even related?
chipscope is tool to probe into signals which are internal to the FPGA.
Spartan 3E kit is development board from Xilinx.
ASIC Design Methodologies and Tools (Digital) :: 02-20-2010 05:03 :: Jack// ani :: Replies: 4 :: Views: 600
Division is not one of the easiest functions to implement in digital systems. However I have a system which will be dividing very large bit numbers in excess of100 bits. The cores provided by chipscope cannot handle this sort of large scale division. How to tackle this issue?
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-14-2010 22:36 :: user_asic :: Replies: 3 :: Views: 1406
i am using Spartan 3E board and i am trying to interface its PHY. I want to transmit UDP packets to my pc using statemachine implemented MAC. I have seen the output on chipscope and it is fine but the problem is that i cannot transmit the packets .
If i dont plug in the crossover cable in FPGA, i can see the activity light on RJ45 port meaning t
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-20-2010 04:10 :: colt45 :: Replies: 2 :: Views: 741
how czn we get power report for the project.
i am using vhdl code i am completed my coding part and i done using fpga in chipscope but i did not get power report how can i get power report
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-22-2010 04:53 :: nithin.j38 :: Replies: 2 :: Views: 680
i am using spartan 3e board to transmit UDP packets.
The problem is that i can write to PHY registers but i cannot read them or atleast i cannot see any data in the chipscope pro.
kindly help me out.
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-24-2010 05:25 :: colt45 :: Replies: 8 :: Views: 2402
I’m implementing DDR SDRAM controller targeting on board xupv2p, virtex-II pro. DDR SDRAM: KVR400x64C3A/256 256MB
I have modulated with modelsim at all levels to “post and route” with model ddr.v of Xilinx and I received good result (be able to write and read). But I had trouble while targeting on board. I used chipscope to obse
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-25-2010 03:41 :: connit1986 :: Replies: 2 :: Views: 781
now i have the software Xilinx ISE 11, but i need some help,
1. when i installed the software, i found out 8 subprograms were on my desktop as follows: (Xilinx ISE 11, Xilinx PlanAhead 11, Xilinx System Generator 11, Xilinx Platform Studio 11, Xilinx SDK 11, Xilinx AccelDSP 11, Xilinx chipscope Pro Analyzer 11, and finally X
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-31-2010 10:53 :: Aya2002 :: Replies: 3 :: Views: 922
i want know how to calculate the delay and power in the vhdl code.
i am completeeed my coding part and i saw my results in chipscope but i want how to calculate delay and power
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-01-2010 06:31 :: nithin.j38 :: Replies: 0 :: Views: 759
What problems are you getting? Can you provide the output of chipscope? How about the out of the simulation? You're not giving us a lot to work with here. As your code is, its a pain to read. If you are gonna post it in public, add comments so there can be a general understanding.
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-23-2010 11:35 :: user_asic :: Replies: 4 :: Views: 1854
I don't think that you enter the first process.
what other devices are connected to the same connection? are you using a router?
Does your PC receive the data when you are using the delay? Have you established the connection between FPGA and PC? Is the header (use Wireshark to check this) correct?
these are just some basic things to check before
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-25-2010 13:01 :: lucbra :: Replies: 4 :: Views: 725
There is a big problem with determining the cause very strange bug:
Project in the crystal Xilinx works fine, but from only 7-10 hours and then one part of it hangs.
Now the details: By many experiments revealed that error inside the trigger of Xilinx chip (ie the output signal ceases to be):
start_flag <= (((EQUAL (rxd_sync (63 downto 56), SF
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-20-2010 15:06 :: asjohnas :: Replies: 3 :: Views: 507
If chipscope doesn't show any activity on the input pin, then I believe there are no other methods.
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-30-2010 09:33 :: Scrts :: Replies: 6 :: Views: 543
what are the Other Specialized software Used in FPGA Design Flow other than Simulation Software And synthesis Software ......Now we work on ISE .....Want to Know More Details About Synopsis Synplify ...Leonardo Spectrum etc ....what is the advantage of Using chipscope Pro ....
Could please Provide a generaL idea about the third party sof
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-06-2011 12:17 :: blooz :: Replies: 4 :: Views: 500
you can use textio to output to a file. Or just use the waveform viewer of your favourite simulator.
If you need to check a signal while its running on an FPGA - you'll have to use chipscope (Xilinx) or SignalTap (Altera).
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-03-2011 07:38 :: TrickyDicky :: Replies: 5 :: Views: 391
I think you can use some UART core to communicate to fpga before that you need some processing core like a Microprocessor /Microcontroller /DSP ..core ....
so the basic processor core will process your data and the data is input to the processor via rs232 and it communicates via Uart core inside fpga program the FPGA with a processor core
Digital communication :: 03-06-2011 02:42 :: blooz :: Replies: 3 :: Views: 617
I need to input data to a ram .....first 64 bits are inputted to first location of the ram in the first clock cycle....
2nd 64 bits are inputted to second location of the ram in the second clock cycle....
till 8th data at the 8th clockcyle?
i had wrote a code for this in verilog.....but this code is not synthesisable........... here me
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-08-2011 21:01 :: dll_fpga :: Replies: 4 :: Views: 582
Have you already tried with Logical Analizator chipscope?
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-16-2011 00:20 :: kirill :: Replies: 16 :: Views: 610
module try(clka //,wea,addra,dina,douta
// input wea;
// input addra;
// input dina;
// output douta;
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-22-2011 23:12 :: dll_fpga :: Replies: 2 :: Views: 588
I have wriiten my 64 outputs into block ram. Now i need show these 64 outputs
on the kit( virtx 2 pro ) for synthesis.
is it possible to use chipscope pro to see the internal(intermediate) nodes?
or can i use uart for this?
can u send me code for uart ( that reads from block ram)?
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-11-2011 00:46 :: anilkumar111 :: Replies: 0 :: Views: 453
I have been trying to get a diagonal line to show up on my screen using a Virtex 5 (V5LX110T) board. It has an external ZBT SRAM chip which I am using as a Frame Buffer.
So far, I have written a series of sequentially incrementing data values at sequential memory locations and have been able to read them back using chipscope. I can verify t
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-21-2011 16:00 :: vjabagch :: Replies: 0 :: Views: 519
I am using MIG as a DDR2 controller for viretx5. I know that the FPGA's RAM's function has some problems in some memory addresss. I'm oing to detect those addresses. I'v generated the design . But after using chipscope, I found the error signal aways being asserted and there are no valid data on the rd_data_fifo_out (rd_data_valid sometimes
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-28-2011 01:22 :: hastidot :: Replies: 0 :: Views: 451
I am working on MATLAB.. Can any one suggest me..
1) how to convert matlab code to hdl code?
2) how to connect FPGA to the CRO??
Thanking you in has good explanation about your Query 1
PC Programming and Interfacing :: 06-10-2011 05:22 :: blooz :: Replies: 3 :: Views: 1112
Look on the manufacturer's website; that's the only place you're going to find a model. You might contact their tech support for more help.
However, without knowing more, I suspect that getting the model is not going to solve your problem. You obviously have a flaw in your design and simulating the model is just going to fail like your chipscope
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-05-2011 13:20 :: barry :: Replies: 4 :: Views: 507