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173 Threads found on edaboard.com: Chipscope
Hi As mentioned in an earlier post, I need an asynchonous instead of a synchronous data memory. The design was working with the BRAM, but the data was delayed by one cycle. So one would expect when adding a synchronous memory with the right timing behaviour to get the design fully working. So I used the core generator 7.1 and generated a dist
Hi all, I am designing a DCT in xilinx. Is ISE enough or any other tools are required for the design . I mean system generator and chipscope pro. What for they are used? Thanks and Regards Deepak
You might have good luck buying an inexpensive third-party USB-JTAG cable. However, such cables usually require their own special software, and probably won't work with whatever JTAG software you already have. That could be a disadvantage if your original software has unique features (such as chipscope debugging) that aren't provided in the third-p
Hello friends, I programmed an application and checked with the modelsim and chipscope pro analyser to test the functionality of the application. Is it necessary to write a test bench in order to check the program or is it okay to check it in the modelsim?what is the main use of writing the test bench when we have modelsim and chipscope pro a
/.../how can I send data into this module and check its response/... create an extra top level where you connect a test data source to your design and - eventually - a kind of output checker; the test data source can be either some logic or a memory filled with test patterns; to check the response use chipscope [xilinx
Hi All, How to get the info of the IR length for non-xilinx devices which are present in the xilinx jtag chain. i need to use chipscope for probing one of the xilinx fpga. hence i need the IR lengths of all the devices in the jtag chain(there are a couple of non-xilinx devices in the jtag chain). Thanx in advance Rgds, Renjith
Does using chipscope to drive inputs to FPGA solves this problem specially it has a core called VIO "virtual inpuy/output" Thank You Yes. VIO core has synchronous Inputs and Outputs ..
Hi, I realyl need a USB based JTAG interface and I am really short of money right now so I can not purchase one. I have a ULINK2 device at home and wonder if it is possible to use that with Xilinx? I specially need to use it with EDK and chipscope
I have Xilinx's Spartan 3e Starter Kit which has onboard DDR memory. I'd like to start using that memory, but have struggled to get a DDR controller working. I've tried using Xilinx's Memory Interface Generator, and while the code compiles, the testbench is too complicated & requires an external function generator (which I do not have access
I am not sure if your PCB track that carries this signal is good...If possible check with the FPGA pin directly unless if it's ball grid. Or capture using chipscope and trace the signal. I'm sure the glicthes couldbe off the chip if your code is perfect!...
Hi FPGA folks I have purchased the XtremeDSP Starter Platform – Spartan-3A DSP 1800A Edition but I didn't order any download cables along with it. I would like to know my options for downloading the bitfile to the FPGA ? .. can I use a normal JTAG cable with one terminal being of USB interface (to be connected to the PC) and the other term
My Platform Cable USB II works just fine on my Win2k computer. I also have a Platform Cable USB and WinXP system. I can mix them around with no problems. I'm running ISE and EDK 10.1.03 tools. I haven't used chipscope, in case that's where your problem occurs. I haven't used FCPU-X.
For FPGA, I use an FPGA from xilinx. After finish my coding, ISE will synthesis it. iMPACT sw will be used to burn the .bit file into FPGA. We can look the system functionality by using chipscope sw as provided.
ppl i do not know how to get started wid instantiating ICON, VIO.... cores using ISE9.2.... chipscope pro manual from xilinx doesnt help me.....can anyone help me out with a elaborative cookbook sort of thing...
I've used the LAN9118 recently on a DSP (Tigershark) I recommend looking at the C-code from the SMSC website. There search for the Init() function. Are you using chipscope or similar to look at the signals? I'm afraid it's not obvious to design the interface entirely in VHDL Regards
Hi Sir/Madam, Can someone share their method to avoid reg/wire bus optimization during FPGA synthesis? I want to maintain some of the reg/wire bus so that i can view the result using SignalTap/chipscope software. Thanks in advance for your help.
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There is a perfect way of observing inside the FPGA. It is chipscope Pro, Xilinx tool and can only be used at Xilinx FPGA. Great tool for debugging, and can be used as a chip-inside osciloscope. You can add a CS file to your project and do some configs. You can observe any signals and all of your data coming through or going from to your RA
i guess u should be having a development board. In that case the easiest way will be defining a memory and storing your values to the memory and u can store the output values to another memory. You can use chipscope or Signal TAP to view your memory through JTAG Next case is u can include an UART code into your FPGA and get the values from your
than what is the use of spartan 3e kit..... How are those two even related? chipscope is tool to probe into signals which are internal to the FPGA. Spartan 3E kit is development board from Xilinx.
Division is not one of the easiest functions to implement in digital systems. However I have a system which will be dividing very large bit numbers in excess of100 bits. The cores provided by chipscope cannot handle this sort of large scale division. How to tackle this issue?
i am using Spartan 3E board and i am trying to interface its PHY. I want to transmit UDP packets to my pc using statemachine implemented MAC. I have seen the output on chipscope and it is fine but the problem is that i cannot transmit the packets . If i dont plug in the crossover cable in FPGA, i can see the activity light on RJ45 port meaning t
hi how czn we get power report for the project. i am using vhdl code i am completed my coding part and i done using fpga in chipscope but i did not get power report how can i get power report
i am using spartan 3e board to transmit UDP packets. The problem is that i can write to PHY registers but i cannot read them or atleast i cannot see any data in the chipscope pro. kindly help me out.
I’m implementing DDR SDRAM controller targeting on board xupv2p, virtex-II pro. DDR SDRAM: KVR400x64C3A/256 256MB I have modulated with modelsim at all levels to “post and route” with model ddr.v of Xilinx and I received good result (be able to write and read). But I had trouble while targeting on board. I used chipscope to obse
hello Friends, now i have the software Xilinx ISE 11, but i need some help, 1. when i installed the software, i found out 8 subprograms were on my desktop as follows: (Xilinx ISE 11, Xilinx PlanAhead 11, Xilinx System Generator 11, Xilinx Platform Studio 11, Xilinx SDK 11, Xilinx AccelDSP 11, Xilinx chipscope Pro Analyzer 11, and finally X
hi i want know how to calculate the delay and power in the vhdl code. i am completeeed my coding part and i saw my results in chipscope but i want how to calculate delay and power
What problems are you getting? Can you provide the output of chipscope? How about the out of the simulation? You're not giving us a lot to work with here. As your code is, its a pain to read. If you are gonna post it in public, add comments so there can be a general understanding.
I don't think that you enter the first process. what other devices are connected to the same connection? are you using a router? Does your PC receive the data when you are using the delay? Have you established the connection between FPGA and PC? Is the header (use Wireshark to check this) correct? these are just some basic things to check before
There is a big problem with determining the cause very strange bug: Project in the crystal Xilinx works fine, but from only 7-10 hours and then one part of it hangs. Now the details: By many experiments revealed that error inside the trigger of Xilinx chip (ie the output signal ceases to be): start_flag <= (((EQUAL (rxd_sync (63 downto 56), SF
I am using Spatran 3E. I have made a code to capture the data packets on ethernet port. I am using the clock of ethernet port which is 25 MHZ but i am not getting the result. When i checked the clock output on chipscope, it have a constant high level of 1. then I checked the UCF and i have used the exact same statement of manual NET "E_RX_CLK" L
what are the Other Specialized software Used in FPGA Design Flow other than Simulation Software And synthesis Software ......Now we work on ISE .....Want to Know More Details About Synopsis Synplify ...Leonardo Spectrum etc ....what is the advantage of Using chipscope Pro .... Could please Provide a generaL idea about the third party sof
you can use textio to output to a file. Or just use the waveform viewer of your favourite simulator. If you need to check a signal while its running on an FPGA - you'll have to use chipscope (Xilinx) or SignalTap (Altera).
I think you can use some UART core to communicate to fpga before that you need some processing core like a Microprocessor /Microcontroller /DSP ..core .... so the basic processor core will process your data and the data is input to the processor via rs232 and it communicates via Uart core inside fpga program the FPGA with a processor core
hello, I need to input data to a ram .....first 64 bits are inputted to first location of the ram in the first clock cycle.... 2nd 64 bits are inputted to second location of the ram in the second clock cycle.... till 8th data at the 8th clockcyle? i had wrote a code for this in verilog.....but this code is not synthesisable........... here me
hi Have you already tried with Logical Analizator chipscope?
////////////////////////////////////////////////////////////////////////////////// module try(clka //,wea,addra,dina,douta ); input clka; // input wea; // input addra; // input dina; // output douta; wire clka; wire wea; wire addra; wire dina; wire douta; ram u
I have wriiten my 64 outputs into block ram. Now i need show these 64 outputs on the kit( virtx 2 pro ) for synthesis. is it possible to use chipscope pro to see the internal(intermediate) nodes? or can i use uart for this? can u send me code for uart ( that reads from block ram)?
I have been trying to get a diagonal line to show up on my screen using a Virtex 5 (V5LX110T) board. It has an external ZBT SRAM chip which I am using as a Frame Buffer. So far, I have written a series of sequentially incrementing data values at sequential memory locations and have been able to read them back using chipscope. I can verify t
Hi all I am using MIG as a DDR2 controller for viretx5. I know that the FPGA's RAM's function has some problems in some memory addresss. I'm oing to detect those addresses. I'v generated the design . But after using chipscope, I found the error signal aways being asserted and there are no valid data on the rd_data_fifo_out (rd_data_valid sometimes
hii.. I am working on MATLAB.. Can any one suggest me.. 1) how to convert matlab code to hdl code? 2) how to connect FPGA to the CRO?? Thanking you in has good explanation about your Query 1 2
Look on the manufacturer's website; that's the only place you're going to find a model. You might contact their tech support for more help. However, without knowing more, I suspect that getting the model is not going to solve your problem. You obviously have a flaw in your design and simulating the model is just going to fail like your chipscope
Not sure if I understand what you are trying to do here. Going by the code snippets, I am guessing... You have an external i2c chip (the i2c slave) that is at address IIC_FMC_MUX_ADDR = 0x74. You send it 1 byte, and 1 byte only, with value 0x04. So over the wire you would expect to see this 0x74 byte going out followed by the 0x04 byte (an
If i were you, I'd use chipscope.
You said in the other thread you used a scope for debugging. What signals have you probed so far, and what did you see? Maybe some screenshots? Or otherwise do you have chipscope captures of the sda/sdc signals? That would help others help you quicker than having another round of guess work .;) That plus a check and recheck of all the addresses
Hi I have a multi-sourcefile VHDL project. One of my signals drives some logic in another module. I was analyzing my project with Xilinx chipscope pro, and monitoring the signal. First, after synthesis one of the ports as a signal should have disappeared since the two ports are directly conneted. Second, Port-A value should have been alwas eq
i am using the multiply and accumulate IP core from Xilinx ,the operation it performs is first multiply the two inputs a and b and give prod= a*b then it subtracts the previous output from Prod s=s-prod problem: i m not able to see the s(present) output as it is loop back. in chipscope one of my input is 30Mhz (12 bit samples) and other one is a
hi guys, Has anybody downloaded or used Xilinx ISE 13.3 webpack edition recently which is about 4.9GB?. My concern is what are the current limitations offered in this webpack (like any device limitation\chipscope\ISIM\floorplanner etc) and I could not also find Xilinx modelSim version along with this package, why is that?. If this is the case,
Aside from a bad SDRAM, there might be a timing issue. Did you do a timing simulation or just a functional simulation? Or, your FPGA might be writing to the RAM when you don't intend to. You might also look at your PCB trace lengths, if there is significant differencs in length, and you're running at high speeds, there might be a skew problem.
Hi I am using the SGMII mode in spartan6 + 88E1111 interface. we found the that autonegotiation not happening between the Marvell Phy and FPGA Mac. we observed the data in chipscope and after completion of Copper link autonegotiation Phy sendng the Configuration char (/C1/ = /K28.5/D21.5/config_reg/config_reg/r /C2/ = /K28.5/