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32 Threads found on Clock And Data Protocol
DSP: TMS320C6713B FPGA: Xilinx V7 interface: EMIF data Bus: 32-bit Bus clock: 100MHz Then how to calculate the effective bandwidth? Could anyone tell me the method...
Suppose I connect 2 FPGAs together in a parallel bus on the same PCB. They will use simple protocol: 1. data bus - 16 bits (or may be bigger) 2. same clock 3. rd_req 4. wr_e One FPGA shall put an address and assert rd_req then the other shall assert wr_e when data is on the bus, the bus is not (...)
If you are writing an SPI slave, then you do not control the clock. Instead you wait for the clock transition (low to high or high to low according to the protocol) and then sample the MOSI bit. Susan
As the title,the 1 and 0 sequence number should be balanced to decrease error rate(clock recovery). I would like to know the principle.Thanks
hi i m trying to interface DS1307 with AT89S51 but the problem is, i successfully write the time in RTC but fail to read. i checked on proteus. i use this protocol for reading start (release start bit) device add. (send device add. #0D0h) get byte (send clock only and get data fomr RTC) (...)
As already mentioned, "bit bash" is obviously a serial connection and follows a protocol. In so far the thread title is completely misleading. The minimal requirements for a "bit bashing" interface are a data line, a clock line (telling when the next should be read) and a sync line (marking either the (...)
Hi nikator, There is some predefined commands on the data sheet to send and receive the message first work it on it. I'm considered the you'r may be using micro controller enable the clock for it and configure the GPIO pin for the Tx and Rx, by using the UART communication (...)
Need some help. I am trying to emulate PS2 keyboard protocol. I am using open-drain pins with external pull ups to drive clock and data lines. Since the ports are open drain, when I write '1', they can become inputs. I need a way to check when the host(PC) tries to send data to the device(keyboard). The (...)
Hello all, What is the PIC SPI protocol clock frequency range and data rate range?? Thanks, Siddesh It depends on PIC so you should check the datasheet. give me your part number. I saw till 25Mhz
I'm not familar with STM8 either but I have coded several master and slave 1-Wire applications. You have to write your own timing routines to generate the reset pulse and clock pulses. Their timing is fairly critical. Remember there is only one master device on a 1-Wire bus so the slaves don't need to generate a clock as
Hi to all, Can i load the code into pic microcontroller using the spi protocol. sending the clock using SCK to PGC and data using SDO to PGD regards, jeevan
It is a serial 32 bit shiftregister you need to clock according to the data sheet to write and read (see datasheet page 8). Since there is no minimum clock frequency mentioned you could generate the read/write cycle by a microcontroller SW using four IO pins I think. Enjoy your design work!
To detect this protocol requires a mixer with clock recovery signal. Digital mixer uses D FF but is sensitive to noise and does not use all the energy of the bit. other method uses analog multiplier (non linear amplifier with clock * data.) clock must be in phase (PLL) Good luck. why use (...)
its SPI protocol having three wire interface. serial clock, serial data and chip select.
clock recovery (CDR) doesn't work with a standard phase-frequency detectors. It can only refer to the phase of existing edges. That's why it needs a protocol with guaranteed run length, e.g. 8b/10b encoding or withened data. Xilinx has XAPP250 and XAPP868 dedicated to CDR, other options are by utilizing (...)
2 wire eeproms use I2C protocol to communicate with controller and eeprom IC.. onw wire is clock line and other is data line.. EEPROM - Wikipedia, the free encyclopedia EEPROM Technology Tutorial:: Radio-Electronics
What I see is a clock line and a data line so it resembles I2C protocol Alex
What I meant was,in uart protocol start bit and stop are mandatory in starting the operation as the data does not depend on clock. but in i2c as it is synchronous why is start bit going low?it can directly send the data to slaves right?
It will be up to you to find the specs for the protocol you want to use to transfer the data and create a controller. You may be able to find one on Otherwise you'll have to code it yourself. My understanding is USB is a really difficult protocol to implement on an FPGA. It will depend on (...)
Can u explain what you wanna know? I2C and SPI are both different communication protocols. Moreover Find out more on these protocols to understand them better. Spi and I2c both use clock signals to send the data... If you wanna knw more, read about these (...)
Hi, 1. With reference to AXI protocol, what does a data beat mean? 2. Burst Size is the number of Bytes in a beat, and can go upto 128 bytes. But the data bus id only 32 bits wide (4-Bytes) so how can we transfer upto 128 bytes in a clock? 3. The Burst Length is actual number of data (...)
If the micro supports analogue inputs then you can use a single pin and a resistor network to give different voltages for each key, not recommended though. Much better way is to have an active serial keypad. If you have 2 port pins you can really use any clock+data protocol. Probably I2C is a good option, then you could use (...)
I designed I2S transmitter in VHDL to control AD1939 codec. My question is that; Is it possible to hold DAC output in certain level such as 2 volts, while disabling bit clock signal or I2S protocol works only continuous mode? I mean that if i want to hold dac output level in certain voltage level *i should send same data over (...)
G'day saudrehman, The SPI protocol has an enable data and clock line. If you only have one slave on the bus and hold the cs low you only need a data and clock line. The basic answer to your question is when the master is not sending out (...)
@pintuinvlsi I2C is a bus protocol for comunication between different devices. I2C stands for IIC - Inter Integrated circuits. It contains two lines. SDA (data line) and SCL(clock line) You can search more on the net for the same. Hope this helps.
You need to know the protocol for the paticular type of card you are communicating with. Some cheap cards use a synchronous interface with an external clock to transfer one bit at a time. The majority of cards use 9600baud rsr232-style signalling with 0v/5V logic levels. The data is half duplex on one connection so you have to tristate (...)
The SMBus communications requires only two pins besides the analog ground pin?through the SDA (data) and SCL (clock) pins. In fact, it is just the standard I2C connection .. The SMBus protocol summary can be found at: To make you confuse even more, here is an example of "smart" batte
still use fast clock to sample slow clock, then the delayed posedge of slow clock (this signal is synchronized to fast clock),if is signal is low, hold data in the slow domain , change the data output to fast clock domain only if this signal is high. In a word , avoiding (...)
Hi folks, I am looking for a serial data transmission protocol. In principle the Ethernet hardware layer should be used for cost reasons. (- symmetric RX and TX line) The protocol should have the following features: - DC balanced data coding - CRC protection - real time (...)
hi, basically jtag is a protocol like rs-232etc., a minimal jtag consists of a clock pin,data pin, supply pin etc. data is sent and recievied via jtag interface. It is used mostly in in system circuit programming. pimr
The keyboard connector will give you 5V. As in 5V full stop. Don't think this will ever change, just as the keyboard communication protocol hasn't changed since it was first introduced on the IBM PC/AT all those years ago... The clock and data lines are open collector, so as long as you let the motherboard pull-ups do (...)
that the reader have a clock singnal out?... I have study a few arthical about wiegand protocol some of them say that the time intervel is 1s and other say 2s. That the time intervel depand manufacture.?