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Clock Jitter Cause

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2 Threads found on edaboard.com: Clock Jitter Cause
On a clock path I had to use buffer insertion technique to achieve specific delay. How can I estimate the additional jitter these buffers give to the signal? In general, from your experience with TSMC 65 G, what variation every clock-type buffer can cause? Thanks.
And usually what causes jitter in silicon are: 1- turn on and turn off time of transistors are not perfect due to process/voltage/temprature variations. All these variation will cause the same transistor to turn on or off differently each time and that will cause jitter. 2- Noise in general is a main (...)