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177 Threads found on edaboard.com: Clock Schematic
Hi all I have a develop board of C51,7 segment show clock,I want to add alarm clock code,who can help me wrap it,Thanks in advance!
SPI flash uses standard SPI mode 0 or 3, not I2S (a protocol for audio chips). The device is very fast and can probably use any available ARM SPI clock, in case of doubt use moderate clock frequency, e.g. 10 - 20 MHz. You have 50 ohm SCK parallel termination in your schematic which can hardly be driven by the ARM clock (...)
Hello guys, I am wondering why i am having this issue. I am working with the evaluation board of xilinx: ZC702 EVALUATION PLATFORM HW-Z7-ZC702 I want to implement a MMCME2_BASE to generate some clocks for the PL. Therefore I am using the 50MHz default clock generated by the PS to drive the MMCME2. Then I compile the project, I prog
Hello Friends. I want to receive data from register-serial interface. I try to do that with module Spi.I want to have clock signal on the SCK pin. But when I start controller-I do not see anything.Can anyone tell some idea. Bestregards:Barosov
If that schematic is all there is to it, then CLK jerks both outputs high during every CLK=L period. This scheme needs a latch backend (with proper clock phasing) to capture the real and block the reset portions of the "output" (should be an intermediate) signal.
Hi. As I know basically, in synthesis, we can get the information which is WNS,TNS, from start point to end point critical data path from synthesis schematic. Also mostly in initial synthesis, we focus/concentrate on the setup violation because the hold violation is changed from CTS flow and P&R flow. But I'm confused that the effect clock ske
Insiders know that the device is a PIC24. I get a SPI clock frequency of 500 kHz and correct mode 0, so everything should be fine, presumed you are setting CS high again after the transmission. It should be also easy to clock in all '0' or '1' for test. Can it be an analog circuit problem?
What is ".f1" ? Try replacing it with just the number 1, "PORTB.1" and see what happens. In a real program you would also configure the clock source and other registers, I'm not sure if MikroC and Proteus respect that though. Brian.
Before talking about software, the RMII hardware setup should be verified. According to the schematic snippet in post #7, DP83848 clock input is driven from a 50 MHz crystal oscillator. The same clock must me connected to the ST32 RMII REF_CLK input. Did you?
Thanks. I have SNR =32 for BER=0.01. Therefore I cannot achieve this capacity is that correct? what modulation scheme do you suggest ? That is good SNR. Show details of eye pattern and schematic. Does your filter have ripple or group delay distortion , excess ISI? What is used for clock recovery? Comparato
Hi, I just bought this clock: 118672 118673 118674 And I want to replace the original display with a much larger one that requires 12V. In the link you will also find the schematic, but BE AWARE there is an ERROR: the displays are COMMON ANODE and not common cath
I agree with Barry but I add that I can't see what part is detecting the vibrations. There is what might be a microphone in the third picture to the right of the circuit board, mounted on the plastic case but without seeing the front side it could be anything. This *might* work but without the technical info on the product it is impossible to be s
Hello! I am planning to build my own chess clock based on Atmega8. I don't have experience in designing circuits so I would really appreciate your help in finding errors in my schematic. Best
Hi everybody, I'm working with a PIC 16F877a and assembly code to display alarm clock (cannot have real time) and temperature but I have some problems with buttons. It's not work. This is my attach file include code and proteus. Please help me! Thanks so much! 116228
Oops! You are quite right FvM, my apologies. Referring to post #7, if the clock is running, the date will still work but obviously will not be set correctly. It isn't necessary to set all the registers before counting commences. Are you running this only in a simulation or in real hardware? Possibly your simulator does not accurately reflect th
If you look at the RTL schematic attached, you will see that I buffered the differential clock with IBUFGDS and it is single ended... If so, can you please guide me how to overcome this problem? You can overcome this problem by licking an lsd laced sugar cube to rewire some neural paths. The paths related to y
The second schematic is wrong sequence for use in original pickit: 1 - VPP (Mclr) 2 - VDD (+5V) 3 - VSS (GND) 4 - DATA (PGD) 5 - clock (PGC) 6 - AUX (LVP)
Hello, I have designed a clock buffer(Inverter chain buffer). Here are my pre(schematic ) and post layout simulation data, Parameter Pre Post Static current 14.79pA 57.31pA
The crystal has no load capacitors (15pF). And it could be that your clock is not ticking.
Pin 14 of U1 and U2 should go to Vdd (+5V) and both pin 7 should go to GND.(0V). Your clock pulse should go to pin 13 of both U1 and U2 as they are identical. Connect a oscilloscope to the 3 points as in my schematic and you can get more info on what your circuit is doing. See my attachment in proteus. Allen
Hi, all I am using Altera Cyclone lV to receive the "LVDS" data from a clock and data recovery (ADN2813) Below is my what I did in the PFGA is, let the pin work as "LVDS" or "LVDS bus", like bel
The C7050 outputs logic level clock to Vcc, and PLL accepts lower levels by AC couple and internal Vcc/2 bias. So direct or AC couple ought to be fine with 15 pF high impedance load expected on clock signal. To debug this, you are going to have to probe each pin and read the chip specs to see if there are any discrepancies, for all inputs and o
I do not know the AVR, but ... try this: - write to the HC164 the value 0b10000000 (0x80, one 'one' and 7 'zero', using 8 clock pulses) and write 0b01111111 (0x7F) to the P0 port. But it depends on the matrix connections (polarity).
Hi, How MGTREFCLK should be used? I saw schematic of an Virtex-5 board with PCI Express x4. Two MGTs of the FPGA had been used for PCI Express. But only MGTREFCLK of one of the MGTs had been routed to clock and the other had been left floating and unused! Does MGT work without using MGTREFCLK? What is the purpose and usage of MGTREFCLK? Than
You must inform to the compiler what crystal are being used at circuit, so that delay function can be able to calculate proper timing. Use directive bellow to achieve that : #USE DELAY(clock = xxxxx) Where xxxxx represents crystal frequency. +++
the 16mhz above you mentioned is the main clock of system,like a people's heart. the main clock passes the divider frequency register , the frequency will be slow. every module in a MCU drived by the different clock divided from the main clock. the code you used in program: delay_ms(); delay_s(); will not execute (...)
Hi Everyone, Design: I have 2 decoder written in Verilog, and a test bench to generate the decoder input and clock. I have imported all the 3 modules separately and created a schematic view and config view. I have also declared global power supply in the design. I have verified the decoder separately for its functionality using ideal voltage
you can't apply your output and input to any port that you want. for example you can apply clock to only some pins, not to all. probably these errors because of this matter.
Hi Friends, This is a PIC16F84A Microcontroller based digital clock. It displays hours, minutes and seconds using six 7 segments displays. The circuit has three push button switches to reset and set hours and minutes. It shows time in 12 hour format. Use the following link to download schematic, source code and compiled hex
For the power supply design you might refer to the evaluation board schematic. It e.g. uses a 1.2V switcher for digital and a common 1.2V LDO for clock and DAC VDD in the default configuration. There's a very clear current consumption specification for each supply node in the datasheet, in case of doubt check with the total power that's als
The hi-tech universal toolsuite is compatible. Yes, the interrupt routine should give you around 78 kHz frequency with 20MHz crystal (1:256 prescaler value). You'll have to delay each clock in software to get the 38kHz freqeuncy you need. The switch transistor is easy to connect. Check the schematic I attached to this post. D1 is the IR LED. R1 is
Hello I have a project as follows: real-time clock using ds1307 pic 16f877a and displayed temperature by IC LM335 display on led 7-segment help people with language CCS Mplab complier
you are using a voltage source with most likely a 1fs rise/fall time, then yes you get those very large glitches, this is clock feed though and charge injection of turning on and off your switches. Never had your switches being switched by a voltage source, put a real inverter in there so it will be driven with something realistic. Also never use
The simplest solution is probably a tilt switch wired to the clock input of a 'D' flip flop. Connect the /Q output to the D input and the LED to the Q output. Use a transistor driver if more LED current is needed. It's a very simple and low cost solution and if battery powered it will draw almost nothing when the LED is turned off. Brian.
Here is my schematic for _dtack: 90387 If reset button released CPU steps 8 cycle of clock and always stpos with bus error. I tryed to analising: cycle1: do nothing cycle2: address is 0000000h ->74hc138 y0 is active low : rom selected. cycle3: _as, _lds, _uds active cycle4: cycle5: cycle6: cycle7: cycle8: _as, _lds, _uds rel
Yes, The glitch will be formed since the asynchronous clocks may reform with different delay. Can you post your schematic here? . Since you are not doing schematic, what is the purpose of this?. Because to understand in depth , it will be good if your working on schematic.
You can select right clock and copy or from file menu.. Or simply if u have hot key enabled click the obect press ''c'' dats it
Hi Look at this schematic what does the end of the dots mean. should I change the direction of the winding like clockwise and anti clock wise according to the dots?
hello, i am using seven segment display for making digital clock. i have made a program for this but on the time of simulating on proteus, it does not gives output & its also does not display even a single seven display. when i start simulation it gives an error." SIMULATION IS NOT RUNNING IN REAL TIME DUE TO EXCESSIVE CPU LOAD" now i am u
5 Digit 7-Segment ds1307 - RTC clock DS1820 - Temperature
Presented here design is a simple clock based on seven-segment displays, which can be easily made at home by every beginner within 2-3 hours. This device can be a nice gift made by yourself. schematic and some useful pictures c
could you post your circuit? as I think you should not use the same clock as the PIC... the common way is to generate the clock with a data pin of the PIC...
You should post your code so we can see what you are doing. Also provide the clock info. A schematic would also be nice
You are on the right track, I think. Are you saying you need to do this project with a schematic rather than VHDL or Verilog? If that is the case, then you ARE going to need a 27-bit counter. The output of this counter would enable the clock input to a flip-flop, so that the output of that flip-flop changes state every two-seconds. You would the
hi, i am trying to make the 8051 digital clock but the leds are not blinking someone plzzz............ suggest me what should i do:sad:
Hello I have a doubt regarding the layouts in trasnmission gate. Suupose i have 2 trasnmission gate TG1, TG2. When i place them close to each other , should the clock and clock_inv(connected to the gate ) , (clock is nothin but control point) be always inversed? i.e . Suppose TG1 has clock in pmos and (...)
A single 4017 IC (one of ten counter) driven by a slow clock, can operate one light. It's too easy to do it that way of course. Are you only allowed to use gates? Nevertheless the 4017 method can give you ideas how to clarify steps in the project flowchart. - - - Updated
Are you managing a 25MHz dot clock? Without seeing your code, it's hard to advise. The schematic would help too.
What is the length of your clock lines? Will it pass the antenna check? You could add small driver buffer into 1 line just to see it the issue goes away. I would think that paratitic inductance could be the culprit. Or you can look into the PEX values and add little LC tank into schematic and re-run the schematic sim.(probably easier)
How about a DDS chip instead? The AD5930 can take a 50MHz master clock, so is good up to about 25MHz output. It's very easy to drive from any MCU and can generate a programmable sweep and burst output.