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164 Threads found on edaboard.com: Clock Schematic
Dear experts, i'm getting problem in RTC on hardware. clock does not run in DS1307. First i set the time on rtc DS1307, whenever i read the clock, it will shows the same time as i set. kindly find the attachment for the circuit i used. - - - Updated - - - PIN 1 & 2 connected to 32.78khz PIN 3 co
If you look at the RTL schematic attached, you will see that I buffered the differential clock with IBUFGDS and it is single ended... If so, can you please guide me how to overcome this problem? You can overcome this problem by licking an lsd laced sugar cube to rewire some neural paths. The paths related to y
The second schematic is wrong sequence for use in original pickit: 1 - VPP (Mclr) 2 - VDD (+5V) 3 - VSS (GND) 4 - DATA (PGD) 5 - clock (PGC) 6 - AUX (LVP)
Hello, I have designed a clock buffer(Inverter chain buffer). Here are my pre(schematic ) and post layout simulation data, Parameter Pre Post Static current 14.79pA 57.31pA
The crystal has no load capacitors (15pF). And it could be that your clock is not ticking.
Valid clock edge ---> output valid
Pin 14 of U1 and U2 should go to Vdd (+5V) and both pin 7 should go to GND.(0V). Your clock pulse should go to pin 13 of both U1 and U2 as they are identical. Connect a oscilloscope to the 3 points as in my schematic and you can get more info on what your circuit is doing. See my attachment in proteus. Allen
Hi, all I am using Altera Cyclone lV to receive the "LVDS" data from a clock and data recovery (ADN2813) Below is my what I did in the PFGA is, let the pin work as "LVDS" or "LVDS bus", like bel
The C7050 outputs logic level clock to Vcc, and PLL accepts lower levels by AC couple and internal Vcc/2 bias. So direct or AC couple ought to be fine with 15 pF high impedance load expected on clock signal. To debug this, you are going to have to probe each pin and read the chip specs to see if there are any discrepancies, for all inputs and o
I do not know the AVR, but ... try this: - write to the HC164 the value 0b10000000 (0x80, one 'one' and 7 'zero', using 8 clock pulses) and write 0b01111111 (0x7F) to the P0 port. But it depends on the matrix connections (polarity).
Hi, How MGTREFCLK should be used? I saw schematic of an Virtex-5 board with PCI Express x4. Two MGTs of the FPGA had been used for PCI Express. But only MGTREFCLK of one of the MGTs had been routed to clock and the other had been left floating and unused! Does MGT work without using MGTREFCLK? What is the purpose and usage of MGTREFCLK? Than
You must inform to the compiler what crystal are being used at circuit, so that delay function can be able to calculate proper timing. Use directive bellow to achieve that : #USE DELAY(clock = xxxxx) Where xxxxx represents crystal frequency. +++
the 16mhz above you mentioned is the main clock of system,like a people's heart. the main clock passes the divider frequency register , the frequency will be slow. every module in a MCU drived by the different clock divided from the main clock. the code you used in program: delay_ms(); delay_s(); will not execute (...)
Hi Everyone, Design: I have 2 decoder written in Verilog, and a test bench to generate the decoder input and clock. I have imported all the 3 modules separately and created a schematic view and config view. I have also declared global power supply in the design. I have verified the decoder separately for its functionality using ideal voltage
you can't apply your output and input to any port that you want. for example you can apply clock to only some pins, not to all. probably these errors because of this matter.
Hi Friends, This is a PIC16F84A Microcontroller based digital clock. It displays hours, minutes and seconds using six 7 segments displays. The circuit has three push button switches to reset and set hours and minutes. It shows time in 12 hour format. Use the following link to download schematic, source code and compiled hex
For the power supply design you might refer to the evaluation board schematic. It e.g. uses a 1.2V switcher for digital and a common 1.2V LDO for clock and DAC VDD in the default configuration. There's a very clear current consumption specification for each supply node in the datasheet, in case of doubt check with the total power that's als
The hi-tech universal toolsuite is compatible. Yes, the interrupt routine should give you around 78 kHz frequency with 20MHz crystal (1:256 prescaler value). You'll have to delay each clock in software to get the 38kHz freqeuncy you need. The switch transistor is easy to connect. Check the schematic I attached to this post. D1 is the IR LED. R1 is
Hello I have a project as follows: real-time clock using ds1307 pic 16f877a and displayed temperature by IC LM335 display on led 7-segment help people with language CCS Mplab complier
you are using a voltage source with most likely a 1fs rise/fall time, then yes you get those very large glitches, this is clock feed though and charge injection of turning on and off your switches. Never had your switches being switched by a voltage source, put a real inverter in there so it will be driven with something realistic. Also never use
The simplest solution is probably a tilt switch wired to the clock input of a 'D' flip flop. Connect the /Q output to the D input and the LED to the Q output. Use a transistor driver if more LED current is needed. It's a very simple and low cost solution and if battery powered it will draw almost nothing when the LED is turned off. Brian.
Here is my schematic for _dtack: 90387 If reset button released CPU steps 8 cycle of clock and always stpos with bus error. I tryed to analising: cycle1: do nothing cycle2: address is 0000000h ->74hc138 y0 is active low : rom selected. cycle3: _as, _lds, _uds active cycle4: cycle5: cycle6: cycle7: cycle8: _as, _lds, _uds rel
I'm not designing any schematic. I wanted to know this because I wanted to switch between asynchronous clocks to the flops . It is guaranteed that input will be stable at time of switching. So if there will be glitch then certainly I need to gate clocks before switching and if not then there is no problem. So could you please tell if there (...)
You can select right clock and copy or from file menu.. Or simply if u have hot key enabled click the obect press ''c'' dats it
Hi Look at this schematic what does the end of the dots mean. should I change the direction of the winding like clockwise and anti clock wise according to the dots?
hello, i am using seven segment display for making digital clock. i have made a program for this but on the time of simulating on proteus, it does not gives output & its also does not display even a single seven display. when i start simulation it gives an error." SIMULATION IS NOT RUNNING IN REAL TIME DUE TO EXCESSIVE CPU LOAD" now i am u
5 Digit 7-Segment ds1307 - RTC clock DS1820 - Temperature
Presented here design is a simple clock based on seven-segment displays, which can be easily made at home by every beginner within 2-3 hours. This device can be a nice gift made by yourself. schematic and some useful pictures c
hello how can i clock the shift register using the pic 16f84a to drive led matrix , i want to use the same clock as the pic ?
You should post your code so we can see what you are doing. Also provide the clock info. A schematic would also be nice
Hello everyone. I would like to excuse myself in the beginning for my bad english. I got assignment to draw a scheme of circuit in Xilinx on Spartan 3 FPGA board, that would write a word on 4 7-segment display , and it needs to blink every 2 seconds. The word is "radi" which means "IT WORKS". Well, i wrote binary code for each leather: "R",
hi, i am trying to make the 8051 digital clock but the leds are not blinking someone plzzz............ suggest me what should i do:sad:
Hello I have a doubt regarding the layouts in trasnmission gate. Suupose i have 2 trasnmission gate TG1, TG2. When i place them close to each other , should the clock and clock_inv(connected to the gate ) , (clock is nothin but control point) be always inversed? i.e . Suppose TG1 has clock in pmos and (...)
A single 4017 IC (one of ten counter) driven by a slow clock, can operate one light. It's too easy to do it that way of course. Are you only allowed to use gates? Nevertheless the 4017 method can give you ideas how to clarify steps in the project flowchart. - - - Updated
Are you managing a 25MHz dot clock? Without seeing your code, it's hard to advise. The schematic would help too.
Hi I am making a clock distribution circuit working at 4GHz. Generated clock is needed by flipflops. I tried to route the clock in such way that the distance of clock source to all flipflops remain same. Moreover, i put a ground line between clock signals to reduce interference. However, as soon as i do the (...)
How about a DDS chip instead? The AD5930 can take a 50MHz master clock, so is good up to about 25MHz output. It's very easy to drive from any MCU and can generate a programmable sweep and burst output.
Hello. I have a simple question i want to build a clock generator but i want it start running when i supply control signal to it .can i do it with 555? I seen an application note of 555 and i understand i can use it as a clock generator but did not figure out how can i control when it starts generating my clock??? Txh.
First of all In my view....you need to fix the spec ....that what is the frequency of operation ( clock speed) then power rating of device then only you can start the design that will work for your functionality.....I had seen the layout picture that you are attached ...but it is always the safe practice to keep the pin names on the layout i.e. sil
Show your circuit. schematic and/or pictures will help. You need to pull the clock and data lines high or the keyboard won't transmit. Throw a 1k-10k pullup resistor between clock and +5V and another with data. See or electrical interface section at
The schematic clock resembles the 555 timer but without the p/n, which some vendors rate the output at 200mA source @12V, but only sink 5mA @5V 1. What is the voltage, Vcc for the 555? 5V? that would explain a part of your 1.1 mA sink current problem,, the other parts are ; design choice of sink vs source, measurement error {inductance and du
Dear all, I am having problem with getting data from my ADC... please see the following I am giving 125Mhz Sampling clock to1 Mhz Sine wave signal. The image attached is the response that I am getting. What are these Sudden Jerks or Instant rise or Falls... Is it because of sampling frequency bei In actual I have to give different si
Hi I am using PIC16F877A, CCS C v4.057, and proteus v7.7. I made a LED fleshing cube and it is working fine. But my program is restarting after few seconds. I have disabled WDT. clock= 4MHZ schematic 77063 #include "J:\Data\UIT WORK\FYP\Workshop\Material\lecture 04\LED PROJECT\CODE\led project.h" void T
76944 clock Signboard
hi every one, i doing eeprom program, some data is write in eeprom and also same data is read and display on code is run correctly but in schematic lcd show nothing... pls where i done my mistake in my code... #include <16F877a.H> #fuses XT,NOWDT,NOPROTECT,BROWNOUT,PUT,NOLVP #use delay (clock=4000000) //#use rs232(baud=9600
was it synthesised away? clock unconnected or stuck at '1'? reset stuck at '1'? clock enable stuck at '0'?
Can any one exlpain the function of IBUF I was just curious since in my synchronous design where reset is also synchronous with clock the reset is applied to IBUF as I saw on View Technology schematic in ISE. Also an ENABLE signal is connected to ibuff and both signals then routed to the whole circuit.
Hi bschaitanya, Can you please clarify the following SDC command? "create_generated_clock -name CLKB -source CLK2 -div_by 2 div_by_2_reg/Q -add" Why "-add" is used in the above command? Rgds, Kumar
I am using 16f877a , but problem is that it is not generating clock,, i have changed many crystals (20MHZ) but no result,, i have checked the crystal frequency ( it was showing 193 KHZ) ,I have programmed it in C and have used NOWDT , and HS Mode in fuses, also i have programmed in PIC C Compiler and burnt it in University Lab Programmer,, i have
The clock buffers would be bigger than the normal buffers in size. U need equal rise and fall times for clock so that u have same amount of duty cycle. Hope it helped....