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70 Threads found on Cmos Dac
It depends on the application. Gm ota's are widely used in low power filters while opamps has much wider spectrum. About dac reference. The good point to start are two books: Rudy van der Plasche "cmos integrated dacs and ADCs 2nd ed." and Franco Maloberti "Data Converters"
A confusing point is that you are initially asking for a digital driver but later saying it's a dac signal. In the digital case, you can simply use multiple paralleled fast cmos drivers.
I tried to design R2R dac structure at in my circuit. In my thought R2R dac is more area effective dac than conventional R-String dac. However, R2R dac has some disadvantages. 1. VCR Issue - In cmos process, poly-silicon resistor or diffusion resistor has voltage (...)
I have done exactly this, making modulation waveforms. Built up with HC series cmos, 25xx UV EPROMS and a poor-boy Rdac using Hcmos inverters and discrete resistors. 5V EPROMs are slow. OTP "EPROMs" (no window) I found were inferior speed grade and no good for my data rate. Willem programmer is what I used. Your question about how (...)
You can find a lot of overview articles in the net. Actually all books on Analog cmos circuit design have chapters on ADC and dac designs. The problem is there are many different architectures, each with its special advantages and weaknesses, s. e.g.
It does sound unusual, but then this is a research paper. It could be an exotic process using 40nm cmos with some critical stray capacitance scheme using a Capacitive dac in C-2C mode rather than R-2R resistive mode at microwave speeds. Any references?
I have found a way around the issue -getting a differential clock output and then converting it using an LVDS to cmos converter - and it works fine. Why don't you use this profound way to distribute a high speed clock signal? It would be my first choice anyway. I agree that you'll preferably monitor the clock signal quality with
HI, I have to simulate an electronic circuit with Altium. But I can not find the spice model of triger schimtt nand gat 40106 and dac 7541 I have a model of 40106 but it does not work. * CD40106B cmos Hex Schmitt Triggers * * The cmos Intergrated Circuits Databook, 1983, RCA Solid State * atl 10/3/89 Update interface and (...)
hello, i hv to design digital sigma delta modulator in dac in cmos software but i dont understand how to make circiut of 3rd order modulator using accumulator with 8 bits, plz help me to make this diagram, no mash topology only single loop 3rd order 8 bit modulator:-(
Dear all, I have to design a dac. To understand different architectures, I draw an ideal 2bit subdac in order to build 1V 4 bit dac, and tried to made the schematic 10.3-6 of "cmos Analog Circuit Design" from Allen and Hollberg work. I used ideal opamp with a 1V reference on the positive input. There is something I (...)
Hello, i m going to implement digital sigma delta modulator of dac in electric vlsi design system ,i don't understand how to take input in cmos design ',plz tell me what will be the input of modulator in cmos....
hi my friends i have been designed 10-bit 50M sample/s Successive Approximation ADC in cmos 0.18um technology i have been used HSPICE for simulation, now i want to test my dac's SFDR, SNDR and ENOB spec in Hspice. i really have not any information about this. is there any good reference for it? i have no time for doing it, please help!!!!!!!!!!
Hi, I am looking for a very simple dac architecture in cmos 0.18um Technology with 1.8V supply, capable to convert between 1.2V - 1.8V. 8-bit resolution is sufficient. Frequency is 32kHz. What kind of architecture would you suggest? Any input is welcome T
News, Jone 2011 "TSMC and Agilent will present and discuss the 60GHz reference design and flow next week at the Design Automation Conference (dac 2011) in San Diego, CA (5?9 June), as well as at the 2011 IEEE International Microwave Symposium (IMS) in Baltimore, MD (5?10 June). " Does anyone have documents relating to this presentation? Thanks.
hello everyone!! I am reading the book "cmos cascade sigma delta modulators for sensors and telecom - Error analysis and practical design". In the first chapter, while discussing about the dac errors in ∑Δ modulators it says--
Hello, I have some issues in designing an opamp to use it as switched cap integrator in an Δ∑ ADC. The process is cmos 65nm Context - introduction : This 14-bits ADC will be used as "Built-in Self Test" for a 10-bits dac - the analog input signal speed is not determined and can be AS LOW AS I WANT. I arbitrarly choose the analog
Thanks ... But now i am designing a 10 bit cmos current steering dac. So how can i apply the inputs and measure differential phase & gan ? How can i make a simulation set up for it ?
Hello all, I am currently designing a current steering dac with an LSB in the range of 20nA, in a 90nm cmos process. I know this is a small value but has anyone every made a dac with an LSB this low? I know this will be very much in the noise and I don't care really about linearity, due to correction later, but can it be done? I also (...)
How to make sure the cmos Li-Ion battery charger has an output voltage accuracy as <1%? You'll need an (at least) appropriately accurate bandGap + digital trimming, e.g. with a 4-to-5-bit R-2R dac .
Hello All, i'm studying a novel architecture of a Successive Approximation ADC based on a charge redistribution dac for a cmos Image Sensor, the converter is differentiel. can you plz help me on how to simulate the INL & DNL of this converter? thank you Maalma
I have to measure dac for Wireless communication. When I look for the way of the how to measure dac, I found "very few people wrote down their dac's SNDR in their Paper." Most of them only measured dac's SFDR. In measuring the dac, All I have to do is to measure the dac's SFDR? (...)
How many bits, and how accurate? I've made rail-rail dacs using cmos hex inverters and discrete resistors (R-2R). But these have no appreciable drive strength.
Hi, I am located in Europe and looking for an analog/mixed IC design engineer position - Telecommuting or Freelance - Frequent travel is possible. EDA tools availability can be figured out. - 15 years strong experience in cmos/Bicmos IC design: PLLs, DLL, ADC/dac, voltage regulators, AGC and control loops, switch cap, amplifiers, buffers, (...)
Hi all I am designing resistor string dac using 0.35um cmos specifiaction is 8bit , 80ks/sec and MAX 10nF load. I have finished designing Resistor string and decoder. Finally I am making output buffer(opamp). I have to consider 2 cases load. my question is As I design the opamp for buffer, Will I
Hi all, I would like to have following paper for current steering dac design. so please download it.. "A 10-b, 500-MSample/s cmos dac in 0.6 mm" by Chi-Hung Lin and Klaas Bult JSSC1998 Dec" Thanks in advance, Siva
All of them are about the current steering dac design. 1: An accurate statistical yield model for cmos current steering D/A converters. A.Van den Bosch, M.Steyaert and W.Sansen. 2: SFDR-bandwidth limitations for high speed high resolution current steering cmos D/A converters . A.Van den Bosch, M.Steyaert and W.Sansen. thanks!!!!
I have a dac book, I want to share for everybody.
Hi to all to forum members, though I have already searched the forums and posted this in Analog IC Layout and Design, I am posting it in this forum too. I have a cmos chip with 12bit and 6 bit current steering dac, and I want to characterize it its INL, DNL, settling time with offset and gain error. Only equipments I have in lab is a mixed s
Hi to all to forum members, I have a cmos dac chip with 12bit and 6 bit current steering dac, and want to characterize it its INL DNL settling time with offset and gain error.I want to test the chip in school setting. Only equipments I have in lab is a mixed signal scope, a function generator and bunch of DC power supply. For an (...)
hi i want to calculte the INL/DNL of ADC, the method given in "cmos analog circuit deisgn " by allan and holberg. in this method he described that put an ideal dac after ADC and sweep the input signal from 0 to vref and make the differnece of dac output and input signal and plot this equvalant vin-vin1 with respect to input . we can then (...)
hi, i'm reading the book cmos analog circuit design by Allen and i have a question about the charge scaling dac. if the switch S1 is closed, the voltage of C1 is Vref and the voltage of C2 is zero, and i think it will not change whether S1 is open or not. So Vout is zero, it's impossible. i don't know what does S1 use for in this circuit. [ur
In 90nm cmos, to design a 6-8 bit, 500MHz dac, which topology gives smallest area? Currently, I'm thinking R-2R ladder, current steering, charge redistribution/algorithmic iterative dacs. Any thoughts on this? Thanks.
I am making a SAR ADC and wondering if you guys can help me. I already have my SAR built and just need assistance with the others. For the analog comparator I know I can use a comparator chip instead but I am trying to do it using cmos, transistors (BJTs) or any other transistor based alternatives. The only idea I have with BJTs is using a dif
i think the book "cmos Integrated Analog-to-Digital and Digital-to-Analog Converters by Rudy J. van de Plassche" is very good, but i can't find the electronic version of it until now. :(
I will design 10-bit 10MSa/s cmos Pipeline adc. Which references will you suggest me ? How can i start my design? I need help who have experience in pipeline adc design. Give me advices about sub-dac, sub adc, and the other components in pipeline structure. Thanks
try "cmos Analog to digital and Digital to Analog converters" by Rud van Plassche.....u get basic ideas...also u get information about good reference papers on SA ADCs
You can also try "Understanding Data Converters" By Behzad Razavi. It contains a chapter about dac design. Also, you can try the following paper "A 10-bit 1-GSample/s Nyquist Current-Steering cmos D/A Converter" IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 3, MARCH 2001.
1. H. Kohno and Y. Nakamura et al., ?A 350-MS/s 3.3-V 8-bit cmos D/A converter using a delayed driving scheme,? in Proc. IEEE 1995 Custom Integrated Circuits Conf. (CICC), May 1995, pp. 10.5.1?10.5.4. 2. A. Marques and J. Bastos et al., ?A 12-bit accuracy 300 MS/s update rate cmos dac,? in Proc. IEEE 1998 Int. Solid State Circuits (...)
Hi ,everyone : Would anybody give me some advices or upload any matirial on AD/DA design with digital cmos process, single power supply
you can read Jacob Baker's book - cmos: Mixed-Signal Circuit Design, 30.2.1 The Ideal dac, it's built in Spice.
1)Can anyone help me to design 12 bit 100MHz pipeline adc? 2)How is the schematic for cmos opamp with Gain=4 3)How is the schematic for 8-to-3 priority encoder? I have design 2 bit flash could i test it?
First, it depends if you want to implement the Unit Current-Cell Matrix or the Binary-Weighted Array (conventional). For binary-weighted, this can achieve smaller silicon area, less transistors, high speed and it is optional to use decoders to drive current cells. It has linearity issues due to cmos process imperfection. dac of this kind coul
Reference the book cmos DATA CONVERTERS FOR COMMUNICATIONS chaper 12
hello ~~ can anyone share the PHD dissertation "cmos oversampled dac with multi-bit semi-digital filtering and boosted subcarrier SNR for ADSL central office modems",Andrew C. Y. Lin, thanks best regard
Jocab and Harry's cmos Analog Circuit Design, Simulation and Layout, Volume I and II (the whole book - volume II talks about ADC/dac)
Dear all, Do you read this paper? I have some questions about this paper. 1.How do the equation form? 2.If the full scale is 20mA, what is the I(LSB)?why? Thanks.
Dear all, I read this book " Kluwer - cmos Data Converters for Communications". I have some questions about equations. I don't know how to generate. Like below. Thanks.
Dear all, I read this book " Kluwer - cmos Data Converters for Communications". I have some questions about equations. I don't know how to generate. Like below. Thanks.
Dear all, I have a question.If my current dac has 10 or 12 bits, how do I choose how many bits are unary and binary? I see 8b+4b or 7b+5b for 12bits. How do I run yield v.s. standard deviation? I try use matlab. According "an accurate statistical yield model for cmos current-steering D/A converters", I use the formula of this paper. I can sh

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