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44 Threads found on edaboard.com: Cmos Regulator
CD4000 cmos logic is working over 3 to 15 V supply voltage range. There's however no logic IC family designed for 24 V supply.
PMOS LDOs always have a hard time with HF PSRR, any groundward jerk on the pass FET gate is directly amplified (common source amplifier). In normal cmos techologies ground parasitics are pervasive. You may need to look at compensation schemes (like, Miller makes it worse as any drain jerk - which would include + supply movement, relative to the f
Hi, The following pic shows cmos current to voltage converter (for DC-DC converters application),can any one help me to know the design steps and suitable opamp required?
By literature studies
Hello, Do you believe that the MCP1703 (sot89) 5v regulator can deliver 5V to a circuit which is pulling zero amps through it? (not loading it at all?) Figure 5 of the datasheet (fig 2-3) appears to suggest so. Its just that im using it to supply a few cmos chips and wonder if at start up, before much load current is being pulled, maybe the o
I need cmos implementation on TSMC90 nm technology for example.
Though i did not design the LDO for your specs..but the structure on cmos may look something like shown in figures attached. I used folded cascode opamp for error amplifier with output stage W/L chosen for 10mA output current. My supply voltage varies from 3.2V to 4.2V. obrazki
Hi, At present, I am learning about Switched-mode power supply and Low drop out regulator using cmos. Could anyone suggest some good books about this? The main problem here is "using cmos". Thanks.
Any good book or resource which discusses voltage regulator design in cmos technology
Hello, I would like to know the layout issues for a low dropout regulator (LDO) in cmos technology. Can you name a document which shows a schematic and the associated layout issues ( like minimizing parasitics and track resistance etc..) for the LDO ?? Thanks in advance.
Hi All, could please someone recommend me a book or a document with a compilation of basic analog building blocks in cmos, like for example: power on reset undervoltage detection voltage regulator 0scillator bias generator bandgap etc what I am looking for is not a theory book but a compilation of different topologies, if possible
A Low-Voltage, Low Quiescent Current, Low Drop-Out regulator,AN AREA-EFFICIENT cmos BAND-GAP REFERENCE CIRCUIT FOR LOW SUPPLY VOLTAGES,,,A Low Power VLSI Implementation for JPEG2000 Codec
I agree, that the unregulated DC/DC converter can be a problem, particularly because the sensitivity of the GM tube depends on the HV level. The logic ICs are standard cmos, I guess, and can manage an even higher supply level. A LDO regulator, e.g. LP2985-5.0 or -5.3 should do the job. It has only a low mV dropout voltage and a moderate current
Hello All, I want to design 12V-5V Unregulated I/P to 3.3V,1A Regulated O/P Linear Voltage regulator using cmos 0.6um Technology with Cadence tool. Can any one please suggest me correct Topology? I have knowledge of LDO but I am not sure for this problem LDO topogoly is suitable or what because Drop out voltage range is very big. Any re
Hi, I want this paper, could you help me if you have? Thanks for your kindly help in advance 1. A Low Noise cmos Low Dropout regulator with an Area-Efficient Bandgap Reference SUMMARY In a low dropout (LDO) linear regulator whose reference voltage is supplied by a bandgap reference, double stacked diodes increase the effective (...)
Dear cmos: it is not that simple. The voltage regulator can´t sink current, only source. When the relays are switched off the free whell diodes carry their current directly to the power supply, but it can´t sink this current. This means a voltage spike will happen that can affect the mcu operation. Regards
Hi to all ASM masters. Basically i am doing a project on wattmeter using PIC, LCD and other components like cmos voltage converter, 3.3V regulator etc. But when it comes to ASM, i headache. To be honest I am getting the asm source code from the web (here), and the latest is that the digital IO on RB6 and RB7 is enabled. However when I go through
A 9.953-12.5GHz 0.13μm standard cmos bondwire LC oscillator using a resistor-tuned varactor and a low-noise dual-regulator Maxim, A.; Turinici, C. Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 IEEE Volume , Issue , 11-13 June 2006 Page(s):4 pp. - 344 Digital Object Identifier 10.1109/RFIC.2006.1651161 Summary:Notice of Viol
In .18 process,there are some kinds of mosfet,for example,mos in 3.3V ,mos in 1.8V,can I use them in one circuit.thanks!
Hi, I need some reference voltages for a CIS chip. These references will also go off-chip, but has to be generated on-chip. Some of them are between the rails, but some aren't. The supplies are 0V for gnd and 3.3V for vdd. Transistors can work up to 6V. I need to generate a couple of references a little bit below 3.3V (say 2.7V) I need to g
Hi, everyone , what the below paper talk about ,. I have no account to download it from IEEE Full on-chip cmos low-dropout voltage regulator,? IEEE Trans. on Circuits and Systems ? I, pp 1879-1890, vol. 54, Issue 9, Sept. 2007
Hi, all I found this ckt in the following paper named Full On Chip cmos Low-Dropout Voltage regulator, which is at the following link.
In cmos or Bicmos RFIC design the power down mode is a typical design practice. In each circuit, each node is controlled (with cmos small switches) in order to assure that the circuit goes properly in power down. I hope it can help. Mazz
sorry, another question, your process is 5v cmos process, then what process that you use to design regulator which should have 15v input, thanks!
Hi, It means generated voltage is not with respect to voltage source(VDD & GND) used to generate it. You can refer chapter 11 of design of analog cmos integrated ckt by razavi. thanks,
you can use step up(boost converter) cnverter using oscilator that vork with 3volt such as cmos component. you can find this topology in any smps book.
Hello all, now I start to design a low quiescent current, low dropout voltage regulation with cmos processor, could you please tell me some structure of the buffer in ldo, the spec is wide bandwith, low quiescent and enough slew rate.
Hello The attached files is some papers and patents for current sensing in dc-dc converter which may be useful for you. Best wishes! 1 An Integrated cmos Current-Sensing Circuit for Low-Voltage Current-Mode Buck regulator Abstract?An integrated current-sensing circuit for low-voltage buck regulator is presented. The minimum (...)
Do it like this. You need a regulator to get stable output voltages, and you can use a cmos 555, whose output swings rail-to-rail.
Hi, I think cmos Circuit design and layout by jacob Baker, and design of analog circuit by Razavi is best for Bandgap reference design. Better to go through Baker for good theorectical understanding.
I want to use the buffer to drive PMOS pass device of regulator. does anyone know it or have papers? Thanks a lot and best regards
can you upload IEEE paper robust frequency compensation scheme for LDO regulators or A capacitor-free cmos low-dropout regulator with damping-factor .. or Single Miller Capacitor Frequency Compensation Technique for Low ... by the way , you make LDO by BJT or cmos process Added after 2 minutes:
cmos shunt regulator with bandgap reference for automotive environment IEE Proceedings - Circuits, Devices and Systems -- June 1994 -- Volume 141, Issue 3, p. 157-161 thanks
I design chip of switching step-down regulator. Its output voltage is from 1 to 5 volts and output current is up to 2 amperes. Is it possible to design switching step-down regulator with use of standard cmos technology ? Have you such experience ? I think isolated nmos and pmos is necessary for good noise rejection.
You can consider the low voltage bandgap: "a cmos bandgap reference circuit with sub-1v operation"
Specs for design: cmos tech forced to use Bandgap and a ballast to build up the simple regulator input 5V+/-20% output 2.5V +/=1% current <2mA Ro < 0.05 Ω Robg < 1 Ω temperature coeff kT < 500 ppm / °C Any design doc or school project report will be very helpful. thx for share!
Hello, I have been assigned a task to do a competitive study on very low jitter PLL's. The PLL has tight specs of 25ps peak-to-peak jitter in 0.13u digital cmos process. 1)How feasible is it? If I use ring-oscillator based VCO, can I meet these specs? How much we can achieve by using a separate voltage regulator for this VCO? 2) If I u
I am designing a utr-low quiescent current cmos LDO. To meet spec,the current source of OP(single stage) is only 0.4uA. When load current is 1mA,the parameters of regulator loop sre as following: P1:8Hz @Vout of OP P2:2KHz @Vout of LDO,load capacitor is 1uF,Resr=10m UGF:4KHz Phase Margin:22 Use compensation capacitor at the Vout of LD
from second edition in this book page 814 has a paragraph : ' in any practical regulator, a bypass capacitor is used to supply charge to the load for fast current transient...' 1. how to decide the bypass capacitor, is decided by transient speed? how to calculate this relationship ? 2 why the bypass capacitor can charge to the load ? t
Hi I find some cmos charge_pump usually use Vin=2.7~5 Vo=5.5v Io=100ma .. why have 2.7v limit ?? and if I want to design 1.2v -> 5.5v Io=100ma , how large size pmos switch will be use ? (assume cmos 5v 0.5um process ) someone tell me pmos need large reduce Rds_on .. but I use (20/0.5 )* 20 cmos switch I find Vo (...)
some LDO asic only work on < 10ua .. how to design it ? regulator need OPA + bandgap .. if bandgap total working current < 1u , cmos process design use BJT model (parasic device) can be use under such small current ( maybe BJT current < 100na ) ?? I don't think FAB have good spice model for BJT device ..
Use a down regulator to provide low DC voltage supply for cmos part.
1. direct use HiV mos + BJT but as I know some process BJT model have problem is HV 2. use 2 step regulator 40v -> ~12 then use 12v device make bandgap is easy than 40V cmos 40V cmos L is very large ... for good Line regulation need Long L what process in your design   UMC/TSMS/VIS or other ??
this is a very complex cmos switching buck boost regulator and is too dificult to model in spice an indication if the model is hard to make work is that national pan dont provide a generic spice3 model so maybe youll have trouble to model this chip....????....???!!!!