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Mmm...., i am not sure i'm right or not. Solving the combinational loop problem is not necessary if using vector-based simulation, but it had better be solved if adopting either STA or DFT in your flow. As to using disable timing command to break the timing loop, i never make it successfully through the whole synthesis process. Once the design is c
Is the output delay corresponding to input is permittable in the design? I guess its not , unless your design is sequential.. You can achieve the same results by using a combinational 16:1 Mux with 16 bit inputs and 4 bit select. But ur code needs to be changed. Please post ur NETLIST for omre comments.. rgds
THere is no concept of Asynchronous load in a register(except for the preset pin). so while synthesis DC considers QQ_set as a synchronous enable. but when QQ_set becomes one , there is no clock running so ur netlist simulation results are wrong. I dont understnad why the QQ_clock occurs non periodically. If you are gating the clock with a signa
You willl usally find this as a sequential logic because of the timing constraints of the memory ( usally memories don't operate at the speed of your digital logic) But if you are using SRAM then may be you could go for purely combinational logic . It all depends on the speed of your memory blocks please go through the data sheet of your memory the
The FSM contains sequential part and combinational part, but only combinational circuit description in your code. Your code style has another issue: racing condition. You should rewrite your FSM.
To the new designer, latch is always a problem in synthesis. Check your verilog code. If you have a combinational always block which has one condition branch, you will get latch in the synthesis. always @(a or b) begin if (a) out = b; // no else here will give a latch end So you can check your verilog code, and add a (...)
no acceptable for synthesis tools , to obey RTL design rule, using non-block in sequence logic and using block in combinational logic, else you will meet unnecessary problem.
assign r combinational statements .. whts the problem ?? why r u left with assign ??/
Sam hit it on the head. Synposys uses some confusing naming, but flattening is changing combinational logic into sum-of-products. Ungrouping removes heirarchy. Both can improve timing. Depending on the design they may reduce gate count.
Hi everyone... I'm getting a warning while i tried to synthesis a carry look a head adder in RTL complier. The warning say "Detected combinational arc in sequential cell". what does this mean. How can i correct it...? Thank you...
latch will be infered when a combinational circuit described improperly example: 1. when sensitivity list is not complete i.e all the combinational inputs must in sensitivity list 2. In always or process all the control paths are not evaluate the output
Hi Seanigang, combinational loops are broken by adding buffers with broken arc (i/p to o/p). It is done for timing purpose. RTL complier timing engine will does insert comb. loop breakers. There is not relationship with Comb. loop breaker with deletion of instance/signal/module. To control the deletion of instance pls use following attribu
The reported behaviour can be found with any HDL compiler, cause it is required to minimize the logic. Ring oscillators are regarded as useless delays. The below synthesis attributes are working with Altera Quartus, but should also help with other compilers. If not, consult the manual for specific syntax. Alternatively to synthesis attributes in HD
The feedback loop is not inferred but is purposly included.The tool that I am using is XST. How to constrain So that I will get the delay.
Hi, What is the problem with having combinational loops in our design. why do we break it while doing synthesis. Thanks
You can generate from synopsys DC a detailed report about how many flip flops and what kind of flip flops are used in your design. With the above info, you can't really tell how many flip flops are present in your design. That would be pure guess. If we would know that you dont have anylatches and RAM's, u can get the flip flip count by dividin
Hi Folks It's been almost 2 hours now, since I started my synthesis process !! .. I feel like there is a problem !! .. I was expecting a run time around 20 to 30 mins max. It's just synthesis !! .. not the complete Bit Generation process !!! I have a doubt regarding one thing .. in my design, I'm having one (VHDL) module that contains one big
Hi everybody! Does somebody has any idea concerning the following question: how will it influence the result design if I take combinational logic out of the clocked process? What are the differences in synthesis? Compare the following two implementations of count register as an example. 1st implementation with the addition inside the clock
Unused combinational logic will be removed automatically. There is a switch that will remove unused sequential logic. Depending on your tool version, the switch may be on or off be default.
I have a question. Will the synthesizer at this case use whatever is present in the library and add some combinational logic before to the DFF to simulate the preset and clear functionality. I find it logical. Any comments? -- Amr Ali
I am having trouble synthesizing blocking statements. I have a model MIPS processor and I am trying to introduce bugs to the processor. I am working with behavioral Verilog and synthesizing/compiling it with Synopsys Design Compiler. I am using ModelSim to check both the behavioral and structural code. I have attached two files. The original and bu
Please refer to the attachment for the equivalent hardware for the verilog provided above. The exact gate count depends upon the mapping library used. Suppose of the corresponding synopsis library has flip flop with synchronous reset, the synthesis just reports one flop. Otherwise, the it reports a flop, and gate count required to map the MU
Hi could you let me know why you want to synthesize a combinational logic to only nand or nor gates. To be honest, I‘ve never try to do so. But, according to ERRORS from DC, I think It means that, DC can not MAP(translate GETCH LIB to STD CELL)only with the cells in the saed90 library do not have the dont_use property. W
For a combinational process, every signal that is assigned to, must be assigned to in every branch of If-Then-Else statement and Case statement. Why?
Following is a segment of a Verilog code I'm trying to synthesize. adder_ks16 ks16_2(c_out, ,notoutAcc,SADmin,1'b0); always @(posedge c_out or posedge signal_m) begin if(signal_m == 1) SADmin <= 16'b1111_1111_1111_1111; else //#1 SADmin <= regAcc;
Halo, I'm having some trouble with synthesizing a design using a T flip flop with multiple outputs. The T flip flop has both a sequential and a combinational output, where the combinational output acts as an enable for subsequent T flip flops when they are used in a counter design. RTL Compiler gives the following warnings and fails to use the c
Hi, When I am doing synthesis - the following warning is coming. "Sequential instance os_ig_init_isto has been reduced to a combinational gate by constant propagation". Can you pls explain me what is the reason for this? Is this warning is ignorable?
hi all, after the synthesis, i can see this values at the end of the synthesis report Minimum period: 9.079ns (Maximum Frequency: 110.139MHz) Minimum input arrival time before clock: 4.806ns Maximum output required time after clock: 3.554ns Maximum combinational path delay: No path found what do these lines in the (...)
when using sequential code to design combinational logic in vhdl if completle truth table is not defined ,the synthesis tool implement______________which is not requried 1.clock buffer 2.buffer 3.flip flop 4.latch
Surely , you need to know some basics about the following topics : Karnaugh maps and realization of digital circuits constructing truth tables combinational and sequential circuits timing analysis and set-up/hold timing requirements then have a look on one of the tutorials available online and make sure you get the following : how to define your
THIS IS FINAL synthesis REPORT OF MY DESIGN. iT HAS"a" AS ITS INPUT,but it's taking a as clock,Dont knw WHY.PLS HELP. SECONDLY,if the same design(which took input as clock,on its own) without clock gives, timing report as Minimum period as well as Maximum combinational path delay,IS THE REPORT CORRECT?? Clock Information: --------------
In fact there's no other problem than getting an obviously inappropriate combinational loop warning. It must be considered as a restriction of the synthesis tool that is particularly designed to analyze asnychronous logic. Altera Quartus has the same problem here, by the way. The normal way is to ignore some warnings. I don't think that anybody
I'm getting the following timing summary from the synthesis: Timing Summary: Speed Grade: -1 Minimum period: 9.982ns (Maximum Frequency: 100.180MHz) Minimum input arrival time before clock: 4.597ns Maximum output required time after clock: 4.364ns Maximum combinational path delay: 2.788ns I want to improve that, is there a way to
brasilino, Dont't get confused by the term "reg". When verilog was developed originally it was meant to be only register. But later the verilog LRM redefined its meaning to be just a variable that can be used to model either a register or latch or gates. Pasting here a detailed post on that
Hi, do you know if DC allows you to find the RTL segments that synthesize into the critical path? I am not talking just about the start-stop registers of the path, but also the RTL that synthesizes into the combinational gates that comprise the critical path. Ideally also with the state of the RTL inputs, plus the event that trigge
hi, I have a module which is such that module code3b (o, a, nrst, en); output o; input a, nrst, en; reg o; always @(a or nrst or en) o = latch(a, nrst, en); function latch; input a, nrst, en; if (!nrst) latch = 1'b0; else if (en) latch = a; endfunction endmodule Will this infer a latch or a combinational logic, as I
I am not familiar with ASIC design flow, maybe somebody else can give some valuable comments.... For FPGA design, what I have used synthesis tools(only to synthesis VHDL code): Synplicity Synplify > Synopsys FPGA Compiler II > Mentor Leonardo Exemplar It is only my personal opinion...
This program is written to provide an ease in the quasi-static analysis/synthesis of SYMMETRIC CPS lines based on conformal mapping method. It is able to take care the finite thickness of the dielectric used and provides the option of including the effect of metallization thickness.
Hi PPP is a Web-based environment for Low-Power Design. Its Graphic User Interface is a set of dynamically generated HTML pages that can be accessed through any Web-browser. Three sets of tools are available: synthesis for low-power, Power Optimization and Power Simulation. File Transfer utilities are also available to upload input files and dow
Hi These materials are made available for ECE 4170: Introduction to HDLs with Applications to Digital Design taught during the Spring 2000 Semester at Georgia Tech. This text focuses on presenting the basic features of the VHDL language in the context of its use for both simulation and synthesis. Basic language concepts are motivated by fami
Problem is from your large combinational logic for sure, check your own code and synthesis result, analyze your critical path, you can make it.
Hi, I have uptil now synthesized my designs using push-button interface of Leonardo Spectrum. I need some good referencing information so as to get aware of its importance and write efficient scripts. Thanks.
Anyone having expertise in High Level synthesis? Can you please help me and others in being upto date. Thanks
Does anybody have Synopsys ACS (Advanced Chip synthesis) ready made Scripts, and Flow Tutorials ? Thanks in Advance for your help !
Incentia Design Systems -> designCraft Monterey Design System synplicity ASIC Have anyone can compare it with Synopsys DC ??
hope it is helpful.
After synthesis and optimization of my verilog file, I find some net( or wire) names is very strange. For example , the net connected from the output of nor gate to the data input of D flip-flop is called " *cell*11/U2/control ". But I want very short net name like " N100" . Does anyone know the answer to this question ? Cyteng
Hi all here is the Microsoft power pont presentation for RTL synthesis. -avinashr :P
Hi all, I need a good post synthesis simulation tool for fpga designing. I also need a good test generator, but i don't know what is the best.
Hi all, i have a question about using synopsys DC, as i give constrain and optimal condition of a verilog design file, then i synthesis it. it has been mapped into gates, right? so i can see the slack timing report . But if i start synthesis the mapped gated netlist again without modify any constrain, and report timing again, then i ge