Search Engine

Combinational Synthesis

Add Question

50 Threads found on Combinational Synthesis
Because you have the following problem in your code: process(clk,rst) begin if(rst = '1') then -- reset code elsif(clk'event and clk='1') then -- clock code end if; -- more code that is now combinational a <= std_logic_vector(unsigned(b) + unsigned(c)); end process; fibo_series <= c;
The circuit implements a combinational latch by specification, including an unknown initial state. It's exactly corresponding to the Verilog description.
I can only answer it at a very top- (concept-) level. In order to reduce the negative slack, try to reduce the combinational logic between two the two registers (flip-flops). Or adding a pipeline can also be a solution. If your design is big, try out 'incremental compilation' to achieve timing closure for a particular partition that does not
i want a verilog code for the following logic in post synthesis simulation when e = 1, output = 1 when e = 0, output = 0 when e = x, output = 1 I have tried casex and many more things but nothing is working in post synthesis simulation.Anyone tell me a verilog code to get the following logic.If possible, try to avoid using registers.use mor
hi, I have a module which is such that module code3b (o, a, nrst, en); output o; input a, nrst, en; reg o; always @(a or nrst or en) o = latch(a, nrst, en); function latch; input a, nrst, en; if (!nrst) latch = 1'b0; else if (en) latch = a; endfunction endmodule Will this infer a latch or a combinational logic, as I
You are also mixing = (blocking) and <= (non-blocking) assignments. You should stick with only using blocking assignments in combinational always blocks (always @*) and non-blocking in sequential always blocks (always @ (posedge some_clock)). Mixing them can result in synthesis/simulation mismatches. Pretty much
Hi, do you know if DC allows you to find the RTL segments that synthesize into the critical path? I am not talking just about the start-stop registers of the path, but also the RTL that synthesizes into the combinational gates that comprise the critical path. Ideally also with the state of the RTL inputs, plus the event that trigge
well you did not find false path. your synthesis has some timing issue, so two possibilities: 1- the designer claims this path is false, so you could add this path to false in your SDC. 2- the designer claims this path is true, then you have a timing issue, to solve by pipeline or rewrite RTL to push combinational logic before or after flops.
No issue after I added a fa.vhd file to the design. You do know this is a very large combinational circuit. Using Vivado it ends up with >60 levels of logic (LUTs) from a_in to y. Of course I didn't add any constraints to try and improve the timing. e.g. 105366 Regards
Hi, is there a way to constrain DC to keep all the signal names from RTL to netlist (the ones that are not removed during synthesis) ? I am particularly interested in combinational outputs. The purpose is to facilitate gate level simulations debugging. Currently, I can only find registers output names. All the combinational outputs get
Hi guys, Ive designed 5 models of squarers and wish to compare propagation delay, area and power consumption. For delay, is putting a marker at input and then at stable output and getting the difference the correct way of doing this. Also, what is maximum combinational delay which is given in the synthesis report. Area, is number of slices and L
VHDL statements don't take "time to execute" because in the generally case each statement describes independent hardware elements, e.g. registers and combinational logic. The delay between registers or in- and outputs in a particular data path has to be considered however. VHDL synthesis tools perform timing analysis to guarantee correct operat
HI everyone , when will Pre synthesis and post synthesis come in ASIC Design flow? when will Pre validation and post validation come in ASIC Design flow? why should we need pre and post (synthesis and validation ) ? what is difference between validation and testing ? when should we neglect STA in ASIC Design flow ? (...)
Hi all, I am trying to synthesize the following verilog module using synplify_pro module poissonEncoderWithLFSR(clk, set, next, seed, dataIn, encOut); parameter NUM_BITS_IN = 12; parameter NUM_BITS_LFSR = 8; input clk,set,next; input seed; input dataIn; output reg encOut;
Hi All, I am trying Synopsys dc tool for synthesizing my design. I tried different operating frequencies and observed the design area. Normally area should increase with increasing operating frequency but in my case design area for 220 MHz is somewhat greater than the area at 240 MHz. How is it possible?? combinational area for 240 MHz is gre
I'm getting the following timing summary from the synthesis: Timing Summary: Speed Grade: -1 Minimum period: 9.982ns (Maximum Frequency: 100.180MHz) Minimum input arrival time before clock: 4.597ns Maximum output required time after clock: 4.364ns Maximum combinational path delay: 2.788ns I want to improve that, is there a way to
I have two combinational blocks, fnA.vhd and fnB.vhd. I have a higher level of hierarchy, test.vhd, which instantiates these two functions, and also infers a clocked register, each with an input mux. There it a top-level port, contrlAnotB, that drives the control inputs to all three muxes. If input port contrlAnotB = 1, then the output of fn
I am new to the system verilog. Blocking statements can be used for combinational circuits and non blocking statements can be used for sequential circuits. But i don't know the reason behind using the use blocking and non blocking. Please help me.
That is a very interesting post. Can you post your multiplier code before and after the retiming.I am wondering is it purely combinational or both combinational + sequential code? When you say compile, what tool are you using to compile the design?
when using sequential code to design combinational logic in vhdl if completle truth table is not defined ,the synthesis tool implement______________which is not requried 1.clock buffer 2.buffer 3.flip flop 4.latch
Minimum period: 8.900ns (Maximum Frequency: 112.360MHz) Minimum input arrival time before clock: 6.670ns Maximum output required time after clock: 4.283ns Maximum combinational path delay: No path found DO these values depend on the FPGA family's selected in xilinx or they are independent of the FPGA families
Asynchronous latches are mostly implemented as "logic loop", feeding back a combinational LE's output to an input of either the same LE or a different one. synthesis tools are often warning about latch synthesis, but they are obviously required in some cases, e.g. as address latches for an asynchronous multiplexed data bus. The most (...)
So is this done for some readability reason, or does something different actually happen during synthesis? As far as I know it gives the same synthesized results, and it's mostly done for readability. And also to split combinational and synchronous logic. See for
Each functional call will be synthesized as a separate combinational logic block.
gmish27, A Finite State Machine is just an abstraction to ease sequential/combinational logic design and synthesis. Of course you are not obligated to work out sequential/combinational logic by state-machines approach, but it is usually easier and clearer. Regards, Regnum
For a combinational process, every signal that is assigned to, must be assigned to in every branch of If-Then-Else statement and Case statement. Why?
hi, A sequential design with clock is RTL and a combinational design is gate level.
I am having trouble synthesizing blocking statements. I have a model MIPS processor and I am trying to introduce bugs to the processor. I am working with behavioral Verilog and synthesizing/compiling it with Synopsys Design Compiler. I am using ModelSim to check both the behavioral and structural code. I have attached two files. The original and bu
Mealy and Moore state machines are most famous. They can be encoded in 1 combinational process and 1 sequential process, or 2 sequential processes and 1 combinational process. -- Amr
I have a question. Will the synthesizer at this case use whatever is present in the library and add some combinational logic before to the DFF to simulate the preset and clear functionality. I find it logical. Any comments? -- Amr Ali
Unused combinational logic will be removed automatically. There is a switch that will remove unused sequential logic. Depending on your tool version, the switch may be on or off be default.
Hi everybody! Does somebody has any idea concerning the following question: how will it influence the result design if I take combinational logic out of the clocked process? What are the differences in synthesis? Compare the following two implementations of count register as an example. 1st implementation with the addition inside the clock
Not in synthesis, cause FFs triggered at both edges don't exist, except in some CPLD families. There are replacements, that utilize two FFs and combinational logic. See a link in in one of the various same topic edaboard threads.
Hi, What is the problem with having combinational loops in our design. why do we break it while doing synthesis. Thanks
I have a requirement that: a certain net should have only one trace path in a single timing path. ex: for combinational logic F = s ? a: a&b; I want the net 'a' to have only one trace in a single timing path. If DC map F to a MUX and a AND, then from 'a' to 'F' there exist 2 trace paths. I don't want this. I want DC map 'F'
I have one basic question about combinational logic To implement any combinational logic, what is the minimum set of logic gate? Why there are so many types of standard cells in the library? Thank you!
The feedback loop is not inferred but is purposly included.The tool that I am using is XST. How to constrain So that I will get the delay.
after synthesis of any code...max combinational delay is calculated by iSE 6.2 vhdl. in which gate delay is give.for the same device i have synthesized the code on ISE 6.1 and ISE 9.1.but the gate delay is differrent for the same device......can any one help me...whts the prob?????
Hi everyone... I'm getting a warning while i tried to synthesis a carry look a head adder in RTL complier. The warning say "Detected combinational arc in sequential cell". what does this mean. How can i correct it...? Thank you...
first u should know why remove glitch? some glitch don't arise problem, and all combinational logic has glitch.
First approch is just taking one substractor and second approch is taking comparator. First approch is taking less combinational delay than second one. So I will also go for First approch.
cycle stealing occurs when combinational logic is moved from one clock phase to another in order to equalise latch-to-latch signal delays throughout a latch based design having multiple latch-to-latch stages.synthesis tools may have the ability to automatically perform cycle stealing during optimization.
in fact, you'd rather use control signals as condition to control the state transition. And write the combinational logic and sequential logic code in one always block, then you are not afraid that you omit the sensitive signals
Basic DFT rules include: ( I remember only these) 1. Clock & data should not change at same time. 2. No combinational loopbacks 3. Clock should not feed data input.
no acceptable for synthesis tools , to obey RTL design rule, using non-block in sequence logic and using block in combinational logic, else you will meet unnecessary problem.
You mean simulation by using Modelsim and synthesis by using DesignCompiler. If you write your code in a standard manner, you will not have major problems. I recommend you to write your code in a standard way in which you separate combinational and sequential parts based on Huff-man model of a digital design. By the way, timing verifiation is the
The FSM contains sequential part and combinational part, but only combinational circuit description in your code. Your code style has another issue: racing condition. You should rewrite your FSM.
This style prevents combinational logic from spanning module boundaries. Then your timing constrain is clearly constraint on the path between clock and not necessay to consider input_delay.
Is the output delay corresponding to input is permittable in the design? I guess its not , unless your design is sequential.. You can achieve the same results by using a combinational 16:1 Mux with 16 bit inputs and 4 bit select. But ur code needs to be changed. Please post ur NETLIST for omre comments.. rgds
do I need to break combinational feedback loop at all conditions? How can i break combination feedback loop.What do the command set_disable_timing do to the combinational ciucuit in DA? thanks!!!