Search Engine www.edaboard.com

Combinational Synthesis

Add Question

129 Threads found on edaboard.com: Combinational Synthesis
Mmm...., i am not sure i'm right or not. Solving the combinational loop problem is not necessary if using vector-based simulation, but it had better be solved if adopting either STA or DFT in your flow. As to using disable timing command to break the timing loop, i never make it successfully through the whole synthesis process. Once the design is c
Is the output delay corresponding to input is permittable in the design? I guess its not , unless your design is sequential.. You can achieve the same results by using a combinational 16:1 Mux with 16 bit inputs and 4 bit select. But ur code needs to be changed. Please post ur NETLIST for omre comments.. rgds
THere is no concept of Asynchronous load in a register(except for the preset pin). so while synthesis DC considers QQ_set as a synchronous enable. but when QQ_set becomes one , there is no clock running so ur netlist simulation results are wrong. I dont understnad why the QQ_clock occurs non periodically. If you are gating the clock with a signa
This style prevents combinational logic from spanning module boundaries. Then your timing constrain is clearly constraint on the path between clock and not necessay to consider input_delay.
You willl usally find this as a sequential logic because of the timing constraints of the memory ( usally memories don't operate at the speed of your digital logic) But if you are using SRAM then may be you could go for purely combinational logic . It all depends on the speed of your memory blocks please go through the data sheet of your memory the
The FSM contains sequential part and combinational part, but only combinational circuit description in your code. Your code style has another issue: racing condition. You should rewrite your FSM.
To the new designer, latch is always a problem in synthesis. Check your verilog code. If you have a combinational always block which has one condition branch, you will get latch in the synthesis. always @(a or b) begin if (a) out = b; // no else here will give a latch end So you can check your verilog code, and add a (...)
no acceptable for synthesis tools , to obey RTL design rule, using non-block in sequence logic and using block in combinational logic, else you will meet unnecessary problem.
in fact, you'd rather use control signals as condition to control the state transition. And write the combinational logic and sequential logic code in one always block, then you are not afraid that you omit the sensitive signals
assign r combinational statements .. whts the problem ?? why r u left with assign ??/
Sam hit it on the head. Synposys uses some confusing naming, but flattening is changing combinational logic into sum-of-products. Ungrouping removes heirarchy. Both can improve timing. Depending on the design they may reduce gate count.
Hi all. I've run a synthesis using design compiler. In the log file, it says that timing loop is detected. After i do a report_timing -loop, it shows that there are 4 timing loops. I thought that after compile, DC will automatically located the timing loops and by disabling timing arc between pins 'CK' and 'Q', it will actually break the timing l
Hi everyone... I'm getting a warning while i tried to synthesis a carry look a head adder in RTL complier. The warning say "Detected combinational arc in sequential cell". what does this mean. How can i correct it...? Thank you...
latch will be infered when a combinational circuit described improperly example: 1. when sensitivity list is not complete i.e all the combinational inputs must in sensitivity list 2. In always or process all the control paths are not evaluate the output
Hi! During synthesis using RTL Compiler, combinational loops were found in my design. As what the log file says, the tool disabled them, deleted several hierarchical instances, then added loop breakers. I've simulated the generated netlist and found errors on the output waveform. Now, my questions are : -What happens to the actual hardware/schem
The reported behaviour can be found with any HDL compiler, cause it is required to minimize the logic. Ring oscillators are regarded as useless delays. The below synthesis attributes are working with Altera Quartus, but should also help with other compilers. If not, consult the manual for specific syntax. Alternatively to synthesis attributes in HD
The feedback loop is not inferred but is purposly included.The tool that I am using is XST. How to constrain So that I will get the delay.
I have one basic question about combinational logic To implement any combinational logic, what is the minimum set of logic gate? Why there are so many types of standard cells in the library? Thank you!
I have a requirement that: a certain net should have only one trace path in a single timing path. ex: for combinational logic F = s ? a: a&b; I want the net 'a' to have only one trace in a single timing path. If DC map F to a MUX and a AND, then from 'a' to 'F' there exist 2 trace paths. I don't want this. I want DC map 'F'
Hi, What is the problem with having combinational loops in our design. why do we break it while doing synthesis. Thanks
Hi I am facing a warning which says "The following signals form a combinatorial loop". I am trying to build a combinational circuit (this is a part of a complete FSM ie a different process and will not have a clock interface). Here I am using a statement like : Sum:= Sum + Const; where Sum is a variable. I think the combinat
You can generate from synopsys DC a detailed report about how many flip flops and what kind of flip flops are used in your design. With the above info, you can't really tell how many flip flops are present in your design. That would be pure guess. If we would know that you dont have anylatches and RAM's, u can get the flip flip count by dividin
Hi Folks It's been almost 2 hours now, since I started my synthesis process !! .. I feel like there is a problem !! .. I was expecting a run time around 20 to 30 mins max. It's just synthesis !! .. not the complete Bit Generation process !!! I have a doubt regarding one thing .. in my design, I'm having one (VHDL) module that contains one big
Hi everybody! Does somebody has any idea concerning the following question: how will it influence the result design if I take combinational logic out of the clocked process? What are the differences in synthesis? Compare the following two implementations of count register as an example. 1st implementation with the addition inside the clock
Unused combinational logic will be removed automatically. There is a switch that will remove unused sequential logic. Depending on your tool version, the switch may be on or off be default.
I have a question. Will the synthesizer at this case use whatever is present in the library and add some combinational logic before to the DFF to simulate the preset and clear functionality. I find it logical. Any comments? -- Amr Ali
I am having trouble synthesizing blocking statements. I have a model MIPS processor and I am trying to introduce bugs to the processor. I am working with behavioral Verilog and synthesizing/compiling it with Synopsys Design Compiler. I am using ModelSim to check both the behavioral and structural code. I have attached two files. The original and bu
Please refer to the attachment for the equivalent hardware for the verilog provided above. The exact gate count depends upon the mapping library used. Suppose of the corresponding synopsis library has flip flop with synchronous reset, the synthesis just reports one flop. Otherwise, the it reports a flop, and gate count required to map the MU
Hi could you let me know why you want to synthesize a combinational logic to only nand or nor gates. To be honest, I‘ve never try to do so. But, according to ERRORS from DC, I think It means that, DC can not MAP(translate GETCH LIB to STD CELL)only with the cells in the saed90 library do not have the dont_use property. W
For a combinational process, every signal that is assigned to, must be assigned to in every branch of If-Then-Else statement and Case statement. Why?
if i have a circuit block , and i want to write VHDL code to describe it i can write the code in either concurent statements or sequential statements. but from the synthesis view , which of them is better. thanks in advance
Following is a segment of a Verilog code I'm trying to synthesize. adder_ks16 ks16_2(c_out, ,notoutAcc,SADmin,1'b0); always @(posedge c_out or posedge signal_m) begin if(signal_m == 1) SADmin <= 16'b1111_1111_1111_1111; else //#1 SADmin <= regAcc;
Halo, I'm having some trouble with synthesizing a design using a T flip flop with multiple outputs. The T flip flop has both a sequential and a combinational output, where the combinational output acts as an enable for subsequent T flip flops when they are used in a counter design. RTL Compiler gives the following warnings and fails to use the c
Hi, When I am doing synthesis - the following warning is coming. "Sequential instance os_ig_init_isto has been reduced to a combinational gate by constant propagation". Can you pls explain me what is the reason for this? Is this warning is ignorable?
A side remark about reading warnings or error messages. Besides all code oddities, that have been analyzed by xtcx in detail, it's confusing at first sight, that the tool complains about combinational loops, although the rising_edge() construct seems to demand FFs. To solve the riddle, you need to start reading in the middle of
hi all, after the synthesis, i can see this values at the end of the synthesis report Minimum period: 9.079ns (Maximum Frequency: 110.139MHz) Minimum input arrival time before clock: 4.806ns Maximum output required time after clock: 3.554ns Maximum combinational path delay: No path found what do these lines in the (...)
Minimum period: 8.900ns (Maximum Frequency: 112.360MHz) Minimum input arrival time before clock: 6.670ns Maximum output required time after clock: 4.283ns Maximum combinational path delay: No path found DO these values depend on the FPGA family's selected in xilinx or they are independent of the FPGA families
when using sequential code to design combinational logic in vhdl if completle truth table is not defined ,the synthesis tool implement______________which is not requried 1.clock buffer 2.buffer 3.flip flop 4.latch
Hi all, I want a circuit which will combinationally divide a number by 3.(or in one cycle :idea:) whats is given is that number will always be divisible by 3 only.:razz: post any tutorial link or any helpful I couldnt find any moderate one.
Surely , you need to know some basics about the following topics : Karnaugh maps and realization of digital circuits constructing truth tables combinational and sequential circuits timing analysis and set-up/hold timing requirements then have a look on one of the tutorials available online and make sure you get the following : how to define your
THIS IS FINAL synthesis REPORT OF MY DESIGN. iT HAS"a" AS ITS INPUT,but it's taking a as clock,Dont knw WHY.PLS HELP. SECONDLY,if the same design(which took input as clock,on its own) without clock gives, timing report as Minimum period as well as Maximum combinational path delay,IS THE REPORT CORRECT?? Clock Information: --------------
In fact there's no other problem than getting an obviously inappropriate combinational loop warning. It must be considered as a restriction of the synthesis tool that is particularly designed to analyze asnychronous logic. Altera Quartus has the same problem here, by the way. The normal way is to ignore some warnings. I don't think that anybody
I'm getting the following timing summary from the synthesis: Timing Summary: Speed Grade: -1 Minimum period: 9.982ns (Maximum Frequency: 100.180MHz) Minimum input arrival time before clock: 4.597ns Maximum output required time after clock: 4.364ns Maximum combinational path delay: 2.788ns I want to improve that, is there a way to
Hi All, I am trying Synopsys dc tool for synthesizing my design. I tried different operating frequencies and observed the design area. Normally area should increase with increasing operating frequency but in my case design area for 220 MHz is somewhat greater than the area at 240 MHz. How is it possible?? combinational area for 240 MHz is gre
Hi, How do you know it's been programmed properly? Look at this comments I added some time ago If it's been configured then start for somethign simple, just create a design with no FFs, only combinational logic, a couple of LEDs on an OFF when you toggle a swi
max(Tpd)Thold-Tczq+Tskew Tpd:the delay of the combinational logic between of two FF; Tstp:the setup time of FF Thold:the hold time of FF Tclk: the period of clock Tskew:the clock skew of clock Tczq:propagation delay of FF,time from arrival of clock signal till change at FF output.
for combinational logic usually blocking assignments are used...though non blocking assignments will work properly..
hi members,there is a dft question about the section in the book: advanced asic chip synthesis,using snopsys design compiler,physical compiler and prime time. at the section :8.3.8 Logic Un-Scannable due to Memory Element the author suggests that shortcircuiting all the inputs feeding the RAM to the outputs of the RAM, thro
use report_timing -to end_point then DC will list the path was passed through what combinational cell.
1)what kind of circuits will be synthesized into? module aa(ck, r1, r2) input ck; output r1, r2; reg r1, r2; always @(posedge ck) begin r1<=r2; r2<=r1; end endmodule 2)waht kind of combinational circuits will be sythesized into? module bb(a, b, x) input a, b; output x; reg x; always@(a or b)begin x=func(a,b); end function func; in