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33 Threads found on edaboard.com: Comparator Common Mode
That circuit cartoon provides no common-mode authority for the inputs. Where are they sitting "naturally" and is that within the proper-function common mode range spec? If this is a single supply comparator, does it work with both inputs near ground (neg supply)? An NMOS-input design would not, the input (...)
Hello, I need to design a differential comparator with maximum of 100V common mode range, with 200mV is hystersis, AC coupled, 10KHz Bandwidth. This is to detect pulse inputs. It would be great help if anyone can suggest design steps. Thanks in Advance!
This probably involves the underdrive/overdrive of the inputs. Inspect the common mode, pre- and post-transition difference voltages. comparator transient performance specs are often quite specific about how "wound up" the front end is initially and how much past null the input transition goes, which affects the degree to which the front (...)
Hi, Don't bother about the center tap voltages. On the receiver side it is just used to bias the inputs, so that the voltages keep within the common mode voltage of the receiver comparator. On the transmitter side it is useless somehow (for totem pole outputs). Maybe the drivers use open collector output stages.. Terminating resistors (...)
Hai all, I am designing a dynamic comparator, how can I measure the kickback noise in its input? Is there any circuits for that?
On page 4 of the LMV761 comparator datasheet , it says that input common mode range is "MAX -0.3V 1.5V" ...What does this mean?.....does it mean that the input common mode range is from 0.3V below ground to 1.5V below the supply rail? (assuming a single supply) LMV761 Datasheet...
Hi, you are absolutely right.. common mode range id the range of input DC voltage for that all the mosfets are in saturation (except the switches). And your test setup is correct.. and no need to give a DC voltage for the operation.. for example, if you are going to use it as a comparator means... you give a reference voltage in one input (...)
Waht you obserev is the limited common mode range of the LVDS receiver. It's not designed as a comparator with rail-to-rail input range.
That looks like you've got ground-related noise. The good news is that the noise is not causing your comparator to have false triggers. It's worth noting that your noise doesn't appear to be common-mode-(the noise is not the same on both + and - inputs). I would check your circuit grounding (as well as your scope grounding-a lot of times (...)
Hello, I'm currently doing my first "real" cmos design for fabrication (0.5um 5V onsemi). One of the main building blocks of my project is a rail-rail high speed comparator. I've done some rough simulations using a typical complementary input stage, and I find that it does work rail to rail, but the gain and speed are significantly reduced when Vcm
I'm not convinced that linearity is the reason: it is the first stage of a high-speed comparator! Also, this topology would reduce the common mode rejection. A main difference with respect to a simple differential stage is that this one allows to have a controlled offset by means of Vref+ and Vref-. Maybe this is the reason? Regards Z
If you have a real-time ramp comparator then this is common. Everything's too dirty when the output stage is switching. You really want a state machine that has only one direction to "ratchet". This is probably what your RS latch refers to, but there's probably more to it than just that.
The comparator is working fine at ambient temperature and also from temperature range 70°C to -20°C.But Temperature above -20°C its not working properly i.e comparator output will be always low(comparator o/p pin is given to CPLD pin). Note: What you mean to say, is that it's not working properly for temperatu
Hi, recently I read the paper"Design Techniques for High-Speed, High-Resolution comparators", and confused about this"Of course, the dc coupling at the input of an OOS comparator limits the common-mode range. Also, in applications where a large differential reference voltage must be stored in the comparator, (...)
LVDS receivers have an analog comparator type front end (for common mode rejection and gain) which will burn some power. Power is needed for speed. You might look for some older and lower speed versions if you're only running RS-232 baud rates. Seems like the intermediate RS-232 to LVDS layer is a waste of material and power, when (...)
I have an input sinusoidal signal going -1V to 1V. There is no common mode in it, how can i apply it to hysteresis comparator with needed hysteresis =50mV.
Hi Paul, If your circuit dont have an stand alone supply: Interesting dreams! :-) Otehrwise, its a good job for an Instr.Amp with high common-mode input range(has an input attenuator system) & a comparator, and you should place the LED on its output... K. Added after 8 minutes: INA117, refer to figur
Hi, I came across this multi-stage comparator circuit. Is anybody familiar with this structure? What is the purpose of the cross-coupled nmos load (M3, M4) under the diff pair? Also, what is the purpose of M6~M11? What is the advantage of this structure? Thanks!
The input is close to ground, what type of CMOS amp or comparator can handle this?
Hi guys, I have two differential input signals (Vinp Vinn) (Vrefp Vrefn) centered around 900mV common mode. I need to amplify the differential difference of these two signals . That is (Vinp + Vrefn) - (Vinn + Vrefp). Can differential difference amplifier be used . How much offsets do these amplifiers typically have for a 0.18um process w
Consider a simple first order single ended sigma delta modulator (RC integrator). Being single ended one terminal of the RC integrator and comparator sits at the common mode level. Being a dc signal it causes spurs in the o/p spectrum. Is there a way of resolving this without going to a differential circuit? Excluding dithering.
Hi, all I'm confused with below two BJT circuit. These are simple comparator, and of cource upper circuit has higher gain. But I cannot understand intuitively in case of BJT. Does anyone clarify this? thanks.
simply speaking, you need to create an output CM voltage detector. the detected output CM voltage then needs to go to a "comparator" because you want to know "is it pretty close to the desired CM voltage or not." then, you need to make a negative feedback loop so that when the output CM voltage is changed, there is a mechanism to bring the CM volta
hi, all, i want to get this paper. pls uploaad it if you have. many thanks! A Low Input Offset Voltage comparator with Wide common mode Input Range and Small Delay Title; A Low Input Offset Voltage comparator with Wide common mode Input Range and Small Delay Author;YAMADA (...)
Hi gurus, Attached is the schematic of a high voltage comparator. The reference voltage is 10v, the Vin changes widely from 4V to 10V. All the transistors are high voltage transistors which means that the Vds can sustain as high as 40V. However, there is serious reliability problem. When Vin changes, the Vcm normally follows. So the V
The input is a triangular wave, but the outputs are quite strange. Any one who can give me some advices on what is wrong? Thanks!
The comparator uses pmos input diff pairs. Thanks.
i am have to do a sar adc project the input is differential and the comparator must be fully differential does any one have material about a differential dac or can explan to me how it works
Hi, Maybe we can use mirror pmos'size and use resistor to transfer the voltage. Use comparator's output to control pmos's gate voltage. Do you have any simple methods? If you know , please teach me . Thanks. Do you know line driver of DAC and common mode feedback? If you has any information or data, can you let me know? I want to (...)
I agree with jiangnancai that getting 20ns with 10uA power consumption for continue time comparator is impossible. I had 200ns with 20uA on CMOS0.6, but this comparator uses feedback current comparator at the OTA output. Using feedback current comparator allow to improve propagation delay. But it seems to me that 20ns (...)
OK give me also a try: 1. Use a bandgap VBDG=1.2V 2. At chip startup sample the ratio of VDD/2 to VBDG by using a opamp and a ladder network. 3. Use a comparator which compares the scaled VBDG with VDD/2 4. Use binary search to fix the scale factor 5. Finish the initial calibration. So the scale factor multiplies the VBDG to V
I have met the problem when design the differential receiver used in USB 1.1 Transceiver,according USB 1.1 spec, the differential sensitive is 200mV ,and common mode range is 0.8 to 2.5V (include dierential range). So the comparator is needed to compare the (v2-v1) and 200mV, I used the two differential pair to realize (...)
I don't have Allan's book, so I don't know exactly what is your comparator (maybe you can post it...). Anyway it does not make sense that you don't have the correct operation with a sampled signal. Probably there is something wrong with your testbench. Is the input common-mode voltage in place? What happens: you (...)