Search Engine

Comparator Dynamic Power

Add Question

9 Threads found on Comparator Dynamic Power
Is there a design methodology one can follow to design a conventional dynamic comparator? 133900
I am designing a low power 100MHz SAR ADC ; but I can not find an accurate differential dynamic comparator for it. Non of the recently published structures work good. Would any one introduce me a proper structure? Thanks
Can anyone let me know to calculate dynamic power & delay in tanner 13 ? And any schematics for Current comparators using CMOS logic?
Dear Friends, Recently I am going to perform a Transient noise analysis of a dynamic comparator. I have some questions: 1. How to set the parameters such as: noisefmax, noisefmin , noise scale , etc. 2. In output results how to draw the power density of noise at the output versus time? Now I do the simulations and in the output waveform (...)
hello everyone i have designed the analog schematic of a comparator circuit in CADENCE . now i want to measure the following parameters of the designed circuit:- 1) clock to output delay 2) input voltage range 3) diffrential voltage swing 4) power consumption 5) load capacitance Can anyony please tell th
Hi Is it good to use typical op-amp instead of comparator? tnx
in per stage 1.5bit pipelined ADC, dynamic comparator can be used to decrease power consumption; as we know , dynamic comparator has three types: resistive dynamic comparator, differential pair dynamic comparator and capacitive (...)
I am designing a dynamic comparator which is composed of a preamp and a latch, i.e. the attached figure. the input signal is differential and it is sampled and subtracts Vthreshold with a swithed capacitance circuit (omitted in the figure). the process i use is 0.18um, and the parameter Vth0=0.4. the question is: is this architecture approp
here the one i/p of comparator is fixed in static one.... in the case of dynamic it changes wrt o/p..... dynamic ones are generally done so improve their noise immunity......