9 Threads found on edaboard.com: Comparator Dynamic Power
Is there a design methodology one can follow to design a conventional dynamic comparator? 133900
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-26-2016 17:07 :: qwerty99 :: Replies: 2 :: Views: 378
I am designing a low power 100MHz SAR ADC ; but I can not find an accurate differential dynamic comparator for it. Non of the recently published structures work good. Would any one introduce me a proper structure?
Analog Circuit Design :: 05-05-2016 21:43 :: mahshidkardan :: Replies: 0 :: Views: 186
Can anyone let me know to calculate dynamic power & delay in tanner 13 ?
And any schematics for Current comparators using CMOS logic?
Analog Circuit Design :: 12-14-2013 11:54 :: Avinash1111 :: Replies: 0 :: Views: 504
Recently I am going to perform a Transient noise analysis of a dynamic comparator. I have some questions: 1. How to set the parameters such as: noisefmax, noisefmin , noise scale , etc.
2. In output results how to draw the power density of noise at the output versus time? Now I do the simulations and in the output waveform (...)
Analog Circuit Design :: 11-12-2012 06:07 :: s_babayan :: Replies: 0 :: Views: 662
i have designed the analog schematic of a comparator circuit in CADENCE .
now i want to measure the following parameters of the designed circuit:-
1) clock to output delay
2) input voltage range
3) diffrential voltage swing
4) power consumption
5) load capacitance
Can anyony please tell th
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 06-30-2011 07:41 :: pankaj jha :: Replies: 1 :: Views: 670
Is it good to use typical op-amp instead of comparator?
Analog Circuit Design :: 09-19-2010 07:26 :: jimjim2k :: Replies: 7 :: Views: 2896
in per stage 1.5bit pipelined ADC, dynamic comparator can be used to decrease power consumption; as we know , dynamic comparator has three types: resistive dynamic comparator, differential pair dynamic comparator and capacitive (...)
Analog Circuit Design :: 03-26-2009 10:35 :: lhlbluesky :: Replies: 1 :: Views: 1234
I am designing a dynamic comparator which is composed of a preamp and a latch, i.e. the attached figure. the input signal is differential and it is sampled and subtracts Vthreshold with a swithed capacitance circuit (omitted in the figure).
the process i use is 0.18um, and the parameter Vth0=0.4.
the question is:
is this architecture approp
Analog Circuit Design :: 12-23-2007 12:04 :: swolf :: Replies: 3 :: Views: 934
this terminology is also used from power dissipation point of view.
static comparators needs a dc current for its operation... but can be used as a continuous time comaprator. ie no need of a strobe signal.
dynamic comparators does not require dc current... but this needs a strobe signal to latch the input.
hope this (...)
Analog Circuit Design :: 05-13-2007 14:51 :: fredflinstone :: Replies: 3 :: Views: 2251