47 Threads found on edaboard.com: Connect Fpga Adc
use SPI interface of adc to connect with fpga for data read and write operation.
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.04.2007 03:48 :: bansalr :: Replies: 3 :: Views: 1674
Hi Vacuum, (hehe that's funny)
The Xilinx Virtex-4 and Virtex-5 can input 1 gigabit/sec per differential input, so you may be able to connect your adc directly to the fpga. Inside the fpga, you could split the data into several parallel paths, and process them at a comfortable clock rate.
Why would you want to use (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.06.2007 23:15 :: echo47 :: Replies: 13 :: Views: 1666
I want to use the adc on spartan 3e kit. I think I need to use SPI interface to connect the adc to the fpga. I wonder if I can find a VHDL source code for using adc with SPI interface. Please help me...
PLD, SPLD, GAL, CPLD, FPGA Design :: 16.04.2010 08:54 :: ytmm :: Replies: 6 :: Views: 3565
My doubt is that whether we need to do something special to connect fpga IOs to adc output (something in programming) or its simple.
I connected AD9224 40 MHZ adc to SPartan 3 fpga. As long as I give only clock signal to adc from fpga data (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 02.09.2010 01:35 :: hallovipin :: Replies: 3 :: Views: 512
Hello to everyone,
I am very new to the world of fpga boards, and digital data converters, and that I deal with signal processing hardware.
I am going to work with a TR4 development board produced by Terasic, such a board is mounting a Stratix IV fpga which is meeting my performance requests.
Now the point is that I would like to (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.05.2013 10:00 :: 8Strings :: Replies: 0 :: Views: 305
I have Digilent-2E with SpartanII fpga and A/D TI-ADS2807 with 2 single-ended input.
I want to know what is the better I/O Signal Type to choose (LVCMOS,HSTL,SSTL,LVTTL) in the Input fpga I/O pin to connect with that A/D.
Thanks in advance
PLD, SPLD, GAL, CPLD, FPGA Design :: 30.10.2003 06:36 :: jonatan :: Replies: 9 :: Views: 6517
Yes, it is safe to drive a A/D Converter from an Xilinx fpga, but I do suggest that you use the DCM from Coregen built-in DPLL device, it able to generate a 25MHz from 50Mhz by dividing 50Mhz. By using this DCM, you also unable to connect to A/D from a clock output pin from fpga. So you save routing resource in your fpga. (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.04.2004 21:42 :: skynet :: Replies: 8 :: Views: 1280
adcs and DACs can?t be implemented in fpgas or CPLDs. fpgas and CPLDs are only for digital logic. You have to choose your desired DAC and adc from companies like Analog Device, Maxim, TI, ? and connect this one to the fpga or CPLD.
PLD, SPLD, GAL, CPLD, FPGA Design :: 17.06.2004 03:25 :: cube007 :: Replies: 12 :: Views: 6184
for digital signals ,u can connect them to fpga if the voltage level matchs.
PLD, SPLD, GAL, CPLD, FPGA Design :: 18.07.2005 22:22 :: freeinthewind :: Replies: 4 :: Views: 1291
I am interfacing adc with DE2 board. I am using adc 0809. My problem is that adc is giving output voltage as 5V for logic 1 and fpga as 3.3V as logic high. Will there is any problem in connecting it directly or should i use any other adc IC which gives o/p with 3.3V as logic high (compatible (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 19.02.2008 02:44 :: atif.india :: Replies: 3 :: Views: 3374
use de2 board from altera or any board which is having adc for conversion or connect the external adc using ide cable .
this is hw set-up !
for code you first read the syn oriented book .
tell me do you have basic about vhdl , your qualification , project for what ? std
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.10.2008 12:45 :: manish12 :: Replies: 1 :: Views: 3055
thanks a lot any other info place for tutorials anything that might help :D:D:D:D:D:D:D:D:D. this forum is great i will see it now
Added after 9 minutes:
Ok i saw it. it was very nice but out of range :cry::cry::cry::cry::cry: i don't have that much money. is there any cheaper work around.................
PLD, SPLD, GAL, CPLD, FPGA Design :: 15.04.2009 06:10 :: timi :: Replies: 2 :: Views: 928
(1) Your guess is correct.
You have to check on which bank your inputs will be connected.
Xilinx fpga's have different banks (a number of I/O grouped together), and each of these banks can be supplied with a different power (for example 2.5V or 3.3V). Depending on the bank-supply, the input has to be set (within the ISE -> Floorplan I/O/PACE) to
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.05.2009 10:48 :: Marcel Majoor :: Replies: 1 :: Views: 1032
I don't think you can find anything with the specification you mentioned for that price.
If you are looking for an fpga board with an fpga better than the one you mentioned, you have to pick your options or end up paying at least $1200 for such a board.
One good compromise will be the Xilinx/Digilent XtremeDSP Starter Platform ? Sp
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.09.2009 03:49 :: farhada :: Replies: 2 :: Views: 835
This is a straight forward adc. Just connect all the data lines to the fpga. Read the datasheet carefully. its an easy task only.
All the best
PLD, SPLD, GAL, CPLD, FPGA Design :: 20.11.2009 23:20 :: sudhirkv :: Replies: 2 :: Views: 843
The basic operation is to select some output pins of your DE-2 boards for adc connections, most likely from one of the
GPIO connectors. These pins must appear in the external port of your design's top entity. You need to make pin assignments
for these pins too. Possibly you can copy port definitions together with the pin assignments from (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 12.12.2009 09:48 :: FvM :: Replies: 10 :: Views: 2172
I need to synchronizes the clock of my DE2 board(altera) from 27MHz to my adc (ADS7861 - 500Khz). As i need to verify the adc, therefore i have been asked to constructed a VHDL code in DE2 board and connect to adc for testing. According the datasheet of adc, two inputs need to trigger for 1 clock cycle only, (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.01.2010 06:24 :: LF_LF :: Replies: 12 :: Views: 2105
May i know how can i test a adc before i connect it to a circuit?
I read some reference and it showed me that some binary/digital number from adc when an analog signal is supplied to it (Eg: 1--> 10 V).
However, i cant figure out how i get that binary number. It seen like the result is calculated from an equation but i (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 22.02.2010 10:46 :: LF_LF :: Replies: 1 :: Views: 509
I want to interact my fpga DE2 board with an adc. However, the max output voltage from DE2 board is only 3.3V while my adc is 5V peak. I tried to not connect anything in between and hoping again hope to obtain my expected result by just connect a jumper between DE2 board and adc but it is (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 29.03.2010 18:52 :: LF_LF :: Replies: 0 :: Views: 809
i need adc core for Spartan 3E fpga kit.....
and how to connect it with MICRO BLAZE Processor???/
plz help me out...
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.04.2010 03:18 :: kajulkumar :: Replies: 0 :: Views: 564
The fpga should have a hard adc on chip that has a bus compatible with those of microblaze and inputs connected to external input pins.
Embedded Systems and Real-Time OS :: 05.05.2010 04:28 :: amraldo :: Replies: 4 :: Views: 1790
Am working on my project based on sampling techniques. I would like to measure the frequency of an analog signal and then sample as per the measured frequency. Am using 484-pin Actel fpga and when I connect the signal to the analog pads, I do not know how to get the signal to the frequency meter in order to determine the frequency. May som
Electronic Elementary Questions :: 12.01.2011 00:59 :: kathalebm :: Replies: 3 :: Views: 641
I'm a bit confused,
you say that you have a dual channel adc with 10bit parallel outputs,
why do you want to isolate that from the fpga using optocouplers,
usually the voltage of the adc can be connected directly because they can work with 3v3.
If you want the isolation for level translation then you can simply use (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 14.03.2011 17:45 :: alexan_e :: Replies: 12 :: Views: 1162
I have 16 parallel adcs to connect to a virtex-5 fpga. They work when 12 of them are connected but when the 13th one is connected, output signal of 2 or 3 of them becomes crazy. When I check the inputs of them, they are ok and also there is no while noise on the output lines.
Does anybody have an (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 01.04.2011 09:09 :: Hadi-Alik :: Replies: 6 :: Views: 472
I saw one used once up to 3 ghz, and it worked suprisingly well. It had a pin with the signal, and 8 pins around it, in a square, connecting the two board grounds together.
Analog Circuit Design :: 12.07.2011 13:44 :: biff44 :: Replies: 3 :: Views: 799
Just as a heads up - you wrote that you used a micro controller (see your first post) and two comparators. Why don't you take the same approach in the fpga implementation? Use two comparators (each @ 5$ - and you'll get much for that price), connect them to your fpga. With some easy counters and the comparators, you'll get pretty close...
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.10.2011 03:37 :: lucbra :: Replies: 17 :: Views: 1137
This is what I have this far,
I want to connect fpga Spartan 3E and MQ-7 CO gas sensor. Firstly, I know that this sensor is analog device. So that I have to convert the signal. I'm intend to use Analog Capture Circuit from Spartan 3E board. MQ-7 need 2 kind of voltage: 5V and 1.4V. From the Spartan 3E datasheet, I know that I have to look fo
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.04.2012 05:53 :: aprilwulan :: Replies: 0 :: Views: 562
yes, as the previous poster said, some of the time its possible to control the voltage level needed for the interface only through a buffer or phy chip. but its not always the best route. if the pins are bi-directional, control on these buffers may become difficult.
an interesting example is an Ethernet interface. you can use a phy chip that co
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.06.2012 03:12 :: completelyuseless :: Replies: 2 :: Views: 579
I am working on a project to construct a low cost Radio Interferometer with a student organization at my university. Our plan is to construct several nodes of antennae, where each node is be responsible for controlling a group of antennae (point position, amplifier temperature, amplifier gain, filter selection, LO frequency, etc.) as well
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.10.2012 13:19 :: vasimr :: Replies: 0 :: Views: 241
You will need to supply much more information to get a meaningful response and not waste people's time.
What sort of board - to connect to what?
How accurate, how precise, what resolution, what frequency bandwidth, what signal range...
Analog Circuit Design :: 30.10.2012 05:19 :: FoxyRick :: Replies: 2 :: Views: 246
kindly I have a question; I want to implement Sigma Delta adc on Altera DE1, i wrote the code and run on QuartusII; now i want to know
is it possible to connect the analog input directly to the board?
as in my code the input is introduced as signed so my original analog input should be converted to the type signed before enter t
PLD, SPLD, GAL, CPLD, FPGA Design :: 14.12.2012 02:25 :: membership :: Replies: 2 :: Views: 774
I'm working on a project where i'm need to display the data through USB to Matlab. For example, to use an oscilloscope. Or data acquisition toolbox.
For example, to connect the adc data received and transmitted via USB as an analog channel in simulink
I read the documentation, but did not understand whether there is any documentation for driver d
PC Programming and Interfacing :: 10.04.2013 05:13 :: Araxnid :: Replies: 0 :: Views: 637
You are possibly right and wrong, all at once. I didn't check if it had i2c because who cares. :P I opened the pdf, did CTRL-F .. SPI ... yup, it has spi, excellent.
So quite possible that it has both I2C and SPI. And on fpga you want to implement it with SPI because that is less troublesome.
Regarding ethercat, I have no opinion. Because "there
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.08.2013 12:58 :: mrflibble :: Replies: 14 :: Views: 1007
My data converter is AD9863. My adc sample clock is souced from fpga.
The sample clock from fpga isn't clean. The adc sample clock frequecy is 15Mhz.I find that noises are introduced into my system. I have some problems about Clock. The sample clock can be sourced from fpga?If not,how can I do? Thanks a (...)
Analog Circuit Design :: 16.09.2004 09:24 :: eda4you :: Replies: 3 :: Views: 1172
Thanks to everyone who helped me with my last problem with this board.
I now would like to ask a question about the clocking on the board. What i am hoping to do is connect up an adc to this board so that it can process the digital output. The adc board itself outputs a clockout. I would like to use this clock out as the main clock for (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.09.2007 03:31 :: suddy72 :: Replies: 4 :: Views: 636
I have a small problem with regards clocking , am sure there is an easy soloution but want to know what you all think.
Right... i am using a XUP Virtex II Pro Evaluation board.
I am attaching an adc board to this fpga board, the adc board is being clocked at 75 MHz, i want to make t
PLD, SPLD, GAL, CPLD, FPGA Design :: 02.11.2007 04:07 :: suddy72 :: Replies: 4 :: Views: 708
I am using several devices (adc, DAC and SRAM) which all use the SPI interface. Now i know i can connect these devices to my fpga and have the devices all run as slaves and one master(fpga).
from doing some background reading i have noticed with SPI only one slave device at a time can be accessed. (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.12.2007 15:55 :: andrew257 :: Replies: 3 :: Views: 1192
DS18S20 with 1-wire connection to fpga
PT100 to analog input of fpga
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.11.2008 14:42 :: mobile-it :: Replies: 6 :: Views: 3125
I was working with 484-pin Actel fpga but I realized that its not possible to connect an external signal as clock that can be used to modify the sampling frequency of the adc. I changed the idea of using that fpga and now I'm looking for a circuit that can measure the analog signal. I want a circuit that can measure (...)
Digital Signal Processing :: 27.01.2011 08:21 :: kathalebm :: Replies: 4 :: Views: 1891
I am using SPARTAN3A fpga kit. I have made a dual layer Digitizer PCB which has AD9224 on board with preamplifier for analog signal and differential driver for adc. Since I only have one ground plane on the PCB , I treat this is as Analog ground plane. I have connected both AGND and DGND pins to the same ground plane, as (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 12.10.2010 01:18 :: hallovipin :: Replies: 1 :: Views: 437
they are used to pull a line high / or low. they are just resistors connected to power or ground. One application they are needed in is I2C communications or anything that needs to pull a line high but can only sink current not source it.
Electronic Elementary Questions :: 11.11.2010 02:19 :: b4bb4ge :: Replies: 8 :: Views: 2896
If all you want is the position for your fpga then you don't need to amplify anything. connect the ends of the pot to ground and the positive supply and the wiper to the adc input.
Analog Circuit Design :: 28.01.2011 03:47 :: keith1200rs :: Replies: 4 :: Views: 623
Many devices will have multiple VDD and GND pins. So even if some of them are powered, the device will work. But it's a good practice to connect all the applicable pins to respective Power/ GND. Because there could be some devices where different pins may be powering different blocks of the device. CPLD and fpga are the best examples for such power
Microcontrollers :: 07.12.2011 09:08 :: cks3976 :: Replies: 2 :: Views: 856
I am a big Microchip fan, and have used their PIC products in a large number of my own independent projects over the past few years. My latest project is a VGA frame-grabber device. I want to connect it to the VGA-out of a video card, and then capture the VGA data and represent it (downsampled) on a simple cell-phone monitor screen
Microcontrollers :: 16.02.2012 13:47 :: dogbertius :: Replies: 1 :: Views: 608
Hi (English isn't my primary language so sorry for some grammar or Syntax mistakes)
I am new to fpga and vhdl, and have some confusion about some minor things.
I found a link to a sinewave generator vhdl code and explanation(i dont remmember the user who posted it BUT thank u verymuch!!!1)
Here is the link
PLD, SPLD, GAL, CPLD, FPGA Design :: 16.06.2012 06:34 :: romikot :: Replies: 4 :: Views: 717
GUMY thanks for you reply
I am not sure whether I can access to spectrum analyzer in our lab, but if I could found one how can I connect my 16-bit output to that?
after that does it show me the power spectrum and SNR?
have you work with it before?
Analog Circuit Design :: 21.05.2013 06:22 :: membership :: Replies: 3 :: Views: 477
I am using Virtex 4 ML403 Evaluation Platform fpga kit, on this kit a product of TI is used for audio data converting named LM4550. This IC work on the AC 97 CODEC which take serial data as an input and output. This IC work on different 16 bit registers to route data either through the adc to DAC or connect input to the (...)
ASIC Design Methodologies and Tools (Digital) :: 04.06.2013 03:45 :: muneebziaa :: Replies: 0 :: Views: 216