1000 Threads found on edaboard.com: Cordic Fpga
An interesting cordic paper:
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-24-2003 18:13 :: matteo128 :: Replies: 1 :: Views: 1292
I need help on how to implement LOGRITHMIC in fpga without using cordic.
I thought of a very crude method of having a rough look up table method and then using Newton Raphsons Method to approximate the values.......
does someone have a better idea which also occupies lesser logic .
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-23-2003 16:03 :: Aircraft Maniac :: Replies: 2 :: Views: 2333
Can sqrt(x) realized by cordic in fpga, or can power(x,n) be realized by cordic?
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-17-2004 00:27 :: davyzhu :: Replies: 1 :: Views: 1979
Sure. Check h**p://www.andraka.com. It has very nice explanations on cordic implementation for fpga.
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-17-2004 09:07 :: Ace-X :: Replies: 1 :: Views: 3156
can anybody give me idea about algorithmic acceleration using fpga ,
or cordic algorithm using fpga:?:
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-15-2007 02:46 :: ameed :: Replies: 4 :: Views: 602
i need fast mul using adder with cordic algorithm in fpga.
Electronic Elementary Questions :: 10-04-2007 03:24 :: mim786 :: Replies: 1 :: Views: 1086
I need for finiche my these by title:"fpga implimention of Qam modem with cordic" , i need a code source for FIR and DAC, thanks
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-05-2012 04:45 :: toufikom :: Replies: 2 :: Views: 632
cordic alghorithem is an interactive process to performe elementary arithmetic functions like sin, cos, arctg
You can find some docs here
?A survey of cordic algorithms for fpga based computers,?
Good luck, Bart
PC Programming and Interfacing :: 02-04-2003 07:46 :: Bartart :: Replies: 3 :: Views: 1589
You can use a look-up table or a cordic algorithm.
Try a search also in this forum.
If you use @ltera they have an evaluation macro that implements
cordic in serial or parallel way.
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-20-2003 13:14 :: redsk_y :: Replies: 19 :: Views: 12370
Thanks in advanced!
Frequency minimum = 70 MHZ
RTL code sample
Xilinx fpga VII 6000 -4
* Xilinx Core Generator
* cordic algorithms on Google
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-27-2004 05:54 :: vomit :: Replies: 2 :: Views: 5016
At this link:
you will find intersting stuff on cordic and fpga.
This is a a doc on " fpga Implementation of Sine and Cosine Generators Using the cordic..."
Digital Signal Processing :: 04-12-2004 12:10 :: redsk_y :: Replies: 8 :: Views: 5777
Req. For cordic algorithm tutorial
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-03-2004 11:16 :: picus :: Replies: 1 :: Views: 1041
How can I find a good book for cordic algorithm
Thank in advance
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-23-2004 08:38 :: picus :: Replies: 4 :: Views: 1068
i would like to implement following formula on xilinx fpga
i know i can implement Sqrt and Arctan or even sin , ... by implementing cordic block,but i feel there is better way to do it.
how i can implement exactl
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-27-2004 10:15 :: vaf20 :: Replies: 7 :: Views: 1132
OK! Sine and cosine generation is an old problem, usually solved using look up tables, specially when the frequency of sine and cosine waves are fixed.
if the frequency is variable and you should compute a different sine or cosine value each time, then you should compute it and as our friends say cordic can do the work.
As you know Xilinx provid
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-02-2004 11:44 :: mami_hacky :: Replies: 5 :: Views: 2350
see following book :
"DSP with fpga"
as comment , cordic unit have 3 modes,circular,linear and hyperbolic.this depends on how u initialize ur parameters in unit(i.e. m=-1 or m=0 or m=1) in circular mode u can calculate square root .....(see relevant articles)
ASIC Design Methodologies and Tools (Digital) :: 11-16-2004 08:36 :: vaf20 :: Replies: 1 :: Views: 2385
I thought the stages in SDR were:
1.Convert RF to IF.
3.DDC (look at redriver), LPF
4. IQ demodulation using cordic or some sort of LUT.
you should look at gnuradio that would give a more detailed description.
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-12-2005 16:38 :: eziggurat :: Replies: 11 :: Views: 1819
Digital Signal Processing :: 03-29-2005 23:17 :: echo47 :: Replies: 4 :: Views: 1323
Can any one answer my following questions:
1- How can I find fpga implementation of arcsin() and do you know any references?
2- In MATLAB, how MathWork implement the arcsin() function do you know its algorithm?
I have same problem with you now, I need to calculate the ar
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-18-2007 01:51 :: xxargs :: Replies: 9 :: Views: 3882
anyone can give me idea about algorithemic accelaration using fpga:?:
argently needed about this.....
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-13-2007 06:03 :: ameed :: Replies: 0 :: Views: 494
cordic algorithm is used to find sin/cos values in Hardware design. Often look up tables are also used.
ASIC Design Methodologies and Tools (Digital) :: 10-24-2007 05:30 :: avimit :: Replies: 5 :: Views: 1110
see the attachments on cordic used in Micro processor and basic cordic structures for fpga implementation
Digital Signal Processing :: 03-28-2008 02:57 :: muralicrl :: Replies: 1 :: Views: 1301
I am not too experienced with fpga, but in a new project I feel there are no way around. I use a Blackfin DSP (ADSP-BF533) running at 500MHz, and need to equip it with hardware acceleration for geometry functions (cordic).
My thoughts are wiring up the fpga (a Xilinx Spartan-3, XC3S1000) on the Blackfin data/address bus, where (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-17-2008 01:10 :: vandelay :: Replies: 0 :: Views: 680
The DDS waveform (commonly a sinewave, but sometimes other waveforms) is usually tabulated in a ROM, because run-time calculation can be slow, as you have discovered.
If you really need a cordic, then its stages can be pipelined in an
Digital Signal Processing :: 03-22-2008 06:40 :: echo47 :: Replies: 2 :: Views: 535
I am doing my project on fft implementation using cordic algorithm......when we put it for synthesies its taking 12-15 hours to pls tell me wats the problem......the problem will be with our code or something else........
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-28-2009 19:19 :: nagu guptha :: Replies: 9 :: Views: 3442
I am trying to implement Arcsine function using cordic methods. I am following the method given in "A surevey of cordic algorithms for fpga based computers" by Ray Andraka. (paper attached).
For the method described, I tried using x0 = 1 (since the paper says we start with a unit vector on x axis), y0 = 0, and z0 = 0. I am getting an (...)
ASIC Design Methodologies and Tools (Digital) :: 06-09-2009 21:30 :: analog_fever :: Replies: 2 :: Views: 735
we can compute e^(-jw) this way; e^(-jw) = cosw - u see j's coefficient is sinw. And there is many way for computation sinus and cosinus. One way is cordic algorithm.
Digital Signal Processing :: 01-28-2010 13:00 :: zula :: Replies: 4 :: Views: 873
Check for cordic Algorithm...
It helps you to implement exponantial functions. implementation of cordic is quite simple, I think...
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-12-2010 06:30 :: Ilgaz :: Replies: 1 :: Views: 1246
I'm doing a project on BPSK and DPCM. I have used LMS algorithm for the predictor and all the values I defined are in real. But I found that computation in real especially multiplication is taking too long. I want to convert real values to fixed point binary in the format for example 110.1011. How do I achieve
Digital Signal Processing :: 03-15-2011 14:51 :: pavankumarl73 :: Replies: 1 :: Views: 887
There's some code involved like CIC filter, FIR filter, IIR filter ,cordic algorithm and FFT in the book "Digital Signal Processing with Field Programmable Gate Arrays".Hope it would be helpful.
ASIC Design Methodologies and Tools (Digital) :: 09-16-2011 01:27 :: rockybc :: Replies: 2 :: Views: 625
Hey, guys! I have been written the PMSM controller these days , and have to implement the space vector PWM /Field oriented control algorithm on fpga. It's said that some modules of SVPWM could be implemented through cordic algorithm, like Park transform and Clark transform.Has anybody ever been involved with the algorithm implementation on (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-28-2011 03:07 :: rockybc :: Replies: 0 :: Views: 600
i m using 512 point FFT IP core in V6 fpga to calculate the frequency of the input signal, i m getting the correct peak and amplitude for the same . the peak's real and imaginary value i have to give to the cordic ip core(atan) to get the phase of the input signal . the input to the fft is a 10 bit samples from adc in 2's complement format the ou
Electronic Elementary Questions :: 04-25-2012 05:52 :: snehalg :: Replies: 0 :: Views: 318
I read about FFT . there are several ways. Pipeline, Radix, cordic ... But i want a good comparison between them.
Digital Signal Processing :: 05-13-2012 16:02 :: Zerox100 :: Replies: 2 :: Views: 650
can u plz help me for implementing cordic algorithm for trignometric functions using vhdl?
Electronic Elementary Questions :: 10-05-2012 06:05 :: mayaraj :: Replies: 3 :: Views: 652
Does anyone implement "arcCos(x)" function by cordic? I did it by Taylor series, but I don't know how to do it by cordic.
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-14-2012 16:32 :: sheikh :: Replies: 4 :: Views: 1034
I need some help in documentation of cordic algorithm....can anyone please suggest me from where should i get some tutorials and documents where cordic algorithm are clearly explained
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-20-2013 03:13 :: sougatavlsi :: Replies: 2 :: Views: 302
Hi,I have implemented radix2/4 & split radix FFT algorithm without using cordic.They are running fine...o/p is coming but the problem is that the code is non make that code synthesizable i have to implement cordic and need to interface it with the FFT code.I read few documents about cordic and able to undersatnd its part...among al
Digital Signal Processing :: 09-07-2013 07:29 :: sougata_vlsi13 :: Replies: 1 :: Views: 402
hello i want to implement a 2D DCT on fpga i have little experience working with complex implementations as such
i did some reasearch and was wondering what is the difference between several implementation methods in speed and efficiency for 2D DCT
does anybody know what's better to use to calculate the cosine values and avoid much floating poi
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-21-2014 14:02 :: ghattas.akkad :: Replies: 0 :: Views: 233
I tryed to calculate a value of sine and cosine functions using cordic algorithm. But it does not work in fixed point system and i wrote it as simple program.
Here is a code:
integer i = 0;
initial begin (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-27-2014 11:05 :: brainiac_rus :: Replies: 4 :: Views: 255
I am not familiar with ASIC design flow, maybe somebody else can give some valuable comments....
For fpga design, what I have used synthesis tools(only to synthesis VHDL code): Synplicity Synplify > Synopsys fpga Compiler II > Mentor Leonardo Exemplar
It is only my personal opinion...
Professional Hardware and Electronics Design :: 07-13-2001 17:19 :: :: Replies: 7 :: Views: 3670
In the next months i have to migrate a fpga VirtexII VHDL design (near to million gates) to ASIC.
In the original design i use a classic fpga flow using as main tools Synplify+Amplfy+Modelsim, but i think boundary conditions,timing constraints and layout (even synthesis) in ASIC will be very different and other flow and considerations will be us
ASIC Design Methodologies and Tools (Digital) :: 01-30-2002 05:09 :: hwswboy :: Replies: 21 :: Views: 7467
Here is a very good link of publications on various fpga Technologies by Dr.Jonathan Rose.Njoy the great stuff.....
"Talent does what it can; genius does what it must."
- Edward George Bulwer-Lytton (1803-1873)
ASIC Design Methodologies and Tools (Digital) :: 03-03-2002 03:46 :: satya :: Replies: 6 :: Views: 2544
fpga CPU Links
1. -> t
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-09-2002 08:46 :: jimjim2k :: Replies: 1 :: Views: 2103
The practical Xilinx Designer Lab book by "Dave Van den Bout" from prentice hall is a very good starting point for beginners in fpga field. In this book two proto boards from XESS Corporation are described with schematics etc. - XS40 board for Xilinx fpga XC4005XL and XS95 for Xilinx XC95108 CPLD. The s/w for this boards are free and can be downed
Professional Hardware and Electronics Design :: 03-24-2002 03:29 :: siraj :: Replies: 4 :: Views: 1537
I want to built a test evulation board for fpga from xilinx
the idea is to built this simple JTAG Programmer
in a test board and use IMpact software to download the code .
IMpact software are integ
ASIC Design Methodologies and Tools (Digital) :: 04-11-2002 09:34 :: Celtadevigo :: Replies: 1 :: Views: 2130
How to convert the fpga to asic quickly, smoothly, and efficiently?
Thx in advance.
ASIC Design Methodologies and Tools (Digital) :: 05-12-2002 02:46 :: whatever :: Replies: 12 :: Views: 1778
Anybody know of a good application note or enginners note for porting an existing ASIC netlist to xilinx fpga? :o
ASIC Design Methodologies and Tools (Digital) :: 05-12-2002 11:05 :: rakko :: Replies: 4 :: Views: 1945
I am not sure if this link has been posted already, but another fpga and ASIC course can be found
ASIC Design Methodologies and Tools (Digital) :: 05-30-2002 21:13 :: Sarnouk :: Replies: 6 :: Views: 1879
Hi, can anyone give me some good references/links/books for information on designing systems that consist of a CPU core, with functionality implemented around the CPU (such as ethernet controller, hard disc controller), that are implemented on an fpga.
I am unsure of the number of macrocells a typical fpga has, and the macrocells required to imp
Microcontrollers :: 06-19-2002 13:05 :: O-Dog :: Replies: 3 :: Views: 2652
Already have fpga compiler, why need Design Compiler (DC)? what is differences ?
ASIC Design Methodologies and Tools (Digital) :: 07-07-2002 11:25 :: dd2001 :: Replies: 13 :: Views: 3883