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42 Threads found on edaboard.com: **Cordic Fpga**

I would also add **cordic** algorithm and look-up table (optionally with linear interpolation) to the candidate list.
Of course it doesn't matter if you are using Verilog or a different hardware description method.

ASIC Design Methodologies and Tools (Digital) :: 02-07-2015 07:34 :: FvM :: Replies: **3** :: Views: **585**

Ok, I see the problem:
zi = zi - **cordic**_iter;
xi = xi - (yi / 2.0**i);//cos
yi = yi + (xi / 2.0**i);//sin
In the third line you are using the new value for xi, it should be the old value.

PLD, SPLD, GAL, CPLD, FPGA Design :: 10-28-2014 05:00 :: std_match :: Replies: **4** :: Views: **874**

PLD, SPLD, GAL, CPLD, FPGA Design :: 05-05-2014 17:59 :: ads-ee :: Replies: **1** :: Views: **916**

i need verilog code of sine wave generator....i tried with **cordic** algorithm but i cant able to proceed....plzzz help

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 03-31-2014 16:29 :: rids1 :: Replies: **1** :: Views: **1231**

Till now manually i have calculated the whole algorithm in pen-paper using BP in log domain for LDPC decoding.The output is coming for regular LDPC only but i have some doubt over irregular i started the coding considering the regular LDPC only.but my doubt to overcome those floating point and tanh calc is **cordic** needed? how to implement th

PLD, SPLD, GAL, CPLD, FPGA Design :: 07-26-2013 06:58 :: sougata_vlsi13 :: Replies: **5** :: Views: **657**

Hello Dears
Does anyone implement "arcCos(x)" function by **cordic**? I did it by Taylor series, but I don't know how to do it by **cordic**.
Regards
Mostafa

PLD, SPLD, GAL, CPLD, FPGA Design :: 10-14-2012 16:32 :: sheikh :: Replies: **4** :: Views: **1897**

hi,
can u plz help me for implementing **cordic** algorithm for trignometric functions using vhdl?
tanx

Elementary Electronic Questions :: 10-05-2012 06:05 :: mayaraj :: Replies: **3** :: Views: **955**

Hello Dears
Could you please tell me which one is better for implementation of "arc Cos(x)" in VHDL?(Also, better for implementation on real hardware(**fpga**))
1_ Using Maclaurin series ( attached fig ).
2_ Using "**cordic**" method.
79271.
Regards
Mostafa

PLD, SPLD, GAL, CPLD, FPGA Design :: 08-29-2012 03:03 :: sheikh :: Replies: **11** :: Views: **1164**

I read about FFT . there are several ways. Pipeline, Radix, **cordic** ... But i want a good comparison between them.

Digital Signal Processing :: 05-13-2012 16:02 :: Zerox100 :: Replies: **2** :: Views: **1026**

i m using 512 point FFT IP core in V6 **fpga** to calculate the frequency of the input signal, i m getting the correct peak and amplitude for the same . the peak's real and imaginary value i have to give to the **cordic** ip core(atan) to get the phase of the input signal . the input to the fft is a 10 bit samples from adc in 2's complement format the ou

Elementary Electronic Questions :: 04-25-2012 05:52 :: snehalg :: Replies: **0** :: Views: **527**

Hallow,
I need for finiche my these by title:"**fpga** implimention of Qam modem with **cordic**" , i need a code source for FIR and DAC, thanks

PLD, SPLD, GAL, CPLD, FPGA Design :: 02-05-2012 04:45 :: toufikom :: Replies: **2** :: Views: **807**

Hey, guys! I have been written the PMSM controller these days , and have to implement the space vector PWM /Field oriented control algorithm on **fpga**. It's said that some modules of SVPWM could be implemented through **cordic** algorithm, like Park transform and Clark transform.Has anybody ever been involved with the algorithm implementation on (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 12-28-2011 03:07 :: rockybc :: Replies: **0** :: Views: **1040**

There's some code involved like CIC filter, FIR filter, IIR filter ,**cordic** algorithm and FFT in the book "Digital Signal Processing with Field Programmable Gate Arrays".Hope it would be helpful.

ASIC Design Methodologies and Tools (Digital) :: 09-16-2011 01:27 :: rockybc :: Replies: **2** :: Views: **781**

Hello everyone,
I'm doing a project on BPSK and DPCM. I have used LMS algorithm for the predictor and all the values I defined are in real. But I found that computation in real especially multiplication is taking too long. I want to convert real values to fixed point binary in the format for example 110.1011. How do I achieve

Digital Signal Processing :: 03-15-2011 14:51 :: pavankumarl73 :: Replies: **1** :: Views: **1110**

Digital Signal Processing :: 11-04-2010 09:06 :: Aser :: Replies: **1** :: Views: **815**

a **cordic** core may be available from **fpga**'s manufacture

PLD, SPLD, GAL, CPLD, FPGA Design :: 03-17-2010 09:00 :: philoman :: Replies: **1** :: Views: **1748**

If you need synthesizable verilog then you can use a LUT, **cordic** processor, DW component, etc.
If it doesn't need to be synthesizable I usually use a Taylor series.

PLD, SPLD, GAL, CPLD, FPGA Design :: 02-17-2010 23:50 :: RBB :: Replies: **4** :: Views: **1661**

Check for **cordic** Algorithm...
It helps you to implement exponantial functions. implementation of **cordic** is quite simple, I think...

PLD, SPLD, GAL, CPLD, FPGA Design :: 02-12-2010 06:30 :: Ilgaz :: Replies: **1** :: Views: **1503**

I am trying to implement Arcsine function using **cordic** methods. I am following the method given in "A surevey of **cordic** algorithms for **fpga** based computers" by Ray Andraka. (paper attached).
For the method described, I tried using x0 = 1 (since the paper says we start with a unit vector on x axis), y0 = 0, and z0 = 0. I am getting an (...)

ASIC Design Methodologies and Tools (Digital) :: 06-09-2009 21:30 :: analog_fever :: Replies: **2** :: Views: **899**

I am doing my project on fft implementation using **cordic** algorithm......when we put it for synthesies its taking 12-15 hours to pls tell me wats the problem......the problem will be with our code or something else........

PLD, SPLD, GAL, CPLD, FPGA Design :: 04-28-2009 19:19 :: nagu guptha :: Replies: **9** :: Views: **3968**

Hi,
see the attachments on **cordic** used in Micro processor and basic **cordic** structures for **fpga** implementation

Digital Signal Processing :: 03-28-2008 02:57 :: muralicrl :: Replies: **1** :: Views: **1638**

Hello.
I am not too experienced with **fpga**, but in a new project I feel there are no way around. I use a Blackfin DSP (ADSP-BF533) running at 500MHz, and need to equip it with hardware acceleration for geometry functions (**cordic**).
My thoughts are wiring up the **fpga** (a Xilinx Spartan-3, XC3S1000) on the Blackfin data/address bus, where (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 03-17-2008 01:10 :: vandelay :: Replies: **0** :: Views: **836**

Tr to search for **cordic** algorithm

PLD, SPLD, GAL, CPLD, FPGA Design :: 02-21-2008 12:47 :: Iouri :: Replies: **3** :: Views: **1492**

Has anyone tried to implement the Hough Transform (HT) for image processing using **fpga**???
I've read it is possible by means of **cordic** algorithm for its capability to implement trigonometrical functions
Any suggestion about????

PLD, SPLD, GAL, CPLD, FPGA Design :: 02-13-2008 05:57 :: bercam :: Replies: **3** :: Views: **1770**

i need fast mul using adder with **cordic** algorithm in **fpga**.

Elementary Electronic Questions :: 10-04-2007 03:24 :: mim786 :: Replies: **1** :: Views: **1405**

for what purpose **cordic** algo.
is used ?

PLD, SPLD, GAL, CPLD, FPGA Design :: 09-23-2007 07:05 :: manish12 :: Replies: **4** :: Views: **735**

hi,
anyone can give me idea about algorithemic accelaration using **fpga**:?:
argently needed about this.....

PLD, SPLD, GAL, CPLD, FPGA Design :: 09-13-2007 06:03 :: ameed :: Replies: **0** :: Views: **745**

Hi
iam implementing an algorithm onto **fpga** in which i need to evaluate standard deviation where i need to find squareroot.i though tof using **cordic**.but i need to convert real number to std_logic.plz mention the ways to implement this or provide code if anybody had it.
thanks in advance

PLD, SPLD, GAL, CPLD, FPGA Design :: 01-18-2007 09:41 :: vinodkumar :: Replies: **0** :: Views: **940**

I thought the stages in SDR were:
1.Convert RF to IF.
2.ADC
3.DDC (look at redriver), LPF
4. IQ demodulation using **cordic** or some sort of LUT.
you should look at gnuradio that would give a more detailed description.

PLD, SPLD, GAL, CPLD, FPGA Design :: 05-12-2005 16:38 :: eziggurat :: Replies: **11** :: Views: **2013**

Digital Signal Processing :: 03-29-2005 23:17 :: echo47 :: Replies: **4** :: Views: **1607**

see following book :
"DSP with **fpga**"
as comment , **cordic** unit have 3 modes,circular,linear and hyperbolic.this depends on how u initialize ur parameters in unit(i.e. m=-1 or m=0 or m=1) in circular mode u can calculate square root .....(see relevant articles)
GoodLuck

ASIC Design Methodologies and Tools (Digital) :: 11-16-2004 08:36 :: vaf20 :: Replies: **1** :: Views: **2736**

OK! Sine and cosine generation is an old problem, usually solved using look up tables, specially when the frequency of sine and cosine waves are fixed.
if the frequency is variable and you should compute a different sine or cosine value each time, then you should compute it and as our friends say **cordic** can do the work.
As you know Xilinx provid

PLD, SPLD, GAL, CPLD, FPGA Design :: 11-02-2004 11:44 :: mami_hacky :: Replies: **5** :: Views: **2750**

Sure. Check h**p://www.andraka.com. It has very nice explanations on **cordic** implementation for **fpga**.
Ace-X.

PLD, SPLD, GAL, CPLD, FPGA Design :: 08-17-2004 09:07 :: Ace-X :: Replies: **1** :: Views: **3985**

Hello all,
Can sqrt(x) realized by **cordic** in **fpga**, or can power(x,n) be realized by **cordic**?
Regards,
Davy Zhu

PLD, SPLD, GAL, CPLD, FPGA Design :: 08-17-2004 00:27 :: davyzhu :: Replies: **1** :: Views: **2504**

How can I find a good book for **cordic** algorithm
Thank in advance

PLD, SPLD, GAL, CPLD, FPGA Design :: 06-23-2004 08:38 :: picus :: Replies: **4** :: Views: **1267**

Req. For **cordic** algorithm tutorial

PLD, SPLD, GAL, CPLD, FPGA Design :: 06-03-2004 11:16 :: picus :: Replies: **1** :: Views: **1251**

At this link:
you will find intersting stuff on **cordic** and **fpga**.
This is a a doc on " **fpga** Implementation of Sine and Cosine Generators Using the **cordic**..."
Regards,
--rs

Digital Signal Processing :: 04-12-2004 12:10 :: redsk_y :: Replies: **8** :: Views: **6622**

Hi every body,
I am looking for verilog code for matrix multiplication (not involving the use of a **cordic** core cause that would take alot of space on the **fpga**.............I mean is it possible to have a code without **cordic** core used.........) .........if any one knows about it then kindly message me
Aircraft Maniac

ASIC Design Methodologies and Tools (Digital) :: 03-05-2003 14:24 :: Aircraft Maniac :: Replies: **0** :: Views: **5250**

Hi all,
I need help on how to implement LOGRITHMIC in **fpga** without using **cordic**.
I thought of a very crude method of having a rough look up table method and then using Newton Raphsons Method to approximate the values.......
does someone have a better idea which also occupies lesser logic .
Aircraft Maniac

PLD, SPLD, GAL, CPLD, FPGA Design :: 02-23-2003 16:03 :: Aircraft Maniac :: Replies: **2** :: Views: **2570**

PLD, SPLD, GAL, CPLD, FPGA Design :: 02-21-2003 11:33 :: igorilla :: Replies: **2** :: Views: **4561**

Hi !
**cordic** alghorithem is an interactive process to performe elementary arithmetic functions like sin, cos, arctg
You can find some docs here
?A survey of **cordic** algorithms for **fpga** based computers,?
Good luck, Bart

PC Programming and Interfacing :: 02-04-2003 07:46 :: Bartart :: Replies: **3** :: Views: **1778**

An interesting **cordic** paper:

PLD, SPLD, GAL, CPLD, FPGA Design :: 01-24-2003 18:13 :: matteo128 :: Replies: **1** :: Views: **1572**

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