64 Threads found on edaboard.com: Cordic Fpga
An interesting cordic paper:
PLD, SPLD, GAL, CPLD, FPGA Design :: 24.01.2003 18:13 :: matteo128 :: Replies: 1 :: Views: 1207
cordic alghorithem is an interactive process to performe elementary arithmetic functions like sin, cos, arctg
You can find some docs here
?A survey of cordic algorithms for fpga based computers,?
Good luck, Bart
PC Programming and Interfacing :: 04.02.2003 07:46 :: Bartart :: Replies: 3 :: Views: 1548
You can use a look-up table or a cordic algorithm.
Try a search also in this forum.
If you use @ltera they have an evaluation macro that implements
cordic in serial or parallel way.
PLD, SPLD, GAL, CPLD, FPGA Design :: 20.02.2003 13:14 :: redsk_y :: Replies: 19 :: Views: 12061
I need help on how to implement LOGRITHMIC in fpga without using cordic.
I thought of a very crude method of having a rough look up table method and then using Newton Raphsons Method to approximate the values.......
does someone have a better idea which also occupies lesser logic .
PLD, SPLD, GAL, CPLD, FPGA Design :: 23.02.2003 16:03 :: Aircraft Maniac :: Replies: 2 :: Views: 2256
Thanks in advanced!
Frequency minimum = 70 MHZ
RTL code sample
Xilinx fpga VII 6000 -4
* Xilinx Core Generator
* cordic algorithms on Google
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.03.2004 05:54 :: vomit :: Replies: 2 :: Views: 4807
At this link:
you will find intersting stuff on cordic and fpga.
This is a a doc on " fpga Implementation of Sine and Cosine Generators Using the cordic..."
Digital Signal Processing :: 12.04.2004 12:10 :: redsk_y :: Replies: 8 :: Views: 5592
A survey of cordic algorithms for fpga based computers
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.06.2004 11:26 :: satellite :: Replies: 1 :: Views: 974
How can I find a good book for cordic algorithm
Thank in advance
PLD, SPLD, GAL, CPLD, FPGA Design :: 23.06.2004 08:38 :: picus :: Replies: 4 :: Views: 991
i would like to implement following formula on xilinx fpga
i know i can implement Sqrt and Arctan or even sin , ... by implementing cordic block,but i feel there is better way to do it.
how i can implement exactl
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.07.2004 10:15 :: vaf20 :: Replies: 7 :: Views: 1091
Can sqrt(x) realized by cordic in fpga, or can power(x,n) be realized by cordic?
PLD, SPLD, GAL, CPLD, FPGA Design :: 17.08.2004 00:27 :: davyzhu :: Replies: 1 :: Views: 1874
Sure. Check h**p://www.andraka.com. It has very nice explanations on cordic implementation for fpga.
PLD, SPLD, GAL, CPLD, FPGA Design :: 17.08.2004 09:07 :: Ace-X :: Replies: 1 :: Views: 2929
OK! Sine and cosine generation is an old problem, usually solved using look up tables, specially when the frequency of sine and cosine waves are fixed.
if the frequency is variable and you should compute a different sine or cosine value each time, then you should compute it and as our friends say cordic can do the work.
As you know Xilinx provid
PLD, SPLD, GAL, CPLD, FPGA Design :: 02.11.2004 11:44 :: mami_hacky :: Replies: 5 :: Views: 2246
see following book :
"DSP with fpga"
as comment , cordic unit have 3 modes,circular,linear and hyperbolic.this depends on how u initialize ur parameters in unit(i.e. m=-1 or m=0 or m=1) in circular mode u can calculate square root .....(see relevant articles)
ASIC Design Methodologies and Tools (Digital) :: 16.11.2004 08:36 :: vaf20 :: Replies: 1 :: Views: 2273
can any one suggest me how to write code for fft & cordic processor.means first i write in C or direct implement in verilog/vhdl.please guide me.
Electronic Elementary Questions :: 01.03.2005 00:20 :: abhineet22 :: Replies: 2 :: Views: 2213
I thought the stages in SDR were:
1.Convert RF to IF.
3.DDC (look at redriver), LPF
4. IQ demodulation using cordic or some sort of LUT.
you should look at gnuradio that would give a more detailed description.
PLD, SPLD, GAL, CPLD, FPGA Design :: 12.05.2005 16:38 :: eziggurat :: Replies: 11 :: Views: 1779
Digital Signal Processing :: 29.03.2005 23:17 :: echo47 :: Replies: 4 :: Views: 1248
Can any one answer my following questions:
1- How can I find fpga implementation of arcsin() and do you know any references?
2- In MATLAB, how MathWork implement the arcsin() function do you know its algorithm?
I have same problem with you now, I need to calculate the ar
PLD, SPLD, GAL, CPLD, FPGA Design :: 18.01.2007 01:51 :: xxargs :: Replies: 9 :: Views: 3675
anyone can give me idea about algorithemic accelaration using fpga:?:
argently needed about this.....
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.09.2007 06:03 :: ameed :: Replies: 0 :: Views: 464
can anybody give me idea about algorithmic acceleration using fpga ,
or cordic algorithm using fpga:?:
PLD, SPLD, GAL, CPLD, FPGA Design :: 15.09.2007 02:46 :: ameed :: Replies: 4 :: Views: 570
i need fast mul using adder with cordic algorithm in fpga.
Electronic Elementary Questions :: 04.10.2007 03:24 :: mim786 :: Replies: 1 :: Views: 973
cordic algorithm is used to find sin/cos values in Hardware design. Often look up tables are also used.
ASIC Design Methodologies and Tools (Digital) :: 24.10.2007 05:30 :: avimit :: Replies: 5 :: Views: 1001
see the attachments on cordic used in Micro processor and basic cordic structures for fpga implementation
Digital Signal Processing :: 28.03.2008 02:57 :: muralicrl :: Replies: 1 :: Views: 1219
I am not too experienced with fpga, but in a new project I feel there are no way around. I use a Blackfin DSP (ADSP-BF533) running at 500MHz, and need to equip it with hardware acceleration for geometry functions (cordic).
My thoughts are wiring up the fpga (a Xilinx Spartan-3, XC3S1000) on the Blackfin data/address bus, where (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 17.03.2008 01:10 :: vandelay :: Replies: 0 :: Views: 647
I have a problem when implement the cordic, I use cordic to geneartor triangle value from in DDS design and I use parallel strucuture and
therefore, there is a very big delay because of cordic iterative.
However, we must have run the DDS at 100MHz, as the long data path of CODIC(propagation time is 37.952 ns), only 26.3
Digital Signal Processing :: 21.03.2008 05:09 :: xie.qiang :: Replies: 2 :: Views: 506
I am doing my project on fft implementation using cordic algorithm......when we put it for synthesies its taking 12-15 hours to pls tell me wats the problem......the problem will be with our code or something else........
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.04.2009 19:19 :: nagu guptha :: Replies: 9 :: Views: 3323
I am trying to implement Arcsine function using cordic methods. I am following the method given in "A surevey of cordic algorithms for fpga based computers" by Ray Andraka. (paper attached).
For the method described, I tried using x0 = 1 (since the paper says we start with a unit vector on x axis), y0 = 0, and z0 = 0. I am getting an (...)
ASIC Design Methodologies and Tools (Digital) :: 09.06.2009 21:30 :: analog_fever :: Replies: 2 :: Views: 705
we can compute e^(-jw) this way; e^(-jw) = cosw - u see j's coefficient is sinw. And there is many way for computation sinus and cosinus. One way is cordic algorithm.
Digital Signal Processing :: 28.01.2010 13:00 :: zula :: Replies: 4 :: Views: 847
Check for cordic Algorithm...
It helps you to implement exponantial functions. implementation of cordic is quite simple, I think...
PLD, SPLD, GAL, CPLD, FPGA Design :: 12.02.2010 06:30 :: Ilgaz :: Replies: 1 :: Views: 1162
cordic is often used to rotate complex vectors, and very rarely is used to convert matrices.
It was obviously useful when hardware multipliers were comparatively heavy.
Now when the floating point cores are usual things
it would be better to implement the usual algorithm to find eigen value of matrix using the floating point calculations.
Digital Signal Processing :: 04.11.2010 09:06 :: Aser :: Replies: 1 :: Views: 542
I'm doing a project on BPSK and DPCM. I have used LMS algorithm for the predictor and all the values I defined are in real. But I found that computation in real especially multiplication is taking too long. I want to convert real values to fixed point binary in the format for example 110.1011. How do I achieve
Digital Signal Processing :: 15.03.2011 14:51 :: pavankumarl73 :: Replies: 1 :: Views: 853
There's some code involved like CIC filter, FIR filter, IIR filter ,cordic algorithm and FFT in the book "Digital Signal Processing with Field Programmable Gate Arrays".Hope it would be helpful.
ASIC Design Methodologies and Tools (Digital) :: 16.09.2011 01:27 :: rockybc :: Replies: 2 :: Views: 547
Hey, guys! I have been written the PMSM controller these days , and have to implement the space vector PWM /Field oriented control algorithm on fpga. It's said that some modules of SVPWM could be implemented through cordic algorithm, like Park transform and Clark transform.Has anybody ever been involved with the algorithm implementation on (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.12.2011 03:07 :: rockybc :: Replies: 0 :: Views: 533
I need for finiche my these by title:"fpga implimention of Qam modem with cordic" , i need a code source for FIR and DAC, thanks
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.02.2012 04:45 :: toufikom :: Replies: 2 :: Views: 577
I uses 3 accelerometers to get the g-vector , I want to transfer the readings to euler angles , i know the rotation matrices and i will need to implement arcsine and arctan which isn't convenient
So, I was wondring if there is other way to get the euler angles without this matrix or can anyone mention another way to get the arcsine and arctan oth
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.04.2012 07:08 :: prof_ :: Replies: 3 :: Views: 725
i m using 512 point FFT IP core in V6 fpga to calculate the frequency of the input signal, i m getting the correct peak and amplitude for the same . the peak's real and imaginary value i have to give to the cordic ip core(atan) to get the phase of the input signal . the input to the fft is a 10 bit samples from adc in 2's complement format the ou
Electronic Elementary Questions :: 25.04.2012 05:52 :: snehalg :: Replies: 0 :: Views: 284
I read about FFT . there are several ways. Pipeline, Radix, cordic ... But i want a good comparison between them.
Digital Signal Processing :: 13.05.2012 16:02 :: Zerox100 :: Replies: 2 :: Views: 576
Look at this
Also, most fpga vendors have cordic modules; some are free.
Electronic Elementary Questions :: 05.10.2012 08:02 :: barry :: Replies: 3 :: Views: 553
Does anyone implement "arcCos(x)" function by cordic? I did it by Taylor series, but I don't know how to do it by cordic.
PLD, SPLD, GAL, CPLD, FPGA Design :: 14.10.2012 16:32 :: sheikh :: Replies: 4 :: Views: 900
I need some help in documentation of cordic algorithm....can anyone please suggest me from where should i get some tutorials and documents where cordic algorithm are clearly explained
PLD, SPLD, GAL, CPLD, FPGA Design :: 20.05.2013 03:13 :: sougatavlsi :: Replies: 2 :: Views: 224
1) the design i have used before can be applied for regular LDPC and also can be applied for irregular column LDPC .
2) as i remeber the any algorithm of BP can be applied for regular and irregular LDPC .
3) we didnt use cordic to over come the floating point and tanh calculation we have make our floating point representation acc
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.07.2013 10:16 :: Mina Magdy :: Replies: 5 :: Views: 324
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.02.2003 11:33 :: igorilla :: Replies: 2 :: Views: 3806
Hi every body,
I am looking for verilog code for matrix multiplication (not involving the use of a cordic core cause that would take alot of space on the fpga.............I mean is it possible to have a code without cordic core used.........) .........if any one knows about it then kindly message me
ASIC Design Methodologies and Tools (Digital) :: 05.03.2003 14:24 :: Aircraft Maniac :: Replies: 0 :: Views: 4242
I use the ip core generator tools as much as saves time (like case u were gonna write ur own code for lets say a cordic would be lot easier and less time consuming to use the coregen to implement it) and secondly makes ur routing a lot easier.
PLD, SPLD, GAL, CPLD, FPGA Design :: 31.08.2003 10:15 :: Aircraft Maniac :: Replies: 7 :: Views: 1333
Some addition to this thread:
Carrier synchronisation should also be considered in conjunction with symbol timing recovery. Some algorithms work fine when symbol timing has been locked and therefore symbol timing recovery has been done in front of carrier synchronization. In these cases cordic can be used.
These kind of signal processing blocks
Digital Signal Processing :: 22.01.2005 11:12 :: Wacko2000 :: Replies: 7 :: Views: 1306
LUTs in the fpgas can be used only for Digital Computations.
For handling sine functions there is a algorithm called cordic which stands for CO-ordinate Rotation for Digital Computing.
This algorithm is used in DDFS- Direct Digital Frequency Synthezisers for the generation of sin wave and i have read that it is also used in Calculators for s
PLD, SPLD, GAL, CPLD, FPGA Design :: 16.11.2005 06:09 :: veejaye :: Replies: 1 :: Views: 708
1.Design and implementation of part of I2C serial interface protocol
2.Design and implementation of a math co-processor. The designed co-processor should be able to perform a complex mathematical operatio such as matrix inversion, QR decomposition, cordic algroithem.
3. Design and implementation of a Reed-Solomon(RS) decoder.
4. Design a 512 wor
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.01.2007 20:43 :: finalmatrix :: Replies: 1 :: Views: 591
iam implementing an algorithm onto fpga in which i need to evaluate standard deviation where i need to find squareroot.i though tof using cordic.but i need to convert real number to std_logic.plz mention the ways to implement this or provide code if anybody had it.
thanks in advance
PLD, SPLD, GAL, CPLD, FPGA Design :: 18.01.2007 09:41 :: vinodkumar :: Replies: 0 :: Views: 639
Hi friends.iam implementing an alogrithm onto fpga.i wrote code and iam able to do simulation in MODELSIM.and for synthesis i used xilinx.the code is synthesizing,but iam getting problem when iam doing simulation with ISE simulator.
i have modified the properties such that i can use modelsim simulator in xilinx.iam getting an error of error load
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.02.2007 01:30 :: vinodkumar :: Replies: 5 :: Views: 701
Has anyone tried to implement the Hough Transform (HT) for image processing using fpga???
I've read it is possible by means of cordic algorithm for its capability to implement trigonometrical functions
Any suggestion about????
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.02.2008 05:57 :: bercam :: Replies: 3 :: Views: 1467
Tr to search for cordic algorithm
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.02.2008 12:47 :: Iouri :: Replies: 3 :: Views: 977