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Dac And Jitter

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6 Threads found on edaboard.com: Dac And Jitter
Hi everybody, recently I'm studying Matlab simulation of clock jitter effects on dac output spectrum. First I get an ideal dac output without clock jitter and do a FFT analysis to see its spectrum. This step is easy to realize. Then I generate dac output with jittered (...)
hi, all How to model the clock jitter in current steering dac, and how to simulate this effect ( in behavior model or in circuit level simulation)?
Dear all, I design current dac. But I don't understand two equations. What's its meaning? These are the same or double. and I design latches, my power is use digital power. How do I simulate clk jitter? If my digital power is dirty, how do I do? Thanks.
This discussion is a few weeks old, but ... If you are using Xilinx ISE, it includes perl: xilperl.exe. The fractional divider technique generates jitter that may be undesirable for the application. The DDS technique can generate a nice low-jitter clock, but it requires an external dac, low-pass filter, and (...)
Precision dacs use architecture based around R-2R architectures and generally do not require a high frequency clock. In high speed converters the clock is an integral part of the dac and clock jitter,overshoot and undershoot on the clock signal contribute to noise.
If you don't use a sufficiently good low-pass filter after your DDS dac, then the sinewave will have unwanted frequency spurs that, on an oscilloscope, look like little wiggles or stairsteps or jitter. You don't want that junk going into your PLL, or it will wiggle and jitter too.