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Dac Settling Time

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26 Threads found on Dac Settling Time
In my device I need pretty fast dacs - ideally 16 bit, with less than 3.5 us settling time, SPI interface. There are plenty of them, but all of them are quite expensive (for mass production; and I need 8 of them on a single board). Then I noticed that there are a lot of "Audio" dacs with standard resolution of 24bit or (...)
Each stage (SAR, dac, comparator, S/H) has its own timing and these need to be sequenced for best sampling rate and accuracy tradeoff. A small state machine with either higher speed clocking, or self-timed, is likely what you want. The analog elements' settling time, response time will set the timing (...)
The comparator will be clocked once per bit. Its delay plus the dac settling time (to 1/2 LSB) and SAR logic delay all have to fit into the bit-time window. In your 5MSPS 10 bit ADC that means 50MHz clock rate. You have to do 10 compares w/ logic action, to get the output word and the word comes once per sample (hold). (...)
Hi, all The dac's load res and cap are fixed, so how to increase the frequency of this dac? thanks
I am not sure what you want to know. What do you want the dac for? What resolution, settling time, voltage range? In general, you add the dac of your choice and throw numbers at it, either parallel or SPI or I2C. Keith
I need to design a reference buffer for a successive approximation ADC. This ADC uses a capacitive dac array. What is the procedure to determine the reference buffer specifications such as gain , bandwidth, settling time etc. ?? Is there a document outlining this ??
how speed of a current output dac can be determined?
I guess, you want to use the PWM circuit as a dac. What are your requirements in dac terms? Resolution, update rate, settling time? What are the available hardware PWM parameters of your microcontroller, respectively the expected frequency, resolution and accuracy of a software pwm solution? You'll notice, that there several (...)
Hi everyone, I was trying to simulate the settling time of a D/A converter in cadence. Because I'm using a dac from the AHDL library and it's an idea one, therefore the simulation result doesn't contain a settling period. I'm thinking to use a RC circuit to simulate that case but I'm not sure how I should do it so that there (...)
Hello, i m working on successive approximation ADC,. for that ,i have to design dac ,which one is better,,resitor string,,R2R ladder, or charge scaling..? i choose charge scaling...but in that i have one problem with,,capacitance value.. how we decide capacitance value for any charge scaling dac? and if i choose 5-bit dac,then why we (...)
Hi, I'm designing an op amp to buffer the output of a 12-bit 1 MSPS dac. My question is how fast should the op amp settle to meet the requirements of less than 1/4 LSB? The output load of the amplifier is 10 KOhm || 100 pF. I am having trouble finding the formula to compute this. Your response would be greatly appreciated. Thanks!
In the dac, dac setting time should be smaller than update rate, for example, update rate is 1M, so the time period is 1us, and setting time should less than 1us. But I found in AD974 (dac Update Rate 210MSPS ,dac settling time 11ns ), (...)
Hi to all to forum members, though I have already searched the forums and posted this in Analog IC Layout and Design, I am posting it in this forum too. I have a CMOS chip with 12bit and 6 bit current steering dac, and I want to characterize it its INL, DNL, settling time with offset and gain error. Only equipments I have in lab is a (...)
Hi to all to forum members, I have a CMOS dac chip with 12bit and 6 bit current steering dac, and want to characterize it its INL DNL settling time with offset and gain error.I want to test the chip in school setting. Only equipments I have in lab is a mixed signal scope, a function generator and bunch of DC power (...)
The settling time of a 10bit dac is 5ns. Can this dac work under clock freqency of 400MHz ? How to understand it? Because we need to gain the stable conversion value of each input code when we calculate the INL, How to get the stable conversion value in such short time (2.5nm/400MHz)? Thanks!
It looks to me like the ADC has some "memory" of a previous compare. Some suggestions to look for: Insufficient settling time on the dac. This would likely worst on the MSB transition, as you are seeing. If the dac has not settled to 16bits (>11 time constant settling) before the (...)
Hi All, What is the best methodology of simulating INL and DNL of PWM one bit dac (or any PDM one bit dac like Delta Sigma). I use HSPICE but considering settling time and number of codes to be simulated one by one (setting PWM frequencies one by one) manually would be very time consuming. I am (...)
This is the dac operation frequency -- I guess so.
You should consider what is the application of your dac? Your application will govern the settling time, output swing, speed, current consumption and so on for your op-amp
please tell me what test bench i appply to measur the settling time of a dac . send me any doc pdf it would be highly appreciable..
in general, current dac is used for video application
How to determine the unity-gain bandwidth of the opamp using in 10bit C-2C dac? And how much the slew rate should be? Thanks !
Hi, How exactly is the measurement of the settling time and power consumption is carried out for a current steering dac. settling time is the time it takes for the output to settle with in 10%. Thanks
Aroma, if I understand your question correctly, your dac is only changing by 1lsb so you can measure the difference between the final value after it has settled (V(1000)) and V(0111) + 1/2 lsb and the time difference from the start of the transition till when you get to 1/2 lsb is the sttling time hope this helps David
When the rate of a dac conversion is comfirm , it is how to determine the bandwith and slew rate of the OPAMP used as buffer . Generally, we can assume single pole of OPAMP for simplification. what is the relation format between the settling time constant and the bandwidth ?
How can the speed (settling time) of a Delta-Sigma dac be derived (1bit output, 10bit accuracy, 4MHz clock system)? The output filter is not defined yet. Since speed of a Delta-Sigma ADC is defined by the decimation filter and accuracy/resolution I thought this would also yield for the dac. But however I still end up with (...)