| Search found 69 matches on edaboard.com: davyzhu |
[hspice] from schematic to netlist
hello all,i have used hspice for a few weeks (mostly cmos analog design), but edit netlist by notepad is not convenient (when number of mosfets more than 20).i wish you recommend a easy schematic editor by which the schematic can be transformed to hs...
Analog IC Design & Layout :: 19 Nov 2009 3:03 :: pakis :: Replies: 53 :: Views: 5622
matlab, how to get frequency spectrum?
hi all,i am a matlab newbie :)how to get frequency spectrum of a vector data? (something like [3 4 2 10 ...])i heard fft is the time-frequency fransform. and i tried fft() function in matlab.but it return a complex number. is it stand for both freque...
Electronic Elementary Questions :: 15 Nov 2009 18:42 :: Aya2002 :: Replies: 27 :: Views: 19320
fsm designing
while desiging in verilog. which fsm is best mealy or moore fsm and why?...
ASIC Design Methodologies & Tools (Digital) :: 12 Nov 2007 12:18 :: manasiw2 :: Replies: 27 :: Views: 2286
clock divider by 3 with 50% duty cycle?
hi all,how to build a clock divider by 3 with 50% duty cycle?input and output are listed below.clkin__--__--__--__--__--__--clkout______------______------any suggestions will be appreciated!best regards,davy...
ASIC Design Methodologies & Tools (Digital) :: 17 Jul 2007 13:50 :: jasmine25 :: Replies: 27 :: Views: 6126
diversity ?= mimo
hi,i am reading code on ofdm.it seems diversity transmitter send out 2 data copy at the same time. is it similar to mimo?best regards,davy...
Digital communication :: 19 May 2007 3:53 :: Cking :: Replies: 6 :: Views: 936
qam demapping to ldpc decoder
hi all,ldpc decoder use soft information. but how to get the soft information from qam?btw, dvb-s2 use ask demapping, is it suitable for soft information demapping?best regards,davy...
Digital communication :: 02 May 2007 17:35 :: mar-cas1 :: Replies: 6 :: Views: 798
reduce power: reduce freq or reduce volt?
hi all,how to reduce power?you have a circuit operating at 20 mhz and 5 volt supply. what would you do to reduce the power consumption in the circuit- reduce the operating frequency of 20mhz or reduce the power supply of 5volts and why? any suggestio...
ASIC Design Methodologies & Tools (Digital) :: 14 Apr 2007 5:16 :: sumit_techkgp :: Replies: 7 :: Views: 549
how to simulate netlist with gated clock?
hi all,when i simulate netlist (verilog style) with gated clock, i found the output is very different with what i see in rtl level (with a lot of red xxxx).so i add tfile in ncsim to forbidden the delay and timing check in global scope (because the d...
ASIC Design Methodologies & Tools (Digital) :: 13 Apr 2007 9:03 :: sumit_techkgp :: Replies: 12 :: Views: 780
what time to use clocking block in systemverilog?
hi,i found in some systemverilog examples, people like to add clocking block to driver and monitor. while some other sv examples only use modport (dont use clocking block).so i am confused with it. 1. is it recommendation to use clocking block?2. sha...
ASIC Design Methodologies & Tools (Digital) :: 23 Mar 2007 1:21 :: ankit12345 :: Replies: 5 :: Views: 177
high input impedence and buffer
hello,i found a sentence the op amp has high input impedance, this mean that its input are buffered. as far as i know, buffer means large current, but high input impedence means little current, am i right?davy zhu...
Electronic Elementary Questions :: 07 Mar 2007 20:55 :: maharshi_qis :: Replies: 3 :: Views: 261
[dc] determine parameter in set_input_delay?
hi all,when use set_input_delay/set_output_delay, how to determine the -max/-min parameter? is it calculated by hand , calculated by tools, or give out by some standard specification?set_input_delay -max 498 -clock extscl [find port ddc_sda_i ...
ASIC Design Methodologies & Tools (Digital) :: 27 Feb 2007 18:29 :: shiv_emf :: Replies: 7 :: Views: 249
matlab rayleigh fading channel simulation?
hi all,i have got a rayleigh fading channel simulation code by matlab.the code list below:% rayleigh fadinga = sqrt(0.5)*( randn( 1, symbols_per_frame) + j*randn( 1, symbols_per_frame) );% complex noisenoise = sqrt(variance)*( randn(1,symbols_per_fra...
Digital communication :: 05 Feb 2007 0:21 :: waqasbukhari :: Replies: 16 :: Views: 5589
systemverilog behavioral model?
dear all,i have try to use systemverilog for 3 month of the year.is there any open simple systemverilog behavioral model that we can learn from.any suggestions are welcome!best regards,davy...
ASIC Design Methodologies & Tools (Digital) :: 15 Dec 2006 12:24 :: Guru59 :: Replies: 2 :: Views: 177
systemverilog clocking block assign data time?
hi all,i use clocking block to construct testbench component like driver.and i am confused with what time clocking block to synchronize data.for example, there is sync_fifo_if_i interface instance and wr_driver_cb clocking block.the clocking block is...
ASIC Design Methodologies & Tools (Digital) :: 08 Dec 2006 2:07 :: davyzhu :: Replies: 3 :: Views: 120
why use fork...join_none in systemverilog?
hi all,i found in most systemverilog example, people like to use fork...join_none pair (not the traditional fork...join pair). is there some advantage to fork...join_none pair? thanks!best regards,davy...
ASIC Design Methodologies & Tools (Digital) :: 29 Nov 2006 2:26 :: davyzhu :: Replies: 4 :: Views: 495
verilog problem: default case to set signal xxxx
hi all,i always found people like to add default branch like below:case(branch) ... ... [all the possible branch] ... ...default: signal = 8bx;and my friend told me its for simulation cause. when branch not hit all the possible...
ASIC Design Methodologies & Tools (Digital) :: 27 Nov 2006 4:30 :: echo47 :: Replies: 6 :: Views: 150
formal logic equivalent check (lec)
hi all,when do formal equivalent check (rtl and gate level) , i remember that the tool compare the comb logic between d-ff .but when synthesis use re-timing and gated clock, can lec tool comparertl and gate?and is gated clock one form of re-timing?i ...
ASIC Design Methodologies & Tools (Digital) :: 24 Nov 2006 10:24 :: bravobravo :: Replies: 6 :: Views: 765
sva "seq_a |-> seq_b |-> seq_c"
hi,all ,there is seq_a |-> seq_b |-> seq_c in sva. is seq_a |-> seq_b |-> seq_c equal to (seq_a and seq_b) |-> seq_c ?or shall we need only care the last implication (|-> or |=>), thanks!best regards,davy...
ASIC Design Methodologies & Tools (Digital) :: 24 Nov 2006 6:18 :: davyzhu :: Replies: 2 :: Views: 84
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parse tree like data like xml by perl?
hi all,i used to embed data in program use something like case orif..else. but my friend advice me to separate program and data. so iwant to use a tree-like data file like xml.the question is:1. is there any better or easier standardized tree-like da...
PC Programming and Interfacing :: 08 Nov 2006 14:03 :: umairsiddiqui :: Replies: 1 :: Views: 204
[ncsim] stop -> force -> run error?
hi all,i want to write a tcl in ncsim to do below work.1. stop when $signal is 12. set the lock to force stop only stop once3. force $other_signal4. continue run5. force $other_signal back6 continue runbut ncsim said cannot run command executed from ...
ASIC Design Methodologies & Tools (Digital) :: 25 Sep 2006 6:08 :: aji_vlsi :: Replies: 6 :: Views: 522
cadence nc-sim's stop / strobe ?
hi all,nc-sim provide two main command to dump data: stop (-cont) and strobe.my problem is which command is faster when used to dump data?thanks!davy...
ASIC Design Methodologies & Tools (Digital) :: 29 Aug 2006 4:38 :: davyzhu :: Replies: 2 :: Views: 276
nc-sim tcl script tool?
hi all,i use nc-sim tcl command (like stop) and found tcl script is white-space sensitive. and i have to wait for the tcl report error in run time and time-consuming. can i debug/lint the tcl script before run all the simulation? thanks!or is there s...
ASIC Design Methodologies & Tools (Digital) :: 29 Aug 2006 4:30 :: davyzhu :: Replies: 6 :: Views: 336
#$sig , $sig in cadence nc-sim tcl
hi all,in cadence nc-sim tcl script, signals are sometimes quoted by #$sig, sometimes quoted by $sig. whats their difference?thanks!davy...
ASIC Design Methodologies & Tools (Digital) :: 29 Aug 2006 4:02 :: davyzhu :: Replies: 2 :: Views: 165
does cadence provide site like synopsys's solvnet?
hi all,does cadence provide site like synopsyss solvnet?btw, does cadence provide free online course and free course material?best regards,davy...
ASIC Design Methodologies & Tools (Digital) :: 06 Jun 2006 12:43 :: spauls :: Replies: 2 :: Views: 261
verification by non-hdl(c++/java)??
hi all,i found that some verification procedure using non-hdl such as c++/java.but how these non-hdl language generate edge stimulus? can non-hdl also generate @posedage???is there any basic idea behind it?best regards,davy...
ASIC Design Methodologies & Tools (Digital) :: 13 May 2006 5:16 :: omara007 :: Replies: 5 :: Views: 252
dose any fpga support reconfiguration?
i found reconfigurable device is a hot research region, does any fpga nowadays support reconfiguration? i heard that atmel has a chip can do that work.thanks!davy...
PLD, SPLD, GAL, CPLD, FPGA Design :: 09 May 2006 9:58 :: Ohh :: Replies: 13 :: Views: 495
change mealy fsm to moore fsm?
hi all,i have read the book verilog design style guide from http://www.edaboard.com/ftopic165643.htmlthe book said you should use moore fsm in principle. but my question is: can i change all the mealy fsm to moore fsm? whats the sacrefice to do this(...
ASIC Design Methodologies & Tools (Digital) :: 20 Apr 2006 2:16 :: kr_vinayak :: Replies: 2 :: Views: 252
verilog 2001 file i/o: read large file?
hi all,i want to read one data @(posedge clock) and compare with my module output.the data file may contain one million data and very large.whats the most efficient way to do it?my boss told me to use $readmemh, but it seems waste ram.does verilog 20...
ASIC Design Methodologies & Tools (Digital) :: 01 Apr 2006 17:22 :: aji_vlsi :: Replies: 1 :: Views: 132
concatenate string in verilog?
hi all,i want to open a lot of files and read data to reg.something like//-----code--------$readmemh(.\pattern\0.dat,inmem0);$readmemh(.\pattern\1.dat,inmem1);...$readmemh(.\pattern\49.dat,inmem49);//-----code end----i want to use something like strc...
ASIC Design Methodologies & Tools (Digital) :: 01 Apr 2006 8:06 :: aji_vlsi :: Replies: 3 :: Views: 795
verilog's integer and reg?
hi all,i heard that verilog has integer type.someone said integer can be signed or unsigned. how to declare signed integer?and whats the difference with integer and reg signed (2s complement) ?any suggestions will be appreciated!best regards,davy...
ASIC Design Methodologies & Tools (Digital) :: 28 Mar 2006 6:51 :: Thomson :: Replies: 4 :: Views: 228
verilog task pass value problem?
hi all,i am reading the book writing testbench. and write the code below:it seems the code is blocked in the task @ (posedge clk), and the task never return the valid, why?i guess task cannot pass the continuous clk value?//--------test.v------------...
ASIC Design Methodologies & Tools (Digital) :: 28 Mar 2006 6:36 :: Thomson :: Replies: 2 :: Views: 258
how to write compact dff chain?
hi all,sometimes i have to write long dff chain like below://------code--------------...reg [7:0] dff0,dff1,dff2,...dff50;always@(posedge clk) if(rst) begin dff0 <= 0; ... dff50 <= 0; en...
ASIC Design Methodologies & Tools (Digital) :: 27 Mar 2006 2:50 :: linuxluo :: Replies: 4 :: Views: 177
auto pipeline logic??
hi all,using hdl to pipelining manually is a hardy task. and i found some tools like synplify have pipeline tools. but the pipeline they provided is just insert reg between ram and logic.my question is: is there a tool to auto pipeline the logic? for...
PLD, SPLD, GAL, CPLD, FPGA Design :: 21 Mar 2006 13:41 :: eda_wiz :: Replies: 1 :: Views: 240
matlab how to do z=f(x,y)?
hi all,i want to do x=;y=;z=log(exp(x)+exp(y)); i want to get z as a 101*101 (n*n) vectorbut the matlab give z as a 1*101 (1*n) vector.how to get z 101*101 vector without for loop?best regards,davy...
Electronic Elementary Questions :: 19 Mar 2006 9:44 :: neils_arm_strong :: Replies: 3 :: Views: 117
does cadence have sth like synopsys snug?
hi all,i am a fresh cadence nc-verilog user. does cadence have the community like synopsyss snug? and does cadence open the article to public?best regards,davy...
ASIC Design Methodologies & Tools (Digital) :: 16 Feb 2006 14:52 :: eda_freak :: Replies: 6 :: Views: 255
what's ncverilog snapshot mean?
hi all,i used to be a modelsim user. now my boss force me to use ncverilog(seems very difficult to learn). we dump data from ncverilog and view signal using debussy. all controled by script.whats snapshot mean in ncverilog?btw, may you recommend som...
ASIC Design Methodologies & Tools (Digital) :: 14 Feb 2006 2:51 :: kgeorge123 :: Replies: 7 :: Views: 1008
nc-verilog hdl.var problem?
hi all,i am a nc-verilog newbie and confused with nc-verilogs file.in cds.lib, map logical lib name to physical locationdefine ic_lib /lsi_libwhy map again in hdl.var?define work worklibdefine lib_map (myfile.v => mylib, ./cell_lib => techl...
ASIC Design Methodologies & Tools (Digital) :: 12 Feb 2006 13:27 :: aji_vlsi :: Replies: 1 :: Views: 225
compile and elaborate?
hi all,i am new to candence tools. whats the difference with compile and elaborate?and where can i download the manual of the candence tools?best regards,davy...
ASIC Design Methodologies & Tools (Digital) :: 21 Dec 2005 7:16 :: xworld2008 :: Replies: 2 :: Views: 198
sorting algorithm in vhdl
hi folks ..anyone has an idea about a good algorithm for sorting values in hardware ? .. i do have 28 registers loaded with different values and i want to get the maximum value stored in these registers .. whats the best algorithm for that ?...
ASIC Design Methodologies & Tools (Digital) :: 03 Dec 2005 17:37 :: omara007 :: Replies: 6 :: Views: 1029
"analog" ram and d-filpflop?
hi all,we know that digital circuit use ram and d-ff to store digital signal values. is there any analog ram and d-ff which can store analog signal values?i am curious to know if not, how to store analog signal values in analog way?any suggestions wi...
Electronic Elementary Questions :: 22 Nov 2005 22:26 :: Sceadwian :: Replies: 6 :: Views: 315
what's one-wait-state on-chip rom mean in ti?
hello all,i am reading tis datasheet. and whats one-wait-state on-chip rom mean? can it be reprogrammable like flash?any suggestions will be appreciated!best regards,davy...
Electronic Elementary Questions :: 29 Sep 2005 7:40 :: puviarasu :: Replies: 6 :: Views: 201
mpeg2 mp(at)ll and mpeg1?
hi all,i heard that mpeg2 and mpeg1 use same compression methods.mpeg2s mp@ll and mpeg1 are all 4:2:0, 352*288*30. but mpeg2s mp@ll is 4mbit/s and mpeg1 is 1.5mbit/s. why they have different bit rates?and if i want to do 352*288*30 video compression....
Digital Signal Processing :: 06 Sep 2005 8:53 :: swahlah :: Replies: 1 :: Views: 177
[verilog] how to read data from a file?
hi all,i want to read one data per clock from a flie, and send them to a pipelined circuit.after that, save one data per clock to a file.i am new to testbench. now i decide to read a data (in) from file @(negedge clk). and pass this data to the modul...
ASIC Design Methodologies & Tools (Digital) :: 10 Jul 2005 17:05 :: jarodz :: Replies: 3 :: Views: 438
[verilog] how to save data to a file?
hi all,i want to save data to a file. and i use $fopen, %fwrite, %fclose. but i found these function only can be called in initial block. when i use them outside initial block, the compiler report errors?? i want to use it in a for block, how?i use m...
ASIC Design Methodologies & Tools (Digital) :: 07 Jul 2005 2:55 :: jjww110 :: Replies: 7 :: Views: 2049
two verilog fsm style compare
hi all,there is a problem on how to write fsm in verilog(http://www.asic-world.com/tidbits/verilog_fsm.html).most synthesis tools recommend second using two always blocks style. but i would like to use third single always style. it seems more compact...
ASIC Design Methodologies & Tools (Digital) :: 04 Jul 2005 10:46 :: nanako :: Replies: 8 :: Views: 381
how about signed adder?
hi all,i want to add two 6 bits signed digit. something like 6b10_0110, the msb 1 is negative digit,other00100 is absolute value.or something like 6b00_0110, the msb 0 is positive digit,other00100 is absolute value.how to design a signed adder to add...
ASIC Design Methodologies & Tools (Digital) :: 29 Jun 2005 14:12 :: AlexWan :: Replies: 6 :: Views: 582
hdl synthesis to what
hello all,i am an verilog/vhdl newbie, when i write it, i can not image what digital circuit will hdl be synthesised to, can you recommand some ref on it?btw, i use fpga for test, and i have ise and synplicity.regards,davy zhu...
PLD, SPLD, GAL, CPLD, FPGA Design :: 27 Jun 2005 7:34 :: wolfheart_2001 :: Replies: 14 :: Views: 870
i/o standard in fpga
hello all,where to find the i/o standard general description list includeing that like lvpecl, cml, hstl/sstl,lvcmos/ttl?how are they supported by fpga?regards,davy zhu...
PLD, SPLD, GAL, CPLD, FPGA Design :: 23 Jun 2005 4:19 :: freeinthewind :: Replies: 7 :: Views: 2448
1*512m vs 2*256m ddr ram?
hi all,i want to buy a new pc. and 1*512m and 2*256m ddr ram, which better?from the performance aspect and why?any suggestions will be appreciated!best regards,davy...
Electronic Elementary Questions :: 22 Jun 2005 14:40 :: power-twq :: Replies: 7 :: Views: 348
internal 3-state replace multiplexer?
i have read a techxclusive from xilinx named timing closure, it suggest that we should use internal three-state buffers to replace large multiplexers, because virtex based fpgas use dedicated and-or logic to implement three-state buffers, and can red...
ASIC Design Methodologies & Tools (Digital) :: 15 Jun 2005 7:10 :: nand_gates :: Replies: 2 :: Views: 672
why not use internal tri-state in asic?
i found many ip cores (e.g. amba bus) dont support internal tri-state, seems we should avoid tri-state in asic design, but why not use it, and what techniques to replace it?regards,davy zhu...
ASIC Design Methodologies & Tools (Digital) :: 14 Jun 2005 23:22 :: tutx :: Replies: 12 :: Views: 651
what is fan-in??
hello,what is fan-in? something similar to fan-out? but what is the difinition?regards,davy...
ASIC Design Methodologies & Tools (Digital) :: 13 Jun 2005 10:19 :: virgorabbit :: Replies: 14 :: Views: 942
how to do parallel operation in matlab?
hi all,is matlab support parallel operation?for example,most of the code in matlab is serial operation: b=a;c=b;that equal to c=a;.but if it support parallel operation. so c~=a.any suggestions will be appreciated!best regards,davy...
Electronic Elementary Questions :: 01 Jun 2005 12:42 :: cedance :: Replies: 4 :: Views: 159
bch code length must be 2^m -1 ??
hello all,matlab supply the bchenc function, but it said the code length must be 2^m -1.could code length not equal to 2^m -1? any suggestions will be appreciated!best regards,davy...
Electronic Elementary Questions :: 23 May 2005 16:52 :: zorro :: Replies: 1 :: Views: 318
"if (x==1 && y==0)" in matlab
hello all,how to do if (x==1 && y==0) in matlab, the if (x==1 && y==0) is in c. thanks!davy...
Software Problems, Hints and Reviews :: 20 May 2005 8:49 :: YUV :: Replies: 4 :: Views: 336
correct 3 bit error in 7k bit length code?
hello all,i encounter a problem that a 7k bit length code have several error (mostly 3 bit error). and the 3 bit error are burst error(i.e. they are nearby in a small region).how to correct this 3 error in 7k length code? and should i seperate the 7k...
Electronic Elementary Questions :: 24 Apr 2005 11:45 :: happy2005 :: Replies: 3 :: Views: 144
what's "side effects" of register?
hello all,a sentence said the registers are setup during reset and can be changed with no side effects, but whats side effects?thanks!davy...
ASIC Design Methodologies & Tools (Digital) :: 21 Feb 2005 3:32 :: Thomson :: Replies: 5 :: Views: 303
how to do byte alignment?
hello all,what may cause wrong byte alignment? and how to do byte alignment generally?thanks!davy...
Embedded Systems and Real-Time OS :: 16 Feb 2005 2:40 :: Ace-X :: Replies: 4 :: Views: 405
difference b/w fpga & cpld
what is the difference between pld, spld, gal, cpld and fpga ?...
PLD, SPLD, GAL, CPLD, FPGA Design :: 23 Jan 2005 22:08 :: lucbra :: Replies: 20 :: Views: 5560
why use 0 ohm resistor
hello all,i found 0 ohm resistor was really exsisted, but how to use it and at which circumstance?regards!davy zhu...
Professional Hardware and Electronics Design :: 28 Dec 2004 9:01 :: mcsdos :: Replies: 24 :: Views: 2304
the third type of input except vh and vl
hello all,i found a set of idt programmable clock skew ic chip (for example 5v9910a)have technique to implement a mode select pin to three states: vhigh, vmiddle,vlow, the vmiddle means vdd/2. the datasheet said: these inputs are normally wired to vc...
Electronic Elementary Questions :: 15 Nov 2004 8:47 :: nicleo :: Replies: 1 :: Views: 402
'signal' (vhdl) = 'wire' or 'reg' (verilog)
hello all,i found vhdl use signal and verilog use wire and reg to describe a connection between combinational logic, but the thing bothered me that how to specify the signal to be wire or reg or signal equal to wire or reg ? :roll: regards,davy zhu...
PLD, SPLD, GAL, CPLD, FPGA Design :: 27 Oct 2004 5:01 :: bibo1978 :: Replies: 4 :: Views: 981
why 33, 47 ohm resistors? and the list of them?
hello all,i found the value of resistors are so strange, why it is defined 33,47 ohms? i think 35, 50 ohm is more easy to remember :)and anyone give me a list of the all the values of resistors and the capacitors that we produce? is there a rule that...
Electronic Elementary Questions :: 18 Oct 2004 14:20 :: M!k :: Replies: 5 :: Views: 582
51 mcu bus to fpga interface
hello all,how about the 51 mcu bus to fpga interface through p0 and p2 bus, i use the register share tech, but if the registers , the design must be complex, can you give me some suggestions on it?regards,davy zhu...
PLD, SPLD, GAL, CPLD, FPGA Design :: 13 Oct 2004 15:38 :: IceMan4 :: Replies: 2 :: Views: 297
telephone cable voltage
hello all,how about the telephone cable voltage?regards,davy zhu...
Electronic Elementary Questions :: 27 Aug 2004 5:10 :: delay :: Replies: 5 :: Views: 942
ti resource cd??
hello all,how to apply for the tis resource cd on tis website?regards,davy zhu...
Digital Signal Processing :: 26 Aug 2004 12:35 :: dora :: Replies: 1 :: Views: 348
fpga xilinx spartan 2 & uclinux
hi,this is my firdtpost.excuse me for my bad english.i want buy the xsb-300e development board the descriptionat http://www.xess.com/prod032.php3 address.i have a one question.can i load uclinux on this board?thank lotsbyeccde_...
PLD, SPLD, GAL, CPLD, FPGA Design :: 18 Aug 2004 21:29 :: davorin :: Replies: 2 :: Views: 423
search asy sram controller(verilog)
hello all,can you give me some ref code or site on asynchronous sram controller by verilog?btw, i have searched opencores, but its controller is by vhdl.regards,davy zhu...
PLD, SPLD, GAL, CPLD, FPGA Design :: 04 Aug 2004 12:48 :: wadaye :: Replies: 3 :: Views: 423
os for 8051?
hello all,if you have more than 5 task in 51, will you choose a small os for it, or use traditional loop?regards,davy zhu...
Microcontrollers :: 28 Jul 2004 10:05 :: Ace-X :: Replies: 3 :: Views: 228
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