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42 Threads found on Decimal Vhdl
You shouldn't expect others to do your homework, but help is surely available. First step would be a clear specification. You can design a divider to give fractional result bits (bits right of the decimal point), however this has nothing to do with floating point number representation. Floating point involves an exponent, showing how many bit po
HI, I have a 14-bit data that is fed from FPGA in vhdl, The NIos II processor reads the 14-bit data from FPGA and do some processing tasks, where Nios II system is programmed in C code The 14-bit data can be positive, zero or negative. In Altera compiler, I can only define the data to be 8,16 or 32
Yes. range indeces are in decimal by default, so 001000010000 is 10 billion, 10 thousand. Not the binary form (this is larger than the range of integer). You need to format the number with: 2#00100001000# to make it a binary representation of an integer (or 16#208# if you want hex) and I think the error comes from using the to_integer function -
I have some real numbers like 9.123472e+002. I need to print these to a file after converting them to normal decimal number representation from scientific representation like in this example I want to write 912.3472 to the file instead of writing 9.123472e+002. Any idea how to do this in vhdl? Any library functions to do this job?
Who can you please tell me how to order the BASYS 2 decimal point ?Please
You are not doing binary to decimal conversion, the output is still Binary. You are taking the absolute value of the vector. what input does the dac expect? Signed binary or offset unsigned binary?
Hi Manasi, The same way You can broken the input BCD value into chunks of 4 and represent it in decimal. Once you broken the BCD value into 4 bit of chunks, it will contains values from "0000" to "1001", means in decimal it is from 0 to 9. Can you specify the input and output ports for your design, with number of bits ?
Hi, How to convert integer value into decimal in vhdl. I am trying to use conv_std _logic _vector But I am getting some error like below: Undefined symbol 'conv_std_logic_vector'. conv_std_logic_vector: Undefined symbol (last report in this block) How can I solve the problem?. Regards xilinx1001
Hi dear friends, Can anybody help me about this calculation (showns below) in vhdl. Otherwise, I will become such an insane. Xn+1 = 4*Xn*(1-Xn) Xn+1 is a new value and Xn is past. Xn will always be in the range of 0< Xn< 1. Xn is float number with 10 decimal point. inital value of Xn is 0.25. So how can I obtain a suitable code fo
With a good scaling factor, you can get rid of the decimals (between 0 and 1). And as FvM suggests, if it is your intention to make your functions synthesizable, 8 bit resolution might be on the low side, but 16 bit video is already on the high side. Maybe some food for thought: how is your outside world communicating with your FPGA? I doubt if it
Hi everybody, I am trying to test out my chip's functionality on vhdl before going ahead. I wanted to know how to simulate decimal point delays like: s <= d after 1.54 ns; vhdl treats that as 2 ns delay. I want to know how to make the compiler simulate decimal point delays. Any help appreciated. Thanks.
hello can I define 2 bit of signal that the type of it is std_logic_vector (12 downto 0) as decimal?
I am trying to write the vhdl code for a Timing Genarator Chip : in the vhdl code i have to incorporate a code for the 16 Bit BCD(Binary Coded decimal) Counter i.e. 4 Decades , i tried a lot but unable to figure it out how to get it working... as the 16 bit BCD counter can count from 0 to 9999 ,for the first 9 clock pulses i can easily cre
Dear all , I am trying to build a comparator in vhdl for a 5-port router north port ,south , east ,west and local port to processing unit I will have an input of 4 bits and these 4 bits will be compared with some x,y coordinates stored for each router's comparator. So lets say that the coordinates are x=1 and y=2 . The coordinates show th
i would say represent 0.390625 in binary in binary it is 0.011001 Now look at the bits to the right of the point. It is 011001 which is 25 in decimal Now look at the binary point and count the number of shifts that you need to make to go from 0.11001 to 011001.0. You need 6 right shifts which mean you divide by 64 So that is all.
Obviously, you can only feed back 8 bits of the result. You have to decide about the intended adder behaviour. It can be either wrap around (simply ignoring the two most significant bits) or saturation, limiting the result to 255 (decimal).
The weight of the lowest fractional bit is 1/16 or 0.0625, so you would need four display digits to represent it exactly. If this is what you want, you can multiply with 625 and convert to decimal. Or just use a look-up table of intended representations with your selected width, as TrickyDicky suggested.
firstly, you should read up a small amount about floating point implementations. In the end, I suggest using a fixed point implementation instead. This is where a decimal point is added. eg, 110010.11 -- a 6.2 fixed point. Math is done as normal, but the decimal point is tracked. eg a 6.2 fixed point, multiplied by 1/4 would simply be a 4.4 fi
your title and your question in the post are 2 different things. Elexan has anwered your question in the post. But for the question in the title - std_logic_vector is not a number, so you have to type convert via the unsigned or signed type to get a std_logic_vector. My main question is why do you want to assign a decimal number to a std_logi
When using std_logic_vectors(xx down to yy) I can use either binary numbers in the form "11010101" or hex numbers in the form x"00". How can I use decimal numbers?
these are based integers these are literals of vhdl e.g. decimal integers: 1 42 153_1203 Based integers: 2#1_0010# 16#F001D# Characters: ’0’ ’1’ ’X’ Strings: "101011" "XXXXXX" Bit string literals: B"1001_0101" X"95" mean "10010101" Underscores added for readability are ignored
hi can any one help me how to convert decimal values into 8 bit binary number. decimal values are actually the image pixel values arranged in matrix form in text file. using vhdl.
a true WTF is that they needed to represent the value 'zero' in hex rather than decimal. (Unless this was just one row in a bunch, and all the other rows actually made sense to be hex: 16#4#, 16#8#, 16#C#, 16#F#, etc.)
my input is of format -6.5 or 10.55 Very unlikely, that's just a decimal number string. Real is a vhdl type available for compile time calculations and simulation. It's not synthesizable. Standard vhdl libraries are providing only integer numbers (unsigned and signed). In addition, there are proposed IEEE libraries for fixe
i am trying to implement pi and pid controller on fpga using vhdl programming and i am finding it difficult to use ki, kp and kd values which are decimal or real in nature. i understand that vhdl is strongly typed language and it does not accept ordinar conventional type transformations. so i need some feeds on this. thankyou.
Hello 1- No one is going to "draw" the code for you. 2- concerning the 4 leds problem, for any multiplier it is very common to just neglect half of the bits(or less) in the result register. For example 1011)binary * 0010)binary which is 11x2 in decimal the exact result should be 00010110, now we can either throw the most 4-bits or the least
So the value will always be between 0 and 1 and I require upto 3 decimal places. Binary arithmetic doesn't know decimal places. You have to choose a suitable representation for the result first. My suggestion would be a binary fixed point format with a factor of 2**10. It can be easily achieved by extending the numerator to 34 bit
FPGA do not have support for REAL numbers, you must make a compromise. If you have only 2 decimal values, you can save the value x 100 in the lookup table, for that, you need to create a memory type, and put the values as constants. Take a look at this for an example: Lookup table can be a ROM :)
hi, sir, i'm working on DA-FIR filter generation using sysgen. i want to design a LUT for the same . so i am using vhdl code to design the LUT. i have designed the FIR filter. so i'm getting the coefficients form it . there are real numbers.. eg: 0.27656, -0.0984,... so initially i have to convert these to 8-bit binary digits. then depending o
how to design a ieee-754 to decimal converter using vhdl.... please help me out by giving a synthesizable code...........
hi can anybody give me vhdl code for binary to decimal or binary to RR-4 no system if you want your decimal only in integer type, then there is a builtin function conv_interger();
i began digital design. i need some good digital design simulation software for simple designs for now ( like bcd to decimal decoder using 74138 and 7404 and 7421 ) i need your advices and cooments :D thanx
Is this a student project for learning digital design? Are you inputting and outputting decimal integers, fractions, hex, or what? How many digits input and output? What type of hardware chips are you allowed to use? Wiring up TTL/CMOS chips could be torture. How about implementing your logic in an FPGA, using Verilog or vhdl?
Hi Everyone, currently i'm doing a final year project. I'm having a problem on the output signal. My It2 doesnt seems to haf clk, it's just gif an output of 0(decimal) all the way. Not like Xr2 or Xi2. The following is my Main program and test bench. The filter is generated from GEN Core. It's a DA FIR 32 tap filter. I dont know where went wrong.
hi all, i feel it is very silly question but it is my first trial ever to write a vhdl code so please help me how can i write decimal numbers in vhdl??i.e 1.2 when i wrote it in binary form vhdl can't understand it any help???
I would do this in Verilog. Verilog doesn't have any fractional data types, so I would simply remember where I put the decimal point. module top (a, b, y); input signed a, b; output signed y; assign y = a * b; endmodule
Please help in displaying the output of 6-bit counter in decimal format instead of hexadecimal on the 2 seven segment displays of FPGA board. Also vhdl code for the debounce of Virtex-II FPGA board from Insight IMPACT with clock speed of 100MHZ
A strongly-typed programming language is one in which each type of data (such as integer, character, hexadecimal, packed decimal, and so forth) is predefined as part of the programming language and all constants or variables defined for a given program must be described with one of the data types. An advantage of strong data typing is that it im
somebody help! how to display an 26-bit binary digit in LED or LCD using decimal style. in addition,the 26-bit binary digit is the output of an FPGA chip. please tell me what should i do and how to describe it in vhdl? thanks very much!! i am waiting on line!
I think you mean fixed point arithmetic? There are lots of references on google. There are no real or fractional data types in hardware. We simply represent it as an integer and declare the position the decimal point lies.
Hello Ahsan, Yes, You can not do the direct decimal Multiplication in vhdl. There are Two alternates for you, 1) You need to use functions to convert from decimal to Bit type and then follow the algorithms, I dont know what algorithms u use. 2) You need to follow the IEEE representation of the Floating Point Representation, for (...)
how can i convert modelsim waveform data into matlab, and simulate it with matlab? another question is how can i convert decimal fraction into binary,my purpose is multiple two decimal fraction and output it finally with fpga.