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Hello Ahsan, Yes, You can not do the direct decimal Multiplication in vhdl. There are Two alternates for you, 1) You need to use functions to convert from decimal to Bit type and then follow the algorithms, I dont know what algorithms u use. 2) You need to follow the IEEE representation of the Floating Point Representation, for (...)
hi all, i feel it is very silly question but it is my first trial ever to write a vhdl code so please help me how can i write decimal numbers in vhdl??i.e 1.2 when i wrote it in binary form vhdl can't understand it any help???
hi can anybody give me vhdl code for binary to decimal or binary to RR-4 no system
hi can any one help me how to convert decimal values into 8 bit binary number. decimal values are actually the image pixel values arranged in matrix form in text file. using vhdl.
Hi everybody, I am trying to test out my chip's functionality on vhdl before going ahead. I wanted to know how to simulate decimal point delays like: s <= d after 1.54 ns; vhdl treats that as 2 ns delay. I want to know how to make the compiler simulate decimal point delays. Any help appreciated. Thanks.
You are not doing binary to decimal conversion, the output is still Binary. You are taking the absolute value of the vector. what input does the dac expect? Signed binary or offset unsigned binary?
I have some real numbers like 9.123472e+002. I need to print these to a file after converting them to normal decimal number representation from scientific representation like in this example I want to write 912.3472 to the file instead of writing 9.123472e+002. Any idea how to do this in vhdl? Any library functions to do this job?
Hi, I see you are trying to synthesize with XST an entity with 'real' ports... not good m8. So what do you think the synthesizer will do? :? Synthesizers don't support reals, at least XST doesn't, maybe Precision or Synplify can figure out how deep you want the port to be and constraint it to 32 bits... although I don't think so. So
I think you mean fixed point arithmetic? There are lots of references on google. There are no real or fractional data types in hardware. We simply represent it as an integer and declare the position the decimal point lies.
Please help in displaying the output of 6-bit counter in decimal format instead of hexadecimal on the 2 seven segment displays of FPGA board. Also vhdl code for the debounce of Virtex-II FPGA board from Insight IMPACT with clock speed of 100MHZ
SA Ahmad, I must be missing something in your questions, since I find no problem in representing negative fractions in binary form and using 2's complements. Regarding their representation and the matter of accuracy, you may prefer using this library found at: Check the fixed_
Hi, I am new to vhdl. And I try to convert to verilog. -- signal internalCNT, CNTupto, internalCNTaddr: std_logic_vector(11 downto 0); type errorLOCtype is array (7 downto 0) of std_logic_vector(7 downto 0); signal errorLOC: errorLOCtype; ........ ........ ..... case errorLOC(conv_integer(internalCNT(1 downto 0) & '0'))(
Dear Sir, I invented new methods for decimal to binary conversion etc. I want to implement that method in devices (About 20 new operations ) to get patent.I also wants to compare the time required to do the same by other best method.Can i go with FPGA? or any other?or with microcontrollers? WHat is the procedure and devices i needs to buy. Which
supposed an unsigned vector A_UNS which represent 4.3 in form q.r: 4 : represents 4-bit of the QUOTIENT 3 : represents 3-bit of the REMAINDER for example: decimal vector 9.125 is represented in binary as A_UNS="1001.001" the simulator will show A_UNS as 73 =======> "1001001"b=73d if I will apply grouping signal I may seperate the QUOTIENT
I'm a beginner with this program...anybody has a sample program with this,,,,it will serve as my guide....just a simple codes adding 2bits binary or decimal digits .....thank you...
hello, you can use matlab which can help you to convert decimal integer to hex format and write into a file with the vendor needed format. the matlab function: dec2hex can help you. good luck.
You should have learned from the detailed answers to your question at other forums, that you have to implement the IEEE float format in your design, cause it's not provided by standard vhdl libraries. The complexity of your design depends on the intended decimal point options in decimal format, which hasn't been mentioned. If you are (...)
how to design a ieee-754 to decimal converter using vhdl.... please help me out by giving a synthesizable code...........
FPGA do not have support for REAL numbers, you must make a compromise. If you have only 2 decimal values, you can save the value x 100 in the lookup table, for that, you need to create a memory type, and put the values as constants. Take a look at this for an example: Lookup table can be a ROM :)
Hi, sir, i want to convert a decimal number ( eg : 0.256, -0.984, -1.25,..) to binary. can anybody please help me, how could this be done in vhdl. thanking you, sincerely, shree
Hello 1- No one is going to "draw" the code for you. 2- concerning the 4 leds problem, for any multiplier it is very common to just neglect half of the bits(or less) in the result register. For example 1011)binary * 0010)binary which is 11x2 in decimal the exact result should be 00010110, now we can either throw the most 4-bits or the least
So the value will always be between 0 and 1 and I require upto 3 decimal places. Binary arithmetic doesn't know decimal places. You have to choose a suitable representation for the result first. My suggestion would be a binary fixed point format with a factor of 2**10. It can be easily achieved by extending the numerator to 34 bit
i am trying to implement pi and pid controller on fpga using vhdl programming and i am finding it difficult to use ki, kp and kd values which are decimal or real in nature. i understand that vhdl is strongly typed language and it does not accept ordinar conventional type transformations. so i need some feeds on this. thankyou.
my input is of format -6.5 or 10.55 Very unlikely, that's just a decimal number string. Real is a vhdl type available for compile time calculations and simulation. It's not synthesizable. Standard vhdl libraries are providing only integer numbers (unsigned and signed). In addition, there are proposed IEEE libraries for fixe
these are based integers these are literals of vhdl e.g. decimal integers: 1 42 153_1203 Based integers: 2#1_0010# 16#F001D# Characters: ’0’ ’1’ ’X’ Strings: "101011" "XXXXXX" Bit string literals: B"1001_0101" X"95" mean "10010101" Underscores added for readability are ignored
Do you mean in simulation? Most simulators can display signed and unsigned signals as a waveform instead of hex, decimal and so on.
your title and your question in the post are 2 different things. Elexan has anwered your question in the post. But for the question in the title - std_logic_vector is not a number, so you have to type convert via the unsigned or signed type to get a std_logic_vector. My main question is why do you want to assign a decimal number to a std_logi
The weight of the lowest fractional bit is 1/16 or 0.0625, so you would need four display digits to represent it exactly. If this is what you want, you can multiply with 625 and convert to decimal. Or just use a look-up table of intended representations with your selected width, as TrickyDicky suggested.
Hello, I'm using the following division function in my vhdl code: ---------------------------------------------------------------- function divide (a : UNSIGNED; b : UNSIGNED) return UNSIGNED is variable a1 : unsigned(a'length-1 downto 0):=a; variable b1 : unsigned(b'length-1 downto 0):=b; variable p1 : unsigned(b'length downto 0):= (
Obviously, you can only feed back 8 bits of the result. You have to decide about the intended adder behaviour. It can be either wrap around (simply ignoring the two most significant bits) or saturation, limiting the result to 255 (decimal).
A testbench can process real data and convert it to fixed point as well. If you generate e.g sine waveforms in a testbench, they are originally real quantities, you always need to convert them to numbers understood by the design under test design. There's however a point of chosing the best format for the data files to be read in by the test ben
My input is a 12bit value form a DAC output. (0..4095 in decimal) I'm using 4 seven segment display, where i willing to see voltage in this form: x.yyy where X is the integer part, yyy is the fraction. In Xilinx ISE, there is problems with fixed / floating points package, so i had to work with integer values only. (see my project in youtube for eas
Hey Folks, I'm having a rough time with my vhdl, I get so many errors all the time it's discouraging. I like doing it but man, it's slow going. :( Now my vhdl State machine isn't working. I have to use case statements for this part of my LAB. I'm trying to have a series of output ports go HIGH for a certain counter state. So I have my Addr
i would say represent 0.390625 in binary in binary it is 0.011001 Now look at the bits to the right of the point. It is 011001 which is 25 in decimal Now look at the binary point and count the number of shifts that you need to make to go from 0.11001 to 011001.0. You need 6 right shifts which mean you divide by 64 So that is all.
Dear all , I am trying to build a comparator in vhdl for a 5-port router north port ,south , east ,west and local port to processing unit I will have an input of 4 bits and these 4 bits will be compared with some x,y coordinates stored for each router's comparator. So lets say that the coordinates are x=1 and y=2 . The coordinates show th
I am writing a vhdl code for a serial interface, now for the purpose of automation i will be writing a perl script or a C code saved as so that i will supply the decimal numbers to the script read from a file named data.txt and will generate the desired binary numbers and store them in another text file named decimal2bi
I am trying to write the vhdl code for a Timing Genarator Chip : in the vhdl code i have to incorporate a code for the 16 Bit BCD(Binary Coded decimal) Counter i.e. 4 Decades , i tried a lot but unable to figure it out how to get it working... as the 16 bit BCD counter can count from 0 to 9999 ,for the first 9 clock pulses i can easily cre
Well I have a matrix that its elements are between 0 and 1 (e.g 0.976) and I want to use it as my design as inputs (my design inputs are 32 bit and fixed point). so i need to convert the matrix values to their binary representation and then use them in the rest of design. So how can i do it? is there any vhdl function that read these decimal number
Hi dear friends, Can anybody help me about this calculation (showns below) in vhdl. Otherwise, I will become such an insane. Xn+1 = 4*Xn*(1-Xn) Xn+1 is a new value and Xn is past. Xn will always be in the range of 0< Xn< 1. Xn is float number with 10 decimal point. inital value of Xn is 0.25. So how can I obtain a suitable code fo
Using vhdl integers breaks down at 32 bits, since you need something larger you should be using 'signed' and 'unsigned' types from the ieee.numeric_std library. Vector length of these types is virtually unlimited (i.e. you can have on the approximately 2^32 bits in the vector as opposed to just 32 bits that represents integers).
Apparently it does: d Matches an optionally signed decimal number, consisting of the optional sign from the set + or -, followed by a sequence of characters from the set 0,1,2,3,4,5,6,7,8,9 and _, or a single value from the set x,X,z,Z,?. I would prefer text format and decimal numbers for testbenches.
Hi, How to convert integer value into decimal in vhdl. I am trying to use conv_std _logic _vector But I am getting some error like below: Undefined symbol 'conv_std_logic_vector'. conv_std_logic_vector: Undefined symbol (last report in this block) How can I solve the problem?. Regards xilinx1001
I was literally stuck witha problem regarding the conversion of negative floating point in binary and to write it in vhdl.For example the num is -0.8.when i convert it into binary it is like .11001100.since it is -ve i have to convert it into 2's complement and to provide the extra MSB bit.
Hi all; I want to write a function for converting a BCD number into decimal in vhdl. I looked for algorithms online but did not quite understand the logic behind it. I feel one can do it following way: I have an address input as BCD value. So it can be broken into the chunks of 4 bits. And then converted into the corresponding (...)
I'm not sure what's your exact problem because your posts are adressing different points. In my view, the interesting point is generating respectively converting "good looking" fonts with required bitmap size. The other point is about programming, converting between different data formats. Binary fonts can e.g have vertical or horizontal ori
Why don't you write down an example with input, expected intermediate results and output data? You can use it also to check the calculation steps in simulation yourself. Presently I don't even understand the presentation of simulation data. Why do you split Q into 3 decimal numbers instead of displaying it binary?
Who can you please tell me how to order the BASYS 2 decimal point ?Please
I am not familiar with ASIC design flow, maybe somebody else can give some valuable comments.... For FPGA design, what I have used synthesis tools(only to synthesis vhdl code): Synplicity Synplify > Synopsys FPGA Compiler II > Mentor Leonardo Exemplar It is only my personal opinion...
If you want an audio interactive tutor to learn Verilog or vhdl.. I did upload it for someone who did ask me... ES PERAN Verilog & vhdl. If you are interested let me know Kind regards.
I am a student from Harbin China. Now I am building a behavioral model of a Direct Sequence Spread Spectrum Communication system using vhdl-AMS. So i want to know where can I find some example similar to that or something that may give help to me. Can you give me some advices. Thank you! [ This Message was edited by: flybear on