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73 Threads found on Decimal Vhdl
Hello Ahsan, Yes, You can not do the direct decimal Multiplication in vhdl. There are Two alternates for you, 1) You need to use functions to convert from decimal to Bit type and then follow the algorithms, I dont know what algorithms u use. 2) You need to follow the IEEE representation of the Floating Point Representation, for (...)
Hi, I see you are trying to synthesize with XST an entity with 'real' ports... not good m8. So what do you think the synthesizer will do? :? Synthesizers don't support reals, at least XST doesn't, maybe Precision or Synplify can figure out how deep you want the port to be and constraint it to 32 bits... although I don't think so. So
I think you mean fixed point arithmetic? There are lots of references on google. There are no real or fractional data types in hardware. We simply represent it as an integer and declare the position the decimal point lies.
Please help in displaying the output of 6-bit counter in decimal format instead of hexadecimal on the 2 seven segment displays of FPGA board. Also vhdl code for the debounce of Virtex-II FPGA board from Insight IMPACT with clock speed of 100MHZ
hi all, i feel it is very silly question but it is my first trial ever to write a vhdl code so please help me how can i write decimal numbers in vhdl??i.e 1.2 when i wrote it in binary form vhdl can't understand it any help???
SA Ahmad, In all cases your I and Q are buses. Even in QPSK and BPSK you are transmitting +1's and -1's not only a 1 and a 0. You have to perform level mapping as shown in the constellation diagrams you sent earlier. In QPSK and BPSK a signed vector of 2 bit width would do, but in the 16 QAM you would need to make the I and Q
Hi, I am new to vhdl. And I try to convert to verilog. -- signal internalCNT, CNTupto, internalCNTaddr: std_logic_vector(11 downto 0); type errorLOCtype is array (7 downto 0) of std_logic_vector(7 downto 0); signal errorLOC: errorLOCtype; ........ ........ ..... case errorLOC(conv_integer(internalCNT(1 downto 0) & '0'))(
Hi Everyone, currently i'm doing a final year project. I'm having a problem on the output signal. My It2 doesnt seems to haf clk, it's just gif an output of 0(decimal) all the way. Not like Xr2 or Xi2. The following is my Main program and test bench. The filter is generated from GEN Core. It's a DA FIR 32 tap filter. I dont know where went wrong.
Dear Sir, I invented new methods for decimal to binary conversion etc. I want to implement that method in devices (About 20 new operations ) to get patent.I also wants to compare the time required to do the same by other best method.Can i go with FPGA? or any other?or with microcontrollers? WHat is the procedure and devices i needs to buy. Which
supposed an unsigned vector A_UNS which represent 4.3 in form q.r: 4 : represents 4-bit of the QUOTIENT 3 : represents 3-bit of the REMAINDER for example: decimal vector 9.125 is represented in binary as A_UNS="1001.001" the simulator will show A_UNS as 73 =======> "1001001"b=73d if I will apply grouping signal I may seperate the QUOTIENT
I'm a beginner with this program...anybody has a sample program with this,,,,it will serve as my guide....just a simple codes adding 2bits binary or decimal digits .....thank you...
hi can anybody give me vhdl code for binary to decimal or binary to RR-4 no system
I tend not to do the homework of students. However, everyone needs to learn... So, let's analyse the system: 1. I don't know what a Fisher chess clock is, but I guess that it will be a variant of a seconds/minutes timer with start/stop/reset buttons. What are your inputs/what outputs do you foresee? Input: Clk (usually something in the rang
hello, you can use matlab which can help you to convert decimal integer to hex format and write into a file with the vendor needed format. the matlab function: dec2hex can help you. good luck.
can anybody help me designing ieee-754 to decimal converter using vhdl.... and it should be synthesizable,,,,,,,,,,,,,,,,,,,,,, i've done it but i m not able to synthesize coz i m using reaL DATA TYPE ...... just help me out.............. how should i perform the float operations
how to design a ieee-754 to decimal converter using vhdl.... please help me out by giving a synthesizable code...........
Counting to 50000000 during one second requires 26 bit. Since you want a 8 bit result we only pass on the highest 8 bits, which is basically a 'div' operation. result(7 downto 0) <= counter(25 downto 18) Mind you, since 50000000 does not exactly fit in 26 bit (26 bit == 67 MHz full range) we do loose some range. An exact 'scaling'
Scales 50e6 to 190 instead of 255. If a better scaling is intended, you need a multiplier. As a more simple solution, adjust the gate time accordingly. can u simplify what u want to say. actually i have counted the pulses now only wanted to scale the decimal values to 8-bit binary. i also tried to do using 8-bit flip flop co
hi, sir, i'm working on DA-FIR filter generation using sysgen. i want to design a LUT for the same . so i am using vhdl code to design the LUT. i have designed the FIR filter. so i'm getting the coefficients form it . there are real numbers.. eg: 0.27656, -0.0984,... so initially i have to convert these to 8-bit binary digits. then depending o
FPGA do not have support for REAL numbers, you must make a compromise. If you have only 2 decimal values, you can save the value x 100 in the lookup table, for that, you need to create a memory type, and put the values as constants. Take a look at this for an example: Lookup table can be a ROM :)
Hi, sir, i want to convert a decimal number ( eg : 0.256, -0.984, -1.25,..) to binary. can anybody please help me, how could this be done in vhdl. thanking you, sincerely, shree
Hello 1- No one is going to "draw" the code for you. 2- concerning the 4 leds problem, for any multiplier it is very common to just neglect half of the bits(or less) in the result register. For example 1011)binary * 0010)binary which is 11x2 in decimal the exact result should be 00010110, now we can either throw the most 4-bits or the least
So the value will always be between 0 and 1 and I require upto 3 decimal places. Binary arithmetic doesn't know decimal places. You have to choose a suitable representation for the result first. My suggestion would be a binary fixed point format with a factor of 2**10. It can be easily achieved by extending the numerator to 34 bit
i am trying to implement pi and pid controller on fpga using vhdl programming and i am finding it difficult to use ki, kp and kd values which are decimal or real in nature. i understand that vhdl is strongly typed language and it does not accept ordinar conventional type transformations. so i need some feeds on this. thankyou.
Hii friends, this site is very useful for the students and this is the first time I am posting and please make me happy....... For your design project you will be creating a simple calculator. The calculator has a keypad as its input. The keypad has the decimal numbers 0 ? 9, clear,=, + and -. You will only be implementing addition and subtracti
my input is of format -6.5 or 10.55 Very unlikely, that's just a decimal number string. Real is a vhdl type available for compile time calculations and simulation. It's not synthesizable. Standard vhdl libraries are providing only integer numbers (unsigned and signed). In addition, there are proposed IEEE libraries for fixe
a true WTF is that they needed to represent the value 'zero' in hex rather than decimal. (Unless this was just one row in a bunch, and all the other rows actually made sense to be hex: 16#4#, 16#8#, 16#C#, 16#F#, etc.)
hi can any one help me how to convert decimal values into 8 bit binary number. decimal values are actually the image pixel values arranged in matrix form in text file. using vhdl.
these are based integers these are literals of vhdl e.g. decimal integers: 1 42 153_1203 Based integers: 2#1_0010# 16#F001D# Characters: ’0’ ’1’ ’X’ Strings: "101011" "XXXXXX" Bit string literals: B"1001_0101" X"95" mean "10010101" Underscores added for readability are ignored
Do you mean in simulation? Most simulators can display signed and unsigned signals as a waveform instead of hex, decimal and so on.
your title and your question in the post are 2 different things. Elexan has anwered your question in the post. But for the question in the title - std_logic_vector is not a number, so you have to type convert via the unsigned or signed type to get a std_logic_vector. My main question is why do you want to assign a decimal number to a std_logi
The weight of the lowest fractional bit is 1/16 or 0.0625, so you would need four display digits to represent it exactly. If this is what you want, you can multiply with 625 and convert to decimal. Or just use a look-up table of intended representations with your selected width, as TrickyDicky suggested.
result <= divide("10110011101111", "10011100010000") -- 11503/10000 should be also "00000000000001" but it's... "11010001100001"(wich is 13409 in unsigned decimal) I have simulated it. The result is correct ("00000000000001") for these numbers if you make sure that you implement the bug fix in my earlier post. With th
Obviously, you can only feed back 8 bits of the result. You have to decide about the intended adder behaviour. It can be either wrap around (simply ignoring the two most significant bits) or saturation, limiting the result to 255 (decimal).
A testbench can process real data and convert it to fixed point as well. If you generate e.g sine waveforms in a testbench, they are originally real quantities, you always need to convert them to numbers understood by the design under test design. There's however a point of chosing the best format for the data files to be read in by the test ben
My input is a 12bit value form a DAC output. (0..4095 in decimal) I'm using 4 seven segment display, where i willing to see voltage in this form: x.yyy where X is the integer part, yyy is the fraction. In Xilinx ISE, there is problems with fixed / floating points package, so i had to work with integer values only. (see my project in youtube for eas
Hey Folks, I'm having a rough time with my vhdl, I get so many errors all the time it's discouraging. I like doing it but man, it's slow going. :( Now my vhdl State machine isn't working. I have to use case statements for this part of my LAB. I'm trying to have a series of output ports go HIGH for a certain counter state. So I have my Addr
i would say represent 0.390625 in binary in binary it is 0.011001 Now look at the bits to the right of the point. It is 011001 which is 25 in decimal Now look at the binary point and count the number of shifts that you need to make to go from 0.11001 to 011001.0. You need 6 right shifts which mean you divide by 64 So that is all.
On real hardware there is no such thing as decimal. All numbers are binary. In vhdl you can compare arrays to decimal values just so its easy to read. You can split up any array by indexing the bits: if din(1 downto 0) > 1 then .. elsif din(3 downto 2) > 1 then etc. You need to use the numeric_std package to convert the input to (...)
I am writing a vhdl code for a serial interface, now for the purpose of automation i will be writing a perl script or a C code saved as so that i will supply the decimal numbers to the script read from a file named data.txt and will generate the desired binary numbers and store them in another text file named decimal2bi
I am trying to write the vhdl code for a Timing Genarator Chip : in the vhdl code i have to incorporate a code for the 16 Bit BCD(Binary Coded decimal) Counter i.e. 4 Decades , i tried a lot but unable to figure it out how to get it working... as the 16 bit BCD counter can count from 0 to 9999 ,for the first 9 clock pulses i can easily cre
See from your spec, you have a 5oHz clk -> 0.02s period => 1200 clk cycles will account for your 24s need. Now converting 1200 into binary format provides 10010110000 which is a 11-bit no. Hence the 11 bit counter comes into picture. Now you can input your clk and make the counter count till 10010110000 which will be
We would prefer a slightly clearer question. What is the relation of decimal <> real number <> 2 bit <> std_logic_vector ???
Hi all, In the process of digital to analog conversion, the thermometer code output, corresponding to the digital value of the input signal, activates the unit value of the analog entities (which may be current or voltage sources). The analog output is the summation of all those activated analog entities. Please can any one help me or give me
Hi all, In the process of digital to analog conversion, the thermometer code output, corresponding to the digital value of the input signal, activates the unit value of the analog entities (which may be current or voltage sources). The analog output is the summation of all those activated analog entities. Please can any one help me or give me
Hi everybody, I am trying to test out my chip's functionality on vhdl before going ahead. I wanted to know how to simulate decimal point delays like: s <= d after 1.54 ns; vhdl treats that as 2 ns delay. I want to know how to make the compiler simulate decimal point delays. Any help appreciated. Thanks.
With a good scaling factor, you can get rid of the decimals (between 0 and 1). And as FvM suggests, if it is your intention to make your functions synthesizable, 8 bit resolution might be on the low side, but 16 bit video is already on the high side. Maybe some food for thought: how is your outside world communicating with your FPGA? I doubt if it
Hi dear friends, Can anybody help me about this calculation (showns below) in vhdl. Otherwise, I will become such an insane. Xn+1 = 4*Xn*(1-Xn) Xn+1 is a new value and Xn is past. Xn will always be in the range of 0< Xn< 1. Xn is float number with 10 decimal point. inital value of Xn is 0.25. So how can I obtain a suitable code fo
Using vhdl integers breaks down at 32 bits, since you need something larger you should be using 'signed' and 'unsigned' types from the ieee.numeric_std library. Vector length of these types is virtually unlimited (i.e. you can have on the approximately 2^32 bits in the vector as opposed to just 32 bits that represents integers).
I need some special counter, time actually divider. Inputs - clock - enable - reset - load - PC 30bit duration of positive output - ND 8bit divider for negative output Output - 1 for clock * PC, 0 for clock * PC / ND Example 1 clock is 1us, PC=1E6 decimal, ND=1000 output log1 for 1s and log0 for 1ms Example 3 clock is 1us, PC=100