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73 Threads found on edaboard.com: **Decimal Vhdl**

Hello Ahsan,
Yes, You can not do the direct **decimal** Multiplication in **vhdl**.
There are Two alternates for you,
1) You need to use functions to convert from **decimal** to Bit type and then follow the algorithms, I dont know what algorithms u use.
2) You need to follow the IEEE representation of the Floating Point Representation, for (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 18.08.2004 08:07 :: reddy :: Replies: **1** :: Views: **3048**

Hi,
I see you are trying to synthesize with XST an entity with 'real' ports... not good m8.
So what do you think the synthesizer will do? :?
Synthesizers don't support reals, at least XST doesn't, maybe Precision or Synplify can figure out how deep you want the port to be and constraint it to 32 bits... although I don't think so.
So

PLD, SPLD, GAL, CPLD, FPGA Design :: 21.10.2004 04:20 :: maestor :: Replies: **8** :: Views: **2638**

I think you mean fixed point arithmetic? There are lots of references on google. There are no real or fractional data types in hardware. We simply represent it as an integer and declare the position the **decimal** point lies.

PLD, SPLD, GAL, CPLD, FPGA Design :: 15.03.2005 07:58 :: checkmate :: Replies: **7** :: Views: **1447**

Please help in displaying the output of 6-bit counter in **decimal** format instead of hexa**decimal** on the 2 seven segment displays of FPGA board.
Also **vhdl** code for the debounce of Virtex-II FPGA board from Insight IMPACT with clock speed of 100MHZ

PLD, SPLD, GAL, CPLD, FPGA Design :: 12.09.2005 01:48 :: wsu :: Replies: **1** :: Views: **3083**

hi all,
i feel it is very silly question but it is my first trial ever to write a **vhdl** code so please help me
how can i write **decimal** numbers in **vhdl**??i.e 1.2 when i wrote it in binary form **vhdl** can't understand it
any help???

PLD, SPLD, GAL, CPLD, FPGA Design :: 15.02.2007 06:01 :: NoHa111 :: Replies: **2** :: Views: **955**

SA Ahmad,
In all cases your I and Q are buses. Even in QPSK and BPSK you are transmitting +1's and -1's not only a 1 and a 0. You have to perform level mapping as shown in the constellation diagrams you sent earlier.
In QPSK and BPSK a signed vector of 2 bit width would do, but in the 16 QAM you would need to make the I and Q

PLD, SPLD, GAL, CPLD, FPGA Design :: 22.02.2007 06:06 :: ahmad_abdulghany :: Replies: **13** :: Views: **1085**

Hi,
I am new to **vhdl**. And I try to convert to verilog.
--
signal internalCNT, CNTupto, internalCNTaddr: std_logic_vector(11 downto 0);
type errorLOCtype is array (7 downto 0) of std_logic_vector(7 downto 0);
signal errorLOC: errorLOCtype;
........
........
.....
case errorLOC(conv_integer(internalCNT(1 downto 0) & '0'))(

PLD, SPLD, GAL, CPLD, FPGA Design :: 14.03.2007 22:08 :: ankit12345 :: Replies: **4** :: Views: **1909**

Hi Everyone, currently i'm doing a final year project. I'm having a problem on the output signal. My It2 doesnt seems to haf clk, it's just gif an output of 0(**decimal**) all the way. Not like Xr2 or Xi2. The following is my Main program and test bench.
The filter is generated from GEN Core. It's a DA FIR 32 tap filter. I dont know where went wrong.

PLD, SPLD, GAL, CPLD, FPGA Design :: 06.07.2007 03:35 :: YenYu :: Replies: **0** :: Views: **576**

Dear Sir,
I invented new methods for **decimal** to binary conversion etc. I want to implement that method in devices (About 20 new operations ) to get patent.I also wants to compare the time required to do the same by other best method.Can i go with FPGA? or any other?or with microcontrollers? WHat is the procedure and devices i needs to buy. Which

Microcontrollers :: 09.10.2007 05:15 :: Raghavendra L :: Replies: **5** :: Views: **723**

supposed an unsigned vector A_UNS which represent 4.3 in form q.r:
4 : represents 4-bit of the QUOTIENT
3 : represents 3-bit of the REMAINDER
for example:
**decimal** vector 9.125
is represented in binary as A_UNS="1001.001"
the simulator will show A_UNS as 73 =======> "1001001"b=73d
if I will apply grouping signal I may seperate the QUOTIENT

ASIC Design Methodologies and Tools (Digital) :: 19.11.2007 18:06 :: khaila :: Replies: **1** :: Views: **942**

I'm a beginner with this program...anybody has a sample program with this,,,,it will serve as my guide....just a simple codes only...like adding 2bits binary or **decimal** digits .....thank you...

PLD, SPLD, GAL, CPLD, FPGA Design :: 04.12.2007 21:58 :: ece9710 :: Replies: **7** :: Views: **817**

hi can anybody give me **vhdl** code for binary to **decimal**
or binary to RR-4 no system

ASIC Design Methodologies and Tools (Digital) :: 07.12.2007 06:53 :: ameed :: Replies: **1** :: Views: **2856**

I tend not to do the homework of students.
However, everyone needs to learn...
So, let's analyse the system:
1. I don't know what a Fisher chess clock is, but I guess that it will be a variant of a seconds/minutes timer with start/stop/reset buttons.
What are your inputs/what outputs do you foresee?
Input:
Clk (usually something in the rang

PLD, SPLD, GAL, CPLD, FPGA Design :: 07.09.2008 15:02 :: lucbra :: Replies: **3** :: Views: **3285**

hello, you can use matlab which can help you to convert **decimal** integer to hex format and write into a file with the vendor needed format.
the matlab function: dec2hex can help you.
good luck.

PLD, SPLD, GAL, CPLD, FPGA Design :: 14.12.2008 20:48 :: radar08 :: Replies: **2** :: Views: **1022**

can anybody help me designing ieee-754 to **decimal** converter using **vhdl**....
and it should be synthesizable,,,,,,,,,,,,,,,,,,,,,,
i've done it but i m not able to synthesize coz i m using reaL DATA TYPE ......
just help me out..............
how should i perform the float operations

PLD, SPLD, GAL, CPLD, FPGA Design :: 12.03.2009 06:01 :: rahulprajesh :: Replies: **3** :: Views: **3371**

how to design a ieee-754 to **decimal** converter using **vhdl**....
please help me out by giving a synthesizable code...........

PLD, SPLD, GAL, CPLD, FPGA Design :: 16.03.2009 03:48 :: rahulprajesh :: Replies: **0** :: Views: **1261**

Counting to 50000000 during one second requires 26 bit.
Since you want a 8 bit result we only pass on the highest 8 bits, which is basically a 'div' operation.
result(7 downto 0) <= counter(25 downto 18)
Mind you, since 50000000 does not exactly fit in 26 bit (26 bit == 67 MHz full range) we do loose some range.
An exact 'scaling'

PLD, SPLD, GAL, CPLD, FPGA Design :: 14.06.2009 02:58 :: Marcel Majoor :: Replies: **6** :: Views: **5418**

Scales 50e6 to 190 instead of 255. If a better scaling is intended, you need a multiplier. As a more simple solution, adjust the gate time accordingly.
can u simplify what u want to say.
actually i have counted the pulses now only wanted to scale the **decimal** values to 8-bit binary.
i also tried to do using 8-bit flip flop co

PLD, SPLD, GAL, CPLD, FPGA Design :: 14.06.2009 01:47 :: koolslash :: Replies: **3** :: Views: **1831**

hi,
sir, i'm working on DA-FIR filter generation using sysgen. i want to design a LUT for the same . so i am using **vhdl** code to design the LUT. i have designed the FIR filter. so i'm getting the coefficients form it . there are real numbers.. eg: 0.27656, -0.0984,... so initially i have to convert these to 8-bit binary digits. then depending o

PLD, SPLD, GAL, CPLD, FPGA Design :: 24.11.2009 00:50 :: shreeharshakg :: Replies: **0** :: Views: **968**

FPGA do not have support for REAL numbers, you must make a compromise. If you have only 2 **decimal** values, you can save the value x 100 in the lookup table, for that, you need to create a memory type, and put the values as constants.
Take a look at this for an example:
Lookup table can be a ROM :)

PLD, SPLD, GAL, CPLD, FPGA Design :: 07.12.2009 14:29 :: farhada :: Replies: **1** :: Views: **1984**

Hi,
sir, i want to convert a **decimal** number ( eg : 0.256, -0.984, -1.25,..) to binary. can anybody please help me, how could this be done in **vhdl**.
thanking you,
sincerely,
shree

PLD, SPLD, GAL, CPLD, FPGA Design :: 11.12.2009 02:29 :: shreeharshakg :: Replies: **9** :: Views: **1797**

Hello
1- No one is going to "draw" the code for you.
2- concerning the 4 leds problem, for any multiplier it is very common to just neglect half of the bits(or less) in the result register.
For example 1011)binary * 0010)binary which is 11x2 in **decimal** the exact result should be 00010110, now we can either throw the most 4-bits or the least

PLD, SPLD, GAL, CPLD, FPGA Design :: 27.03.2010 16:28 :: sameh_yassin99 :: Replies: **3** :: Views: **2193**

So the value will always be between 0 and 1 and I require upto 3 **decimal** places.
Binary arithmetic doesn't know **decimal** places. You have to choose a suitable representation for the result first. My suggestion
would be a binary fixed point format with a factor of 2**10. It can be easily achieved by extending the numerator to 34 bit

ASIC Design Methodologies and Tools (Digital) :: 27.03.2010 12:25 :: FvM :: Replies: **2** :: Views: **1347**

i am trying to implement pi and pid controller on fpga using **vhdl** programming and i am finding it difficult to use ki, kp and kd values which are **decimal** or real in nature.
i understand that **vhdl** is strongly typed language and it does not accept ordinar conventional type transformations. so i need some feeds on this. thankyou.

Power Electronics :: 13.07.2010 05:47 :: chunduri balaji tilak :: Replies: **0** :: Views: **952**

Hii friends, this site is very useful for the students and this is the first time I am posting and please make me happy.......
For your design project you will be creating a simple calculator. The calculator has a keypad as its input. The keypad has the **decimal** numbers 0 ? 9, clear,=, + and -. You will only be implementing addition and subtracti

PLD, SPLD, GAL, CPLD, FPGA Design :: 07.11.2010 11:15 :: susheelcpanguluri :: Replies: **4** :: Views: **2546**

my input is of format -6.5 or 10.55
Very unlikely, that's just a **decimal** number string.
Real is a **vhdl** type available for compile time calculations and simulation. It's not synthesizable.
Standard **vhdl** libraries are providing only integer numbers (unsigned and signed).
In addition, there are proposed IEEE libraries for fixe

PLD, SPLD, GAL, CPLD, FPGA Design :: 26.02.2011 05:44 :: FvM :: Replies: **1** :: Views: **517**

a true WTF is that they needed to represent the value 'zero' in hex rather than **decimal**. (Unless this was just one row in a bunch, and all the other rows actually made sense to be hex: 16#4#, 16#8#, 16#C#, 16#F#, etc.)

PLD, SPLD, GAL, CPLD, FPGA Design :: 11.03.2011 00:32 :: TA37 :: Replies: **8** :: Views: **2232**

hi can any one help me how to convert **decimal** values into 8 bit binary number. **decimal** values are actually the image pixel values arranged in matrix form in text file. using **vhdl**.

ASIC Design Methodologies and Tools (Digital) :: 25.05.2011 04:45 :: chitra ranganath :: Replies: **1** :: Views: **649**

these are based integers
these are literals of **vhdl**
e.g. **decimal** integers: 1 42 153_1203
Based integers: 2#1_0010# 16#F001D#
Characters: ’0’ ’1’ ’X’
Strings: "101011" "XXXXXX"
Bit string literals: B"1001_0101" X"95"
mean "10010101"
Underscores added for readability are ignored

PLD, SPLD, GAL, CPLD, FPGA Design :: 14.06.2011 06:22 :: ckshivaram :: Replies: **4** :: Views: **358**

Do you mean in simulation? Most simulators can display signed and unsigned signals as a waveform instead of hex, **decimal** and so on.

Digital Signal Processing :: 28.07.2011 04:55 :: FvM :: Replies: **19** :: Views: **1922**

your title and your question in the post are 2 different things.
Elexan has anwered your question in the post.
But for the question in the title - std_logic_vector is not a number, so you have to type convert via the unsigned or signed type to get a std_logic_vector. My main question is why do you want to assign a **decimal** number to a std_logi

PLD, SPLD, GAL, CPLD, FPGA Design :: 27.08.2011 13:45 :: TrickyDicky :: Replies: **3** :: Views: **4816**

The weight of the lowest fractional bit is 1/16 or 0.0625, so you would need four display digits to represent it exactly. If this is what you want, you can multiply with 625 and convert to **decimal**. Or just use a look-up table of intended representations with your selected width, as TrickyDicky suggested.

PLD, SPLD, GAL, CPLD, FPGA Design :: 19.10.2011 04:12 :: FvM :: Replies: **9** :: Views: **1883**

result <= divide("10110011101111", "10011100010000") -- 11503/10000 should be also "00000000000001"
but it's... "11010001100001"(wich is 13409 in unsigned **decimal**)
I have simulated it. The result is correct ("00000000000001") for these numbers if you make sure that you implement the bug fix in my earlier post. With th

PLD, SPLD, GAL, CPLD, FPGA Design :: 02.01.2012 10:57 :: std_match :: Replies: **5** :: Views: **939**

Obviously, you can only feed back 8 bits of the result. You have to decide about the intended adder behaviour. It can be either wrap around (simply ignoring the two most significant bits) or saturation, limiting the result to 255 (**decimal**).

ASIC Design Methodologies and Tools (Digital) :: 15.01.2012 17:50 :: FvM :: Replies: **1** :: Views: **675**

A testbench can process real data and convert it to fixed point as well. If you generate e.g sine waveforms in a testbench, they are originally real quantities, you always need to convert them to numbers understood by the design under test design.
There's however a point of chosing the best format for the data files to be read in by the test ben

Electronic Elementary Questions :: 05.02.2012 05:33 :: FvM :: Replies: **5** :: Views: **755**

My input is a 12bit value form a DAC output. (0..4095 in **decimal**) I'm using 4 seven segment display, where i willing to see voltage in this form: x.yyy where X is the integer part, yyy is the fraction. In Xilinx ISE, there is problems with fixed / floating points package, so i had to work with integer values only. (see my project in youtube for eas

PLD, SPLD, GAL, CPLD, FPGA Design :: 28.02.2012 07:40 :: Kepsz :: Replies: **4** :: Views: **870**

Hey Folks,
I'm having a rough time with my **vhdl**, I get so many errors all the time it's discouraging.
I like doing it but man, it's slow going. :(
Now my **vhdl** State machine isn't working.
I have to use case statements for this part of my LAB.
I'm trying to have a series of output ports go HIGH for a certain counter state.
So I have my Addr

PLD, SPLD, GAL, CPLD, FPGA Design :: 05.03.2012 20:32 :: Gerry_robotics :: Replies: **5** :: Views: **547**

i would say represent 0.390625 in binary
in binary it is 0.011001
Now look at the bits to the right of the point. It is 011001 which is 25 in **decimal**
Now look at the binary point and count the number of shifts that you need to make to go from 0.11001 to 011001.0. You need 6 right shifts which mean you divide by 64
So that is all.

ASIC Design Methodologies and Tools (Digital) :: 15.03.2012 22:52 :: tariq786 :: Replies: **3** :: Views: **401**

On real hardware there is no such thing as **decimal**. All numbers are binary. In **vhdl** you can compare arrays to **decimal** values just so its easy to read.
You can split up any array by indexing the bits:
if din(1 downto 0) > 1 then
..
elsif din(3 downto 2) > 1 then
etc.
You need to use the numeric_std package to convert the input to (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 31.05.2012 07:24 :: TrickyDicky :: Replies: **13** :: Views: **1754**

I am writing a **vhdl** code for a serial interface, now for the purpose of automation i will be writing a perl script or a C code saved as so that i will supply the **decimal** numbers to the script read from a file named data.txt and will generate the desired binary numbers and store them in another text file named **decimal**2bi

PLD, SPLD, GAL, CPLD, FPGA Design :: 10.07.2012 01:36 :: beast_boy :: Replies: **1** :: Views: **572**

I am trying to write the **vhdl** code for a Timing Genarator Chip :
in the **vhdl** code i have to incorporate a code for the 16 Bit BCD(Binary Coded **decimal**) Counter i.e. 4 Decades , i tried a lot but unable to figure it out how to get it working...
as the 16 bit BCD counter can count from 0 to 9999 ,for the first 9 clock pulses i can easily cre

PLD, SPLD, GAL, CPLD, FPGA Design :: 24.07.2012 05:02 :: beast_boy :: Replies: **5** :: Views: **2914**

See from your spec, you have a 5oHz clk -> 0.02s period => 1200 clk cycles will account for your 24s need. Now converting 1200 into binary format provides 10010110000 which is a 11-bit no. Hence the 11 bit counter comes into picture. Now you can input your clk and make the counter count till 10010110000 which will be

PLD, SPLD, GAL, CPLD, FPGA Design :: 31.08.2012 08:02 :: barry :: Replies: **15** :: Views: **744**

We would prefer a slightly clearer question. What is the relation of **decimal** <> real number <> 2 bit <> std_logic_vector ???

PLD, SPLD, GAL, CPLD, FPGA Design :: 18.09.2012 10:20 :: FvM :: Replies: **6** :: Views: **318**

Hi all,
In the process of digital to analog conversion, the thermometer code output, corresponding to the digital value of the input signal, activates the unit value of the analog entities (which may be current or voltage sources). The analog output is the summation of all those activated analog entities.
Please can any one help me or give me

Digital Signal Processing :: 24.09.2012 05:20 :: noura7 :: Replies: **0** :: Views: **197**

Hi all,
In the process of digital to analog conversion, the thermometer code output, corresponding to the digital value of the input signal, activates the unit value of the analog entities (which may be current or voltage sources). The analog output is the summation of all those activated analog entities.
Please can any one help me or give me

Digital Signal Processing :: 24.09.2012 06:25 :: noura7 :: Replies: **3** :: Views: **434**

Hi everybody,
I am trying to test out my chip's functionality on **vhdl** before going ahead. I wanted to know how to simulate **decimal** point delays like:
s <= d after 1.54 ns;
**vhdl** treats that as 2 ns delay. I want to know how to make the compiler simulate **decimal** point delays.
Any help appreciated.
Thanks.

PLD, SPLD, GAL, CPLD, FPGA Design :: 24.10.2012 20:16 :: n_sanjay_n :: Replies: **1** :: Views: **206**

With a good scaling factor, you can get rid of the **decimal**s (between 0 and 1). And as FvM suggests, if it is your intention to make your functions synthesizable, 8 bit resolution might be on the low side, but 16 bit video is already on the high side.
Maybe some food for thought: how is your outside world communicating with your FPGA? I doubt if it

PLD, SPLD, GAL, CPLD, FPGA Design :: 29.11.2012 04:56 :: lucbra :: Replies: **11** :: Views: **2717**

Hi dear friends,
Can anybody help me about this calculation (showns below) in **vhdl**. Otherwise, I will become such an insane.
Xn+1 = 4*Xn*(1-Xn) Xn+1 is a new value and Xn is past. Xn will always be in the range of 0< Xn< 1. Xn is float number with 10 **decimal** point. inital value of Xn is 0.25.
So how can I obtain a suitable code fo

PLD, SPLD, GAL, CPLD, FPGA Design :: 11.01.2013 03:26 :: hitx :: Replies: **8** :: Views: **406**

Using **vhdl** integers breaks down at 32 bits, since you need something larger you should be using 'signed' and 'unsigned' types from the ieee.numeric_std library. Vector length of these types is virtually unlimited (i.e. you can have on the approximately 2^32 bits in the vector as opposed to just 32 bits that represents integers).

PLD, SPLD, GAL, CPLD, FPGA Design :: 29.01.2013 13:22 :: malikkhaled :: Replies: **5** :: Views: **568**

I need some special counter, time actually divider.
Inputs
- clock
- enable
- reset
- load
- PC 30bit duration of positive output
- ND 8bit divider for negative output
Output
- 1 for clock * PC, 0 for clock * PC / ND
Example 1 clock is 1us, PC=1E6 **decimal**, ND=1000
output log1 for 1s and log0 for 1ms
Example 3 clock is 1us, PC=100

PLD, SPLD, GAL, CPLD, FPGA Design :: 04.03.2013 10:09 :: Astrid :: Replies: **1** :: Views: **136**

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