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72 Threads found on edaboard.com: Delay Locked
This circuit shows the operation from 5 V, but you should be able to operate it from 3.3 V. Point VF1 will be the connection to the chip open drain connection. So input from VF1 is locked out until VF4 goes low. Time is set by the RC time constant. After the initial delay, the fault signal will appear on VF5 when generated.
Hi all, I designed delay locked lock which generate 8 phase output for USB2.0 chip (using pdk 65nm). However, I wonder how conditions noise of voltage supply (1V)? I added the sine signal on 1V supply but I don't know clearly magnitude and frequency of it??? and any more difference real conditions? My project will make real USB. So, it is very im
Consider a base delay of one or more cycles +/- a variable fraction.
Hello, sorry if this is a bit vague, but could anyone give me some tips on how to implement a TDC (based on tapped delay structure) in Simulink. There seems to be very little information online on how to simulate such a device in Simulink. I need it for simulation of an All-Digital Phase locked Loop.
The FFs in my simulation have a reset that need to be set to LOW. You should correct the schematic for clarity, but I see that you are actually using a NAND gate in simulation. There's apparently a problem with the reset timing of the DFF model, it seems to expect a longer signal duration. Adding some delay in the reset path sho
hi, I am doing a project on delay locked that i had a doubt that i tested the delay locked loop the output is like this.but in that result the ref clk and output of vcdl wont be locked exactly.can u suggest any idea where it went wrong . 102844. how to calculate the jitter and (...)
Hi everyone, For my master's thesis i need to do system level modeling of DLL in simulink to calculate jitter. Later on design has to be done in cadence. I could not find any reference to implement DLL in simulink. I am stuck with modeling of VCDL(voltage control delay line). Please guide me. thanks a lot!
Hello everyone. I am studing DLL at the moment. Im trying to simulate my DLL Schematic and got curious about the 'locking time' The DLL's sub block 'Charge Pump' generates the 'Control Volatge' which is provided into the 'Voltage Controlled delay Line'. I was curious about the 'Control Voltage' locking time. Exactly when is the loc
Hi All, I have a very basic question, is the locking time of loop depends on the types Phase detector, means if i use PD using static logic (NAND gate) or PD using Dynamic logic(TSPC), which will have better smaller locking time and why(reason). please replay. Thanks
Hi, I am working on delay locked loop design. My concern is related to loop filter capacitor, does loop capacitor can cause loop stability issue. please help in this regards.
Hi, i am working on Voltage controlled delay line (VCDL) for delay locked loop(DLL). i started VCDL design using Replica Bias which is given in razavi book(Fig attached). as mentioned in book, For VDD= 3.3V , i kept VREF = 2.1V , so that to have swing of 1.2V. And kept both M3 and M4 in linear region. The problem i am facing is : 1. The (...)
Hi all, I was going through some docs on a mircrocontroller and I came across a couple of terms: Line locked Clock(LLC) and delay locked Loop(DLL). I really do not the meaning of those. Can anyone plz explain me? Thanks in advance
Hi, Read about how DLL will fail to lock or falsely lock if the initial delay of the vcdl is not between 0.5T to 1.5T of the reference clock. How do i simulate this condition showing? How do i check if the locking is valid and not a false lock? Best Regards, de3n
Hi guys, Why do the locking time or cycle increases when the frequency increases? What is the reason or theory behind this. Thank you. :)
Yes, you can decrease the delay stage to achieve higher frequency operation. However, the lower limiter of frequency might be increased too. I am using 8 delay stages in and a bias circuit in the VCDL, what you mean is that I should reduce the number of delay stages in VCDL in order to reduce the delay of from the start of t
Hi, I need help with my DLL design which consist of a phase detector, charge pump loop filter and a voltage control delay line(VCDL). The input of the phase detector is fed by 2 clocks (clock reference and output clock with is a feedback from the output of the VCDL. The problem I am facing now is that I am unable to lock the reference clk and ou
A auto calibration circuit can be employed for 50% duty cycle correction. The principal is similar to the chargepump in PLL. The on time is used to charge while the off time is used to discharge. The output voltage of chargepump can be used for the edge delay controlling. This feedback loop will calibrate the duty cycle.
Hi guys, I'm doing a project on analog dll, any available references which I am able to refer to? such as design of the phase detector, charge pump and VCDL? please advice. :)
Good day... Please suggest any measures on how to effectively reduce jitter in a delay locked Loop. Thank you.
Good day everybody.. I am doing a delay locked loop.. I can't understand what went wrong... As shown in the figure below, the control voltage from the charge pump already settles (that's one of the criteria for locking ). But the output clock is still not locked with respect to the reference
1) Does Quartus 2 allow to use logic gate to simulate the timing diagram without verilog coding ? 2) Is Quartus 2 able to simulate delay locked Loop?
Hi all, I am a student, would like to design a delay locked loop. Is Pspice able to help me in the simulation ? 1) Is Pspice suitable for a timing simulation? 2)Pspice can change the (process , voltage, temperature )PVT in the setting? 3) Does Pspice can add additional libraries in the tools? or any simulation tools that able help me?
HI iam using first order loop filter. what is the value of loop filter... thanks............
HI EVERYBODY AS I AM DOING A PROJECT IN "BIST CIRCUIT FOR DLL FAULT DETECTION",I WANT TO STUDY THE ANALOG delay locked LOOP CIRCUIT DESIGN and BIST circuit , C CAN ANYBODY SENDS THE REQURIED INFORMATION FOR THIS PROJECT.... THANKS..............
Thats what I was expecting, glad you stated it explicitly! Assuming you'll be targeting Xilinx devices. It has what you call delay locked Loop(DLL), instead of PLL. To utilize DLL in your design you have to generate and instantiate HDL module in you design. Xilinx core generator will take parameter like multiplication/division factor to gene
falsh locking happens when the delay line is too long or too short, where it goes 1 or more cycles ahead, and still can reach the lock status. don't know how to fix, might need very careful control at the beginning of locking operation, use a counter or something to limit your delayline range.
Hi all, I hope I could have some real help from the DLL experts in this forum. Let me first describe my problem referring to the attached file. Basically I want to make a delay locked Loop. However, the delay lines inside the loop are composed of (1-delta%) and delta% which give the total 100% delay (or (...)
Hi, I have a question for delay locked loop. When a DLL is correctly locked, the total delay of the delay line should equal one period of the reference clock ? or it can be two or more reference clock cycles ? regards, Jef
Hello everyone, Has anybody tried simulating delay locked Loop in simulink. I am starting off my thesis and it would be really helpful if anyone can attach the simulink files for DLL. I searched everywhere in this website and couldnt find any helpful information to start off. Thanks a lot! Best Regards
hi as far as i knew, in DDR-1 memory systems, only the memory controller has a DLL circuit (delay-locked-loop), but the memory chips dont have. so during writes the data and strobe have 90deg phase difference on the board traces, during reads, they have 0deg (controller makes the 90deg delay on the incoming strobe signals). i heard, (...)
How to caculate the bandwidth of a digital delay locked loop? I hope an easy way to get the close loop bandwidth of a fully digital DLL(use updown counter as lpf).Thanks. BR eric 11/30
If what you meant was an Digital module. i.e ASIC or FPGA design... then you have to reduce your critical timing delay of you design....
can anybody tell me whether delay line in digital delay locked loop can be realized in fpga
can any body help me in modelling dll in verilog,
A DLL is a delay locked loop. Rather than adjust the phase until the error is zero, the output signal is delay with a tapped delay line and the taps are adjusted until the delay error is minimal. Zero error cannot usually be obtained because of the coarseness of the delay steps. On some (...)
How do we calculated the lock range, capture range, acquisition time, lock in time in a delay locked loop... and how to find the gains of the phase detector, VCDL, loop filter.... we have to assume the charge pump current..? or we have to assume the loop filter capacitor..? how to charecterrize this...?
Hi all, Can anyone give the main applications of delay locked loops and their usage etc Thanks
Dear All: I am surveying the Matlab product for phase/delay locked loop design/simulation. Except the main program of Matlab and Simulink, Which toolboxes are also helpful for the PLL/DLL simulation?? Thanks a lot. slchen Communication Blockset, SimPowerSystems, Simulink Extras.
Hi anybody I want double my input clock frequency. Except use PLL, is there any other circuit can realize this function? My input clock frequency is 250Mhz, output clock duty cycle shold be 40%~60%, propagation delay should be <2ns. thanks very much
The Spartan 2E was designed before they started incorporating the DCM as one function. Back in these older parts, the clock generation was called a DLL, for delay locked loop. The operation is very similar to a PLL. The main difference is the delay elements can be adjusted only in discrete steps rather than continually like a PLL. (...)
first: and: then very intuitive the differences between those: do you need more scientific?
HAI, I HAVE SIMULATED THE DLL USING SIMULINK. I USED A GENERAL BLOCK WHICH CONSISTS OF PHASE DETECTOR, CHARGE PUMP OR DIGITAL CONTROLLER OR DIGITALLY CONTROLLED delay LINE or VOLTAGE CONTROLLED delay LINE . I am facing problems with CP or digtial controller and DCDL or VCDL. Can anyone post me a good working block of CP or digtial contro
Hi, I require some design concepts and techniques involved in vlsi (vhdl/verilog with FPGA ) implementation of digital delay locked loop.Generally digital DLL consists of following components. I.Phase detector II.Digitally controlled delay unit III. Digital controller I am trying to use a Up/Down counter for the digit
Hi , I need the method and technique required for simulation of digital delay locked loop using the C/C++ language . If any one has done coding using the C/C++ language post it in the forum. Can i get any information regarding the simulation of DLL using C in any website or link.
AS I AM DOING A PROJECT IN DIGITAL delay locked LOOP ,I WANT TO STUDY THE delay locked LOOP STRUCTURE,TYPES AND DIFFERENT METHODLOGIES USED FOR DESIGNING THE CIRCUIT PLEASE SEND ME SOME PAPERS OR THESIS ,WHICH EXPLAINS THE DLL FROM THE SCRATCH TO THE END FOR JITTER REDUCTION AND MINIMIZATION THANKS IN ADVANCE
Could any one help me in the designing of digital controlled delay unit circuit for my delay locked loop Circuit As i am not able to implement uisng a Verilog Simulation tool ,FPGA ADVANTAGE PRO. Send me any ALL DIGITAL delay locked LOOP CIRCUIT ,as i am not able to find any complete circuit in the (...)
Hai, I need the vhdl/verilog codes for the all digital delay locked loop ,with any simple architecture which can work on few Mhz of frequency or the website ,materials(pdf). 20 points for a good code
Hai, can anyone send me digital delay locked loop vhdl/verilog codes with any architecture of DLL. I want it urgently . thanks in advance .
Hai, I am working on digital delay locked loop using verilog HDL but , i am not able to get any reference paper in which the entire simulation is done using verilog HDL. So that i can fuse it in an FPGA kit or performe the ASIC design . Some papers they dont tell in which tool they simualted the design . As some circuits are given as dig
Low-jitter clock multiplication: a comparison between PLLs and DLLs van de Beek, R.C.H. Klumperink, E.A.M. Vaucher, C.S. Nauta, B. Univ. of Twente, Enchede, Netherlands This paper appears in: Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Tr


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