Search Engine **www.edaboard.com**

## Delta Sigma Adc |

Are you looking for?:

sigma delta adc , adc sigma delta , sigma and delta and adc , how design delta sigma adc

sigma delta adc , adc sigma delta , sigma and delta and adc , how design delta sigma adc

592 Threads found on edaboard.com: **Delta Sigma Adc**

Hi,
Can anybody please suggest me how to implement this block diagram using Capacitors? I tried but messed up because when I try with one gain coefficient, it changes the already calculated capacitance for other branch.
136191
Thanks

Hobby Circuits and Small Projects Problems :: 02-16-2017 21:45 :: ashrafsazid :: Replies: **5** :: Views: **388**

Hi Altruists,
I need to design an incremental **sigma** **delta** **adc** (OSR=500) where I need to implement a CoI Filter. From literature study i found that this CoI filter is actually same as CIC but without the comb part for CIC. I need to write a code in Verilog (or Verilog A) for CoI Filter. I dont have so much deep knowledge on CIC. I checked (...)

Analog Circuit Design :: 02-13-2017 21:08 :: ashrafsazid :: Replies: **0** :: Views: **644**

hi
I wanted to know that can a **sigma** **delta** **adc** will handle multiple inputs from different source by using a mux

Analog Circuit Design :: 02-06-2017 09:00 :: manissri :: Replies: **2** :: Views: **535**

Hi Folks,
I need to design a 1 bit DAC for **sigma** **delta** modulator. Can anybody please suggest me some architecture for dac design?
For incremental **delta** **sigma** the dac needs to provide three state ( two states from two quantizer levels and one state for input level). How is it possible with 1 bit DAC?

Analog Circuit Design :: 02-05-2017 03:47 :: ashrafsazid :: Replies: **1** :: Views: **520**

In addition, there are two flavor of **delta** **sigma** **adc**. Discrete time and continuous time.
Continuous time has inherent anti-aliasing.

Analog Circuit Design :: 01-05-2017 13:39 :: deba_fire :: Replies: **3** :: Views: **565**

The DS **adc**(**delta** **sigma** **adc**) output will be equal to the input*STF(signal transfer function) + quantization error*NTF(noise transfer function). At the output, the data needs to passed through a low pass filter to filter out the shaped noise. In most practical cases, the STF is almost one in the signal bandwidth. Thus, there (...)

Digital Signal Processing :: 11-05-2016 15:45 :: deba_fire :: Replies: **1** :: Views: **682**

Hi,
I need help to determine the op amp gain required to match certain **adc** specifications. I need to design a **delta** **sigma** 14 bit **adc** and need to find out required op-amp gain for the integrator design. Is there any certain formula to find out that

Analog Circuit Design :: 10-01-2016 09:30 :: ashrafsazid :: Replies: **0** :: Views: **503**

Hi,
You are desgning the is a clocked system, so you should know after how much clock cycles the output is valid.
(Just to be sure: you don't talk about **delta** **sigma** **adc**?)
Klaus

Analog Circuit Design :: 08-09-2016 06:26 :: KlausST :: Replies: **2** :: Views: **423**

Hi,
I need a book or reference that discusses the **adc**'s Calibration .... what is it ? and why is it done ? and how ? and does it differ from an **adc** type to another ?
Thxx

Power Electronics :: 07-20-2016 20:37 :: Ayman Essam :: Replies: **1** :: Views: **297**

I would like to measure the ENOB of a **sigma**-**delta** **adc** on Cadence Virtuoso.
what are the steps to be done ?
do i need MATLAB ?No, you don't need MATLAB at all.
Simply use Skill Language in Cadence dfII.
ENOB=(SQNR-1.76)/6.02
Excerption from My Skill CodeTstep = 1/fs
Tstart = round(5*(1/fIF)/Tste

Power Electronics :: 07-03-2016 09:51 :: pancho_hideboo :: Replies: **3** :: Views: **739**

Hello,
I've read around extensively about FFT setup for a **sigma** **delta** **adc** and I'm not sure if I'm not setting it up properly .
my current setup for a first order **sigma** **delta** **adc**
sampling frequency : 38.4 kHz (for the **adc** and FFT setup)
FFT bins : 65536
input (...)

Analog Circuit Design :: 06-28-2016 07:48 :: irascible :: Replies: **0** :: Views: **838**

Many people use SAR **adc**, some stick to **delta**-**sigma** and some like pipelined **adc** while designing signal conditioning circuit for SoC or for IoT application Chip. What is your view on this? Which one you will pick and why? There are hell lot of literatu

Analog Circuit Design :: 05-15-2016 10:29 :: Rahul Sharma :: Replies: **3** :: Views: **474**

Dear All,
Could you please tell me what's the relationship between OSR and ELD in continous-time **sigma**-**delta**
**adc**? And why lower OSR is more sensitive to ELD?
Thanks a lot!
best,
Ken

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 05-05-2016 06:11 :: ken_cn :: Replies: **8** :: Views: **617**

Attached circuit shows Feedback DAC of CT-DSM-**adc**(Continuous Time **delta** **sigma** **adc**).
What type of DAC do you think this DAC is, Current(Fig.4.5) or Resistive(Fig.4.3) ?
I think this DAC is current type same as Fig.4.5.
Here I have two questions.
What purpose do you think circuits inside red rectangular have ? (...)

Analog Circuit Design :: 04-21-2016 13:06 :: pancho_hideboo :: Replies: **1** :: Views: **572**

I am working on **sigma** **delta** modulators.
I came to know that the MIXMODEST presentation/document provides an excellent description of the factors related to the design of **sigma** **delta** modulators.
the link given below does not work.
Can anyone forward me the docu

Analog Circuit Design :: 03-08-2016 06:20 :: pankaj jha :: Replies: **0** :: Views: **345**

Why are anti-aliasing and low pass filters not always integrated into the data converters?
Hardly possible, in general. With the exception of oversampling **adc** (**sigma**-**delta** type) that mostly have a high order low-pass filter built in. They can be operated with only a simple low-pass filter removing input signal components above half

Digital Signal Processing :: 03-04-2016 15:55 :: FvM :: Replies: **1** :: Views: **845**

Hello,
First...sorry for my English and bad grammar. I'm not native speaker.
I need to measure dc voltage signal (or get average value from slow periodic signal to 100Hz - but it's not neccesary) with biggest resolution as possible. Dynamic range is 0.2-4.8V. Let' s say 500uV resolution is neccesary and anything better like down to 100uV reso

Analog Circuit Design :: 11-26-2015 22:31 :: Longin :: Replies: **2** :: Views: **766**

I am designing a 3rd order Continuous time **adc** , with 1 MHz Bandwidth ,32 OSR and 3 level Comparator.
I have a question regarding the coefficient values.
I used the equation:
coefficient * fs = 1/(R*C)
However, since the coefficient has 3 or 4 points precision (for instance: coeff = 0.0805 )
Assuming So the p

Analog Circuit Design :: 11-06-2015 07:58 :: pankaj jha :: Replies: **2** :: Views: **723**

I have been working in the design of a 3rd order **sigma** **delta** analog to digital converter. right now I am concerned with the implementation of the digital part, the digital filter & the decimation filter. Any help? as i can't find a resource that illustrates the link between the analog part of the **adc** & the digital one.

ASIC Design Methodologies and Tools (Digital) :: 09-02-2015 14:32 :: Shady Ahmed :: Replies: **2** :: Views: **775**

I am working on a 3rd order, 1 MHz **sigma** **delta** **adc** with the following Specs
3 level quantizer and OSR = 32.
I am facing a linearity problem that i don't know how to fix it.
The system achieved max SQNR = 69 dB at Vin Full Scale and Max Frequency (i.e: Fin = Fb)
The following figure shows the PSD:
1

Analog Circuit Design :: 11-06-2015 08:13 :: pankaj jha :: Replies: **1** :: Views: **649**

Hi Friends,
I am wondering how **sigma** **delta** **adc**'s work with a 1 bit Comparator. I went through some articles and I have a rough idea of its architecture. There's a 1 bit comparator and the input is sampled many more times than the Nyquist rate.
Suppose I have a 0 to 10V measuring **sigma** **delta** (...)

Analog Circuit Design :: 11-06-2015 07:19 :: pankaj jha :: Replies: **6** :: Views: **821**

Hello everybody! Recently I have designed a 2nd order Incremental **sigma**-**delta** **adc**. I have two main concerns about my design:
1 - The goal was achieving at least 14 bits, but unfortunately after realizing the FFT in order to obtain the outuput spectrum, the fundamental is attenuated by 20 dB. I don't know which reasons can

Analog Circuit Design :: 11-06-2015 07:10 :: pankaj jha :: Replies: **5** :: Views: **770**

hello all
I have two queries on **sigma** **delta** **adc**
1. While going through its material i found that while some show that the output of the modulator is series of 0s and 1s, some show it as series of 1 and -1.
Which is correct
2. The output of decimator is shown as a discrete signal and not a digital (0 and 1). but the (...)

Analog Circuit Design :: 10-19-2015 08:15 :: sona_ :: Replies: **20** :: Views: **2491**

hi
i am working on **sigma** **delta** **adc**
one query :
how to find hte input range for **sigma** **delta** modulator for which the **adc** can work properly
please suggest
Manissri

Analog Circuit Design :: 09-23-2015 18:03 :: manissri :: Replies: **6** :: Views: **670**

Reference previous thread:
hi wowee
For weigh scale application I recomment you AD7730.
I did not counter the problem hat you have ,(my application is unipolar)
Totally,I fear to use analog devices **sigma** **delta** for my future products ,I think It is better to te

Professional Hardware and Electronics Design :: 09-02-2015 14:03 :: A1365rash :: Replies: **0** :: Views: **800**

hi my friends
I want to design an **delta** **sigma** **adc**, and i need to amount of minimum jitter in my Calculation.
what is the amount of jitter in TSMC 0.13 ?

Analog Circuit Design :: 07-29-2015 12:19 :: rey1991 :: Replies: **1** :: Views: **441**

I am designing a 3rd order **sigma** **delta** **adc** with OSR = 32 , Fsampling = 64 MHz, with 1.5 bit comparator. The design is in 0.13um technology.
The target peak SNR from the system design (i used Schreier toolbox) was 76 dB.
After generating the system coefficients, i verified it on Cadence using ideal components.
The system peak SNR was (...)

Analog Circuit Design :: 07-28-2015 07:54 :: Shady Ahmed :: Replies: **7** :: Views: **1922**

Is there any way to measure the SNR of signal used in Verilog-AMS models (for ex. **sigma** **delta** **adc**) on cadence environment?

Analog Circuit Design :: 06-26-2015 09:10 :: simulbarua :: Replies: **0** :: Views: **416**

The op amp with the ideal vcvs in the CMFB circuit still affects the **sigma** **delta** **adc** performance greatly!!
Could you show how you connected the vcvs-CMFB to your opAmp?

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 07-07-2015 12:24 :: erikl :: Replies: **18** :: Views: **1211**

Okay, here's the deal:
1) Learn about coherent sampling. You should use sampling frequencies and input frequencies that are coherent. Meaning that the input frequency should always be exactly on a bin that is computed by FFT to get the most accurate performance measurement. There's more to it but this is an intuitive explanation. If you get this p

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 06-10-2015 21:09 :: kemiyun :: Replies: **5** :: Views: **818**

1. The discrete Fs numbers are industry standard audio sampling rates. The converter can work at different rates, the essential point is the master clock to fs ratio.
2. The internal fs divider is switched according to the actual BCLK rate.
3. A **sigma**-**delta** converter is continuously sampling the input signal and generating the output data str

Embedded Linux and Real-Time Operating Systems (RTOS) :: 06-08-2015 12:55 :: FvM :: Replies: **2** :: Views: **1011**

A strange phenomenon appears when I was testing my **sigma** **delta** **adc**(MASH 2-1 structure, with single bit quantizer at both stages) . The small signal (10mVpeak-peak, 2.9Vpeak-peak as FS value) 1kHz sine wave is used as stimulus to the data converter and 2nd, 3rd, 4th, 5th harmonic distortions can be observed in Audio Precision measurement's (...)

Analog Circuit Design :: 05-18-2015 06:26 :: threekingtiger :: Replies: **3** :: Views: **591**

Hi,
We are trying to interface Shunt 75mV at 500 Amps AD/DC load to PIC24FJ128GC006 microcontroller,
Can we connect shunt directly to Micro controller CH0+ and CH0- pins or do we need any circuit in between. PIC24FJxxxGCyyy series micro controllers have inbuilt 16 bit **sigma** **delta** **adc**. So considering the resolution we think that 0.1 (...)

Microcontrollers :: 05-16-2015 09:47 :: gravi :: Replies: **25** :: Views: **1981**

Hello
I have some queries about **delta**-**sigma** DAC.
1) basically, it is same with **delta**-**sigma** **adc**, but it consists of digital blocks, such as accumulators. However, how to synchronize the clock with PCM signals from a DSP? Does it need serial communication circuits?
2) I tried to find Simulink (...)

Analog Circuit Design :: 04-04-2015 05:38 :: CHL :: Replies: **0** :: Views: **1045**

Hi All,
This is my first **adc** and verifying it is proving to be more difficult then actually designing the subblock.
I have been able to do a transient simulation in cadence (spectre) and have successfully imported the data into matlab.
This is where I'm encountering most of my headache.
1) I'm new at matlab
2)All of the fft examples I've

Analog Circuit Design :: 04-03-2015 18:41 :: Souljah44 :: Replies: **0** :: Views: **1085**

Hello CHL,
While **delta**-**sigma** or **sigma**-**delta** is in essence an averaging process the oversampling is not the only thing responsible for the ENOB.
For example only OSR improves the number ob bits from n to ENOB=n+0.5*log2(OSR). Now this means that for a 5-bit gaing OSR of 1024 is needed.
Now if you look at (...)

Analog Circuit Design :: 03-12-2015 09:47 :: helpmejerry :: Replies: **3** :: Views: **961**

Hi,
Is there any way to simulate the frequency response of digital filters using Cadence Virtuoso? (like AC or PAC analyses done for analog filters)
Actually, I am trying to realize a **delta**-**sigma** **adc** in Cadence, which consists of a (digital) decimation filter.
Can anybody give any idea how to simulate the performanc

ASIC Design Methodologies and Tools (Digital) :: 03-12-2015 14:11 :: jdp721 :: Replies: **0** :: Views: **870**

Hi,
I need help regarding 2's complement coding scheme to be used on the **delta** **sigma** modulator output before feeding to the decimator. Following scheme is suggested in some Lousiana State Univ thesis:
convert 1b'0 to -1 = 1111...11, and 1'b1 to +1

PLD, SPLD, GAL, CPLD, FPGA Design :: 03-10-2015 15:24 :: jdp721 :: Replies: **2** :: Views: **620**

Hi.....
I have designed and fabricated a 16Bit second order, single bit **sigma** **delta** modulator based **adc**. During testing of **adc**, when we apply zero volt at the input of **adc**, sometimes it works fine and sometimes it gives a fixed code of 00FF (hex). Otherwise the **adc** is working fine. Are (...)

ASIC Design Methodologies and Tools (Digital) :: 02-11-2015 15:56 :: mohd asim :: Replies: **0** :: Views: **419**

One of these references may help.

Analog Circuit Design :: 01-30-2015 17:18 :: crutschow :: Replies: **3** :: Views: **502**

Currently, I have designed a second-order **sigma**-**delta** **adc** (fin = 20kHz, fs = 5MHz). In this **adc**, a 2-bit flash **adc** was adopted as a quantizer, and a 2-bit DAC was inserted into the feedback signal path. The attached file is the system architecture and the simulated results.
113250
According to the (...)

Analog Circuit Design :: 01-17-2015 04:04 :: davison7 :: Replies: **0** :: Views: **671**

Paper or Thesis information:
T. Thantipwan and N. Wongkomet. "A power-optimized 16-bit 1MS/s nyquist-rate **sigma**-**delta** analog-to-digital converter", Chulalongkorn University. To be published.
thank a lot !
- - - Updated - - -
be badly in need of this paper!!!

Analog Circuit Design :: 01-04-2015 07:31 :: wonbef :: Replies: **1** :: Views: **684**

hi
i am designing a **sigma** **delta** **adc**. \can i keep a osr which is not in powers of 2 eg. 50. will i be able to design a decimation/\cic filter for such a decimation factor?? or is it necesaary to keep \osr in powers of 2???

Analog Circuit Design :: 12-01-2014 12:25 :: pankaj jha :: Replies: **0** :: Views: **423**

Dear all,
I am trying to design a single-bit first order **delta**-**sigma** **adc**. The architecture that I am using is the very simple single ended ΔΣ modulator. The modulator is supposed to work for audio band signals (20-20KHz). The clock signal that is used is a 2.56MHz pulse. Therefore OSR is 64.
Switches that i

Elementary Electronic Questions :: 11-25-2014 06:10 :: mmnavidi :: Replies: **0** :: Views: **536**

Hi guys. nowadays i'm learning **delta**-**sigma** **adc**.
i'm too confused because of one problem...
111414
ficture from understanding **delta**-**sigma** data converters by Richard Schreier
here's the image related to my Q
as you can see
there's single tone input at 2*10^-3 (normalized frequency) (...)

Analog Circuit Design :: 11-17-2014 07:21 :: Ray Ch :: Replies: **0** :: Views: **425**

Hi,
Is there any thumb rule to set the Quantization threshold for generating the bitstream while modeling a first order **sigma** **delta** **adc**?
I am trying to model a 16 bit SDM **adc** with a full scale input of of 1Vrms.
Thanks,
Ranand

Analog Circuit Design :: 11-12-2014 09:03 :: Ranand :: Replies: **0** :: Views: **428**

Hi,
I'm a bit unclear about a decimation filter used in oversampling data converters. Say in a **delta** **sigma** **adc** that has a sampling frequency of 64 MHz, input frequency of 1 MHZ, oversampling equal to (64MHz/(2*1) = 32), and a 1-bit internal **adc**, the resolution is supposed to be 20 bits. So there would be 64 samples at the (...)

Analog Circuit Design :: 10-21-2014 15:28 :: mordak :: Replies: **0** :: Views: **580**

Hi, folks,
I am writing an academic paper about micro-watt 1st order **sigma**-**delta** **adc**. The schematic is attached here. I need to know what is the ratio between analog components and digital components. I think that that in a mixed-signal circuit, compared to that of analog components, the digital components power consumption is much lower (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 10-16-2014 14:27 :: hyleeinhit :: Replies: **1** :: Views: **781**

Hi,
I was wondering if for **delta** **sigma** **adc**s it would be possible to use non-uniform sampling (under sampling) for frequencies higher than the maximum bandwidth of the **adc**. For example, assuming a **delta** **sigma** **adc** has certain resolution for an input frequency up to X Hz, (...)

Analog Circuit Design :: 10-16-2014 04:55 :: mordak :: Replies: **3** :: Views: **723**

Some of this depends on the "ASIC" target foundry flow. A
mostly-digital **sigma**-**delta** converter is popular (esp. in audio
ranges and lower) because almost any cheapo digital flow
can support it. Whereas others are needful of high quality
matching and linearity in resistors or capacitors, which may
not be available or well enough controlled / model

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-17-2014 21:10 :: dick_freebird :: Replies: **6** :: Views: **926**

Last searching phrases:

cst head | spice tutorial | temperature filter | set data check | stepper motor control program | arithmetic operations | array distance | pwm 555 | pll integration | transformer layout

cst head | spice tutorial | temperature filter | set data check | stepper motor control program | arithmetic operations | array distance | pwm 555 | pll integration | transformer layout