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Design A 4 1 Mux Using 2 1 Mux

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1000 Threads found on Design A 4 1 Mux Using 2 1 Mux
Sorry but really i cant realize what is the advantage of using mux to design those logic gate ? With respect to digital, again you have to use gates to build mux, and with respect to analog surely the number of transistor you are going to use to build a logic gate by (...)
how to design 2x1 mux using half adders
How to implement a 4:1 mux using just 2 4-input LUTs? Does each 4-input LUT independently use four inputs to select one of 16 design-time-configured "fuses"? So each LUT generates an independent function of four inputs? Under those conditions, the problem is solvable with the caveat that switching between (...)
In scan insertion, tool convert the design flip-flop in Scan flip-flop. Already we have bunch of flops in design. So no need to insert extra flops. Is it same for mux also if i am using mux-D flops scan cells. Have we enough amount of mux (...)
Hi friends I want implement a 4:1 mux using 8:1 mux. I have a solution. whether it is correct? I attached the Logic, see to it and reply. Thanks & Regards....
Hi, I am a new member of this site. I start with a simple question - How we can implement a 5:1 mux using any number of 4:1 mux?What about unused ports?
hi , anyone help me to implement mux using XOR gate? Note: its not xor using mux thanks in advance
Any one please give me circuit digram of "8:1 mux using Transmission gates"
Hi all, Below is the verilog code for posedge and negedge flipflops using mux. I have also attached the pictorial representation of the circuit. Verilog code : module mux_ff( clk, in, out_pos, out_neg ); input clk; input in; output out_pos; output (...)
hello all, i designed 2x1 mux using transmission gate in 65nm node. i am getting 40ps delay from mux. any one can suggest me method to reduce delay. i knw the delay depends upon the o/p and i/p load. i want to knw any one have ans for the load optimization also. i want to thank you in (...)
Hi, I want to draw a module diagram for 32 bit RZ encoder using mux or state machine in ARINC 429 Transmitter block. Please help me to draw this. Thanks
Hi, what are the input and output pin description to rz encoder using mux in arinc 429 protocol. Pls reply to my question. Thanks
Can any one can send me right verilog code for designing 16 by 1 mux using 4 by1 mux in structural modellng?
Hi all! what is the difference between PAM using mux/demux for 1 link/ 2 link/ 3link. We had performed all three in lab. But I don't understand the significance of doing it in three ways. Which one is better?
Hi, I want to design a FIR Filter bank using c and implement it in tms320c6711, how do i approach this project. i already have a fir filter but how do i suppose to approach the fir filter bank for freqencies to be used later for speech recognition? I am confused about different filter bank approach. Unifrom, nonuniform and so on.. Also how do i
Hi all, There is another interview problem: design a 1-bit fulladder using a decoder and 2 "or" gates? Any suggestions will be appreciated! Best regards, Davy
usually in power amplifier design u need to use LSSP , which is based on HB simulation , small signal S parameters are not ususally used in PA also it will be not vaild at all if u design a class C PA so use HB , or LSSP khouly
Hi I have one doubt.we are developing a big core in our company.A small IP core is brought from other company.I have to test the dsign in to integrate that ipcore in ours design in altera FPGA kit using quartus-II software. Thanking you
How to design 3D engine in C++ using OpenGL in multiplatform? Please suggest articles regarding developing Framework in C++.
Hi if you want to work with DAS2005 for antenna design, you should work with Layout section. in there you should work with momentum in mainbar for all of your simulation process(create substrate, port selection, mesh setup, optimization and simulation). I hope it be useful
how to design a pulse width modulator using vhdl?
Hi , I want to know how can we design a frequency doubler without using PLL? It would be great help. Regards Tauqueer
can anybody tell how to design a+(b+c)'+c using cmos ....2nd term b+c)' is nor gate but how to add a+c with nor that i don`t understand
Does anybody know anything about the optimization design of analog integrated circuits using genetic algorithm?? How to use Hspice and matlab ensemble??
how to design a 3x3 hybrid combiner using coupler or another?
Take a look on existing free designs: I made a project with LEON:Improving The LEON2-XST PCI Interface, I2C master connected and tested with LEON Processor.... CPU 8051 translation from VHDL to verilog. I used 8051 from ..... The VHDL code has been translated to verilog. The cpu is also slightly
hi frnds i want to design a combline bandpass filter using tapped line input..... the problem coming here is the location of tappedline on the first resonator...from my specs my external quality factor is around 182... by parameter extraction for determination of external quality factor. ..... i changed the tapping position onto the first resonator
Currently i doing project based on design a bluetooth communication system using simulink . If any one know how to do it Pls give me some links regarding this project as soon as possiable... Thankx....
Pedroni's one is a good book and i consider it from time to time. It is not suitable for an experienced developer though. I personally prefer "HDL Chip design" by Douglas J. Smith, although it is quite old. There a couple of newer books that are interesting, too...
How can I design a gray code counter using Verilog without using a binary-gray converter?
Hello Everyone, I need help to design a dual bandpass filter using mainfold principle (using quarter wavelength). Please please help me...
can somebody help me how to design a cross dipole antenna using cst software?i have try the R.Cahill journal (understanding measuring circular polarization) prototype but i dont understand it,,
I need to design Voltage to frequency converter using LM555 IC. Pin5 Control Volatge can be used for to achieve this function as per thair datashets. But I donot have formula defining relationship between Control Voltage Input(Input DC Level) and Output frequency. Please help. Thanks.
hi any one who know about how to design the digital pid controller using counter method pls give path how to do that.
hi VHDL Lover , i want to design the sound recognisation system using vhdl , can anybody suggest how to start with it . i knoe the basic vhdl coding thanks kalpana
Hi, Can anyone provide matlab/c source code for design of rectangular microstrip antenna using cavity model? thanks bob
guys i need help urgently plz can anybody tell me how to design a shunt voltage regulator using pd and pid controll with variable reference input.
it is very very simple in designing circular patch in ie3d. you need the dielectric constant, its height, and i think you are new to antenna so you should study "balanis" 1st learn basic things and after you will definately get help here on edaboard. i can easily help you in about IE3D because i have good command on it. regards
Hey all could someone teach me how to design a single stub tuner using awr design environment. I need a step by step example as i am new to this software and this rf and microwave analysis subject, thx Regards Johnson
Hi i want to know how to design a printed dipole antenna using hfss 13 . It doesn't matter the parameters of the antenna .I just want an explanation of (how) or an explained example any thing that will teach me how to design it on this program . Thank you
Can anybody help to put light on how to design a battery charger device using pressure generated through motion
I'm Looking for design coax to rectangular waveguide using T bar, including method and equation. Pls help
Hi everyone, Can you help me to design a band pass filter using ADS and microstrip technology. The parameters of the band pass filter are: 1. Center frequency: 1.575GHz 2. BW=50MHz and the following is parameters of the substrate: 1. εr=4.6 (Fr-4) 2. H=1.59 mm 3. T=0.035 mm 4. Tand=0.02 5. Match Impedance = 50 Ohm In addition,
hey friends; I have to code a routing logic using train algorithm, in vhdl. Details regarding the routing logic: The 2-D mesh structure is span in form of tree, as shown in the figure99076 The top is the root and addressed as 000, the branches below it are given address 100 and 200 respectively. and all the node
actually this is not my own question mux contain ,. gates anybody can design.gates by xor we are not able to build gate by using xor Main aspect is to design 'or' using xor.. tis was the question asked by TTM(time to market) Tata elxsi..and sirs from cdac can any body .. (...)
can any one design D flip flop and T flip flop using 2:1 mux
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Can anyone tell me how to design a XOR gate using 2:1 mux and an inverter. I have tried all ways and couldnt find a solution. Thx radhika
u can design xor by giving the select line of mux as B input of xor and input at '0' pin of mux as A and input at '1' as Abar. Then the complete design is xor using 2:1 mux
Hi guys , I am designing a mux, i want the select line to be set to 1 on every rising edge and 0 on every falling edge, that way the mux is changing twice every clock cycle. I seem to be having problems getting this to work, any one have any simple code that will do what i require. thanks stuart