139 Threads found on edaboard.com: Design A 4 1 Mux Using 2 1 Mux
it's hard to do,I think the important problem is the vendor's technology,not the design itself
ASIC Design Methodologies and Tools (Digital) :: 04.11.2007 02:55 :: straw :: Replies: 4 :: Views: 689
I just try to implement my design by tri-state. If all mux can be implemented by LUTs and LUTs can play better performance than tri-state, why does Xilinx provide internal tri-state gates?
Other Design :: 26.07.2002 10:01 :: Joyee :: Replies: 7 :: Views: 1739
Timing and testing in tri-state bus implementation is a problem.
The designers don't take more time to trim timing problem by using mux-based bus.
In SOC design, all most designs choose mux-based bus, because IP integration is easier.
Another benefit of (...)
Microcontrollers :: 23.01.2003 02:14 :: jiang :: Replies: 28 :: Views: 6129
Can anyone tell me how to design a XOR gate using 2:1 mux and an inverter. I have tried all ways and couldnt find a solution.
ASIC Design Methodologies and Tools (Digital) :: 14.07.2005 16:17 :: Radhika iyer :: Replies: 2 :: Views: 2446
hi i want to design barrel shifter using combinational logic
can any body help me 4 that
thanks in advance
PLD, SPLD, GAL, CPLD, FPGA Design :: 14.08.2006 03:18 :: dipen_dudhat :: Replies: 3 :: Views: 2454
u can design xor by giving the select line of mux as B input of xor and input at '0' pin of mux as A and input at '1' as Abar. Then the complete design is xor using 2:1 mux
PLD, SPLD, GAL, CPLD, FPGA Design :: 16.12.2006 13:06 :: haneet :: Replies: 8 :: Views: 1975
yes tristates cell delay is big, but I think it just used in IO port, so it don't take big delay for Ur design.
mux is also, has big cell delay. perhaps U can use CTSmux
ASIC Design Methodologies and Tools (Digital) :: 06.07.2007 10:23 :: FLEXcertifydll :: Replies: 3 :: Views: 671
actually this is not my own question
mux contain ,. gates
anybody can design.gates by xor
we are not able to build gate by using xor
Main aspect is to design 'or' using xor..
tis was the question asked by TTM(time to market)
Tata elxsi..and sirs from cdac
can any body .. (...)
ASIC Design Methodologies and Tools (Digital) :: 01.08.2007 01:06 :: naaj_ila :: Replies: 3 :: Views: 2767
What algo or codes does a Vignene Encryption do? How many bits it used? and can you show your old design? May be we could help
(I'm very sorry for I don't know the algo of such encryption, perhaps just show some algo)
Hobby Circuits and Small Projects Problems :: 03.08.2007 00:10 :: the_risk_master :: Replies: 2 :: Views: 902
can any one design D flip flop and T flip flop using 2:1 mux
ASIC Design Methodologies and Tools (Digital) :: 31.08.2007 03:30 :: anantha_09 :: Replies: 2 :: Views: 4039
Hi guys ,
I am designing a mux, i want the select line to be set to 1 on every rising edge and 0 on every falling edge, that way the mux is changing twice every clock cycle. I seem to be having problems getting this to work, any one have any simple code that will do what i require.
PLD, SPLD, GAL, CPLD, FPGA Design :: 29.10.2007 06:51 :: suddy72 :: Replies: 12 :: Views: 1044
how to design of 8:1 mux with 2GHz frequency.
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.11.2007 12:00 :: sachinmaheshwari :: Replies: 3 :: Views: 1000
hye all..can anyone help me about how to design the mimo-cdma system using simulink communication blockset..
i have done the system by using serial to parallel block at transmitter and parallel to serial block at receiver. i use the mux and demux in both block, but i have (...)
Software Problems, Hints and Reviews :: 15.04.2008 01:25 :: ierakl :: Replies: 1 :: Views: 858
design a system using a 4:1mux to identify whether a 4-bit number is prime
ASIC Design Methodologies and Tools (Digital) :: 10.05.2008 12:23 :: phoenix_pavan :: Replies: 4 :: Views: 1273
Sorry but really i cant realize what is the advantage of using mux to design those logic gate ? With respect to digital, again you have to use gates to build mux, and with respect to analog surely the number of transistor you are going to use to build a logic gate by (...)
ASIC Design Methodologies and Tools (Digital) :: 15.05.2008 03:08 :: atena :: Replies: 17 :: Views: 25279
I M using BUS IM MY design.
THERE IS ERROR " ONLY INPUT PIN ON . CH52"
WHERE CH52 IS ONE OF THE SIGNAL IN THE BUS.
WHERE CH52 IS SIGNAL GOIMG FROM BUFFER TO mux.
PCB Routing Schematic Layout software and Simulation :: 18.11.2008 04:53 :: zia.roghani :: Replies: 1 :: Views: 1327
Please suggest possible ways for
Possible ways of designing Flip Flop from Latch and mux
along with waveforms
ASIC Design Methodologies and Tools (Digital) :: 20.06.2009 05:37 :: spartanthewarrior :: Replies: 2 :: Views: 1380
I am trying to build a gas sensor array ... i do not want to connect them all seperately to the microcontroller as i need many port pins for further application circuits... can u plz help me in designing a data acq circuit for the sensor array... am planning to use MQ series gas sensors...
Microcontrollers :: 06.04.2010 09:46 :: hgfedcba :: Replies: 5 :: Views: 1620
how to design 2x1 mux using half adders
ASIC Design Methodologies and Tools (Digital) :: 06.05.2010 09:22 :: tchintap :: Replies: 1 :: Views: 3089
How to implement a 4:1 mux using just 2 4-input LUTs?
Does each 4-input LUT independently use four inputs to select one of 16 design-time-configured "fuses"? So each LUT generates an independent function of four inputs?
Under those conditions, the problem is solvable with the caveat that switching between (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.07.2010 11:43 :: supercat :: Replies: 5 :: Views: 4491
Well I have to design a base index generator. When I say base index it is nothing but indexing the output of a binary counter.
Well let me explain it clearly.
We have a 13-bit binary counter who outputs are quoting to 4096 locations on a RAM and we have 13 such stages which is like the counter should count to 4K for 13 stages. Now we
Digital Signal Processing :: 20.09.2010 12:06 :: DEEPTHIPENDYALA :: Replies: 0 :: Views: 1063
I would like to find or build an analog signal multiplexer to serve as the front-end to an ultra-low bias current op-amp, for example the LMP7721. This amp has 3fA typical, 20fA max input bias current. This is the lowest amp I've found, but there are several other amps that are within 10X higher.
However, I am having a really hard tim
Analog Circuit Design :: 03.10.2010 17:20 :: snowblind :: Replies: 0 :: Views: 1012
the following is the mux design
din_0 , // mux first input
din_1 , // mux Second input
sel , // Select input
mux_out , // (...)
ASIC Design Methodologies and Tools (Digital) :: 27.01.2011 09:28 :: karan hans :: Replies: 5 :: Views: 2175
As they said above,
It is used for the DFT (design for test) to test the controllability and observability.
In DFT insertion, All FFS are converted with the muxed FF. so while at DFT mode, normal functionality of the design is disabled and vice versa.
Scan chain means, The FF's are connected in FIFO way and will be (...)
ASIC Design Methodologies and Tools (Digital) :: 12.04.2011 07:53 :: lohi21 :: Replies: 3 :: Views: 681
Hello! I am designing a clock, and i have some questions before moving to the layout part
1--i want to be able to drive a big (12p) load. My most "correct" node to take the output is the comparator output, but i don't want to load it so heavily. So what do you think would load my comparator output as little as possible and be able to drive such
Analog IC Design and Layout :: 08.05.2011 09:33 :: geozog86 :: Replies: 1 :: Views: 552
Check these links:
Electronic Elementary Questions :: 05.03.2012 02:39 :: yadavvlsi :: Replies: 2 :: Views: 2233
in my case the clock signal is used for selecting data inputs...
So is it necessary to fix the clock gating violations?
The question can't be answered without considering the purpose of the mux output signal. Instead of raising general questions, you should analyze your design's timing. in detail.
A mux (...)
ASIC Design Methodologies and Tools (Digital) :: 01.07.2012 04:50 :: FvM :: Replies: 14 :: Views: 1024
i want the procedure for designing the different logic gate, combinational circuits and sequential circuits using only muxes.
Electronic Elementary Questions :: 08.09.2012 05:48 :: harish reddy :: Replies: 3 :: Views: 356
its pretty easy. Read chapter 4 of morris mano's book "Digital design"
ASIC Design Methodologies and Tools (Digital) :: 18.12.2012 07:26 :: tariq786 :: Replies: 3 :: Views: 851
Can any one explain me how to solve this Quations
1) design a 4x4 multiplier using onlly one adder
2) design 17x1 mux using only 4x1 mux
3) design 8x3 encoder by using 4x2 encdoer
4) design 8x3 encoder (...)
ASIC Design Methodologies and Tools (Digital) :: 20.03.2013 04:20 :: kish12334 :: Replies: 0 :: Views: 289
While passing time here I came across an interesting article in QEX for those interested in SDR. Especially look at the sampling method using a 150Mhz video at the last two articles: A SDR for the masses. Seems that the article follows on, but there is no link to that yet...mayb
RF, Microwave, Antennas and Optics :: 03.01.2003 02:14 :: twinsen :: Replies: 1 :: Views: 1885
pls set all the necessary constraint on case2 & case3
so that we can afford to compare in the same condition.
at case3 pls set the clock500MHz constraint after mux.
This is a interesting issue.
wait to get your response
one thing I am curious's that in what process or design will make 500MHz such
high freq clk without any timing (...)
ASIC Design Methodologies and Tools (Digital) :: 25.06.2004 03:16 :: roger :: Replies: 9 :: Views: 1889
In the AMBA specs says
"using tri-state implementation to reduce area"
can anyone justify how exactly are we optimising on area when we use a tristate design.
ASIC Design Methodologies and Tools (Digital) :: 08.09.2004 05:15 :: gold_kiss :: Replies: 4 :: Views: 837
You need not to add mux in your design. You can use BIST to contain the Memory in RTL codes and synthesis the design. Then during DFT, you use ""set_scan_element false Path/Memory", the DFT tool automaticlly shortcutting the memory and treat it as a blackbox. This is one kind of method that can solve the (...)
ASIC Design Methodologies and Tools (Digital) :: 01.11.2004 00:23 :: horzonbluz :: Replies: 5 :: Views: 1486
I tried to do this in the past but found out as you have that even though the cells in tsmc library can switch at speed close to 650mhz but they have terrible jitter at speeds above 300mhz. I ended up using cadence tool to design the cells mostly uning transmission gates. if you look into tsmc cells, for example a 2-1 mux (...)
Analog IC Design and Layout :: 19.12.2004 19:42 :: rakko :: Replies: 4 :: Views: 1599
Ok it seems that your design is compose of subcomponents like counter, mux,.... (Structural)
You can use direct or component instantiations to connect these subcomponents to form final model (top design)
In both cases you use "port map" commands to connect the subcomponents together.
Search for "component (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.12.2004 08:47 :: SphinX :: Replies: 3 :: Views: 635
You can build any logic using 2x1 mux. The only reason why we don't use that it will be not optimal design.
This is generally true because you can build an entire look-up table using them. But why the enthusiasm on multiplexers?
Electronic Elementary Questions :: 31.01.2005 05:26 :: checkmate :: Replies: 11 :: Views: 10599
i will design one bidirection 1-8 multiplexer, i did not sucessful,i used the method
module (Dir, Sel, Row, Col);
who can help me ? how to design the bidirection module?
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.09.2005 00:02 :: ZFDok :: Replies: 5 :: Views: 778
Any Boolean function can be realized using muxes. Draw truth table of the function. Connect inputs to control signals of mux, then according to truth table tie the proper input to either Vdd or Gnd.
To simplify the circuit you can move one of controls to input section. For example of half-adder see (...)
ASIC Design Methodologies and Tools (Digital) :: 22.09.2005 01:40 :: vardan :: Replies: 10 :: Views: 24881
Mentor Mbistarchitecture is powerful tools to give memory bist logic in RTL format. It is readable.
You can design memory BIST circuit by a LFSR and PREG, It is two FSM. You can see any DFT book.
And you can refer synopsys DW_rambist about the memory bist arch.
For test algorithm and fault model, please search in IEEE or google. There are l
ASIC Design Methodologies and Tools (Digital) :: 14.02.2006 02:52 :: zhustudio :: Replies: 5 :: Views: 3795
Hey, I'm a 3rd year student of electronics and I need help to design a circuit that receives a sinal V0 with respect to the ground and outputs:
1) V0 in pin A and 0 (zero) in pin B, if V0>=0;
2) 0 (zero) in pin A and V0 in pin B, if V0<0;
Any ideas how to implement this circuit?
Electronic Elementary Questions :: 18.03.2006 12:12 :: ashade :: Replies: 3 :: Views: 889
If you know that a 2:1 mux can be used as a universal gate and also if you know how to design two's complement circuit, then there should not be any problem.
Now you have sufficient hint.You try it of your own.
PLD, SPLD, GAL, CPLD, FPGA Design :: 15.11.2006 04:42 :: xstal :: Replies: 10 :: Views: 1495
The exact problem specification still isn't clear. As already mentioned, the normal way is to define the counter operation in a hardware description language of your choice and let the synthesis tool implement it. You can inspect the gate level netlist to check how it fit's into LUTs and registers.
I assume, that you have been given a homework p
PLD, SPLD, GAL, CPLD, FPGA Design :: 04.08.2012 05:17 :: FvM :: Replies: 14 :: Views: 1594
I am now designing a divided-by-2.5 prescaler using phase-selecting technique. So first a divided-by-2 prescaler is designed with CML circuits and then the four quadrature signals are selected by a mux to the output. The question is how to design the control logic of the (...)
RF, Microwave, Antennas and Optics :: 14.04.2007 09:16 :: zhangjavier :: Replies: 1 :: Views: 516
Hi,basically I'm a analog and sensor guy,but I need do some simple controlling timing for my sensor array(image pixel array with expsouring time,readout,CDS),how can I get familiar with digital design efficiently?Now I'm read the Rabeay's book.I'm not majored in EECS although I had study digital circuit at undergraduate,but you can suppose I forget
ASIC Design Methodologies and Tools (Digital) :: 01.08.2007 14:58 :: leohart :: Replies: 3 :: Views: 991
for example, you have a clock mux , one input is normal clock , another is test clock, the two clocks work in diff period. the slow test clock may have a hold violation , the normal clock may have a setup violation. you can use set_case_analysis to analysis the timing of the design.
ASIC Design Methodologies and Tools (Digital) :: 28.09.2007 21:13 :: funzero :: Replies: 2 :: Views: 1273
Digital design by John F Wakerly is a good book.
Digital design by Morris Mano is good for beginers.
ASIC Design Methodologies and Tools (Digital) :: 28.09.2007 02:18 :: vlsi_freak :: Replies: 8 :: Views: 1060
Go through the Douglus Perry. In that book number of ways are given for writting the test bench.
Writing the testbench for fulladder and mux are as simple as writing their design.
Try first and even then you don't get, ask
ASIC Design Methodologies and Tools (Digital) :: 14.11.2007 22:48 :: gck :: Replies: 7 :: Views: 2576
I assume you are referring to a Xilinx FPGA. I'm not clear exactly what you are building, but if you really need to switch between two clocks without glitches, try the BUFGmux (if your FPGA provides it) instead of an ordinary mux such as muxF7.
If possible, try to design (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.12.2007 02:13 :: echo47 :: Replies: 3 :: Views: 1312
If inverted output of D flip-flop is connected to its input how the flip-flop behaves?
design a circuit to divide input frequency by 2?
design a divide by two counter using D-Latch.
design a divide-by-3 sequential circuit with 50% duty cycle.
What are the different types of adder implementation?
Draw a (...)
ASIC Design Methodologies and Tools (Digital) :: 05.02.2008 08:49 :: master_picengineer :: Replies: 4 :: Views: 18725