1000 Threads found on edaboard.com: Design A 4 1 Mux Using 2 1 Mux
Sorry but really i cant realize what is the advantage of using mux to design those logic gate ? With respect to digital, again you have to use gates to build mux, and with respect to analog surely the number of transistor you are going to use to build a logic gate by (...)
ASIC Design Methodologies and Tools (Digital) :: 05-15-2008 03:08 :: atena :: Replies: 17 :: Views: 25411
how to design 2x1 mux using half adders
ASIC Design Methodologies and Tools (Digital) :: 05-06-2010 09:22 :: tchintap :: Replies: 1 :: Views: 3137
How to implement a 4:1 mux using just 2 4-input LUTs?
Does each 4-input LUT independently use four inputs to select one of 16 design-time-configured "fuses"? So each LUT generates an independent function of four inputs?
Under those conditions, the problem is solvable with the caveat that switching between (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-08-2010 11:43 :: supercat :: Replies: 5 :: Views: 4523
In scan insertion, tool convert the design flip-flop in Scan flip-flop. Already we have bunch of flops in design. So no need to insert extra flops. Is it same for mux also if i am using mux-D flops scan cells. Have we enough amount of mux (...)
ASIC Design Methodologies and Tools (Digital) :: 09-13-2013 02:02 :: deepen talati :: Replies: 0 :: Views: 231
I want implement a 4:1 mux using 8:1 mux. I have a solution. whether it is correct?
I attached the Logic, see to it and reply.
Thanks & Regards....
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-15-2006 05:57 :: research_vlsi :: Replies: 6 :: Views: 9699
I am a new member of this site. I start with a simple question -
How we can implement a 5:1 mux using any number of 4:1 mux?What about unused ports?
ASIC Design Methodologies and Tools (Digital) :: 04-21-2007 07:35 :: pkgupta_work :: Replies: 1 :: Views: 1793
anyone help me to implement mux using XOR gate?
its not xor using mux
thanks in advance
ASIC Design Methodologies and Tools (Digital) :: 08-20-2007 08:07 :: meetspraveen :: Replies: 2 :: Views: 3614
Any one please give me circuit digram of "8:1 mux using Transmission gates"
Electronic Elementary Questions :: 03-13-2008 01:16 :: rizwanspirit :: Replies: 4 :: Views: 4423
Below is the verilog code for posedge and negedge flipflops using mux.
I have also attached the pictorial representation of the circuit.
Verilog code :
ASIC Design Methodologies and Tools (Digital) :: 02-16-2010 11:15 :: Guru59 :: Replies: 1 :: Views: 2155
i designed 2x1 mux using transmission gate in 65nm node. i am getting 40ps delay from mux. any one can suggest me method to reduce delay. i knw the delay depends upon the o/p and i/p load. i want to knw any one have ans for the load optimization also.
i want to thank you in (...)
Analog IC Design and Layout :: 02-21-2011 01:24 :: girishnayak12 :: Replies: 1 :: Views: 909
I want to draw a module diagram for 32 bit RZ encoder using mux or state machine in ARINC 429 Transmitter block.
Please help me to draw this.
Electronic Elementary Questions :: 12-10-2011 10:06 :: tulsi :: Replies: 0 :: Views: 468
what are the input and output pin description to rz encoder using mux in arinc 429 protocol.
Pls reply to my question.
Electromagnetic Design and Simulation :: 12-11-2011 06:36 :: tulsi :: Replies: 0 :: Views: 441
Can any one can send me right verilog code for designing 16 by 1 mux using 4 by1 mux in structural modellng?
Electronic Elementary Questions :: 10-31-2012 22:30 :: YASWANTH_802 :: Replies: 0 :: Views: 548
what is the difference between PAM using mux/demux for 1 link/ 2 link/ 3link.
We had performed all three in lab. But I don't understand the significance of doing it in three ways.
Which one is better?
Digital communication :: 03-18-2013 08:40 :: Sur93 :: Replies: 0 :: Views: 199
Hi, I want to design a FIR Filter bank using c and implement it in tms320c6711, how do i approach this project. i already have a fir filter but how do i suppose to approach the fir filter bank for freqencies to be used later for speech recognition?
I am confused about different filter bank approach. Unifrom, nonuniform and so on.. Also how do i
Digital Signal Processing :: 11-11-2004 12:24 :: maged :: Replies: 0 :: Views: 916
There is another interview problem:
design a 1-bit fulladder using a decoder and 2 "or" gates?
Any suggestions will be appreciated!
ASIC Design Methodologies and Tools (Digital) :: 10-27-2005 23:36 :: davyzhu :: Replies: 1 :: Views: 1057
usually in power amplifier design u need to use LSSP , which is based on HB simulation , small signal S parameters are not ususally used in PA
also it will be not vaild at all if u design a class C PA
so use HB , or LSSP
RF, Microwave, Antennas and Optics :: 08-15-2006 05:24 :: khouly :: Replies: 3 :: Views: 881
First try out simulating the design. if u get test bench.
After that u connect the IP core to ur processor design and port into fpga.
Is the board available for the IP. the inputs and outputs.
then u connect it to some logic and see how u can drive inputs from external world and check the output.
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-14-2006 02:20 :: bansalr :: Replies: 1 :: Views: 431
How to design 3D engine in C++ using OpenGL in multiplatform?
Please suggest articles regarding developing Framework in C++.
PC Programming and Interfacing :: 11-29-2006 23:07 :: ranjit123 :: Replies: 0 :: Views: 682
Hi if you want to work with DAS2005 for antenna design, you should work with Layout section. in there you should work with momentum in mainbar for all of your simulation process(create substrate, port selection, mesh setup, optimization and simulation). I hope it be useful
Electromagnetic Design and Simulation :: 12-02-2006 06:44 :: ali110 :: Replies: 1 :: Views: 612
how to design a pulse width modulator using vhdl?
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-03-2007 15:29 :: engrbabarmansoor :: Replies: 1 :: Views: 1565
I want to know how can we design a frequency doubler without using PLL?
It would be great help.
Analog Circuit Design :: 10-09-2007 16:27 :: alam.tauqueer :: Replies: 8 :: Views: 2295
can anybody tell how to design a+(b+c)'+c using cmos
....2nd term b+c)' is nor gate but how to add a+c with nor that i don`t understand
Analog IC Design and Layout :: 11-07-2007 04:40 :: seemagoyal44 :: Replies: 3 :: Views: 806
Does anybody know anything about the optimization design of analog integrated circuits using genetic algorithm?? How to use Hspice and matlab ensemble??
Analog IC Design and Layout :: 01-28-2008 10:11 :: s_babayan :: Replies: 3 :: Views: 1059
how to design a 3x3 hybrid combiner using coupler or another?
Electromagnetic Design and Simulation :: 04-17-2008 09:30 :: gliet :: Replies: 7 :: Views: 2330
Take a look on existing free designs:
I made a project with LEON:Improving The LEON2-XST PCI Interface, I2C master connected and tested with LEON Processor....
CPU 8051 translation from VHDL to verilog. I used 8051 from ..... The VHDL code has been translated to verilog. The cpu is also slightly
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-09-2009 11:14 :: pini_1 :: Replies: 2 :: Views: 1675
hi frnds i want to design a combline bandpass filter using tapped line input..... the problem coming here is the location of tappedline on the first resonator...from my specs my external quality factor is around 182... by parameter extraction for determination of external quality factor. ..... i changed the tapping position onto the first resonator
Electromagnetic Design and Simulation :: 11-03-2009 01:16 :: sandeepsreeman :: Replies: 1 :: Views: 1403
Currently i doing project based on design a bluetooth communication system using simulink . If any one know how to do it Pls give me some links regarding this project as soon as possiable...
Digital communication :: 01-25-2010 08:02 :: prashan14 :: Replies: 3 :: Views: 2183
Pedroni's one is a good book and i consider it from time to time.
It is not suitable for an experienced developer though.
I personally prefer "HDL Chip design" by Douglas J. Smith, although it is quite old.
There a couple of newer books that are interesting, too...
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-23-2010 17:55 :: the_penetrator :: Replies: 2 :: Views: 2025
How can I design a gray code counter using Verilog without using a binary-gray converter?
ASIC Design Methodologies and Tools (Digital) :: 02-16-2010 05:00 :: vivek_p :: Replies: 0 :: Views: 1529
I need help to design a dual bandpass filter using mainfold principle (using quarter wavelength). Please please help me...
RF, Microwave, Antennas and Optics :: 05-17-2010 06:16 :: fadubhai :: Replies: 2 :: Views: 539
can somebody help me how to design a cross dipole antenna using cst software?i have try the R.Cahill journal (understanding measuring circular polarization) prototype but i dont understand it,,
RF, Microwave, Antennas and Optics :: 07-22-2010 09:08 :: good cp :: Replies: 2 :: Views: 1445
I need to design Voltage to frequency converter using LM555 IC. Pin5 Control Volatge can be used for to achieve this function as per thair datashets. But I donot have formula defining relationship between Control Voltage Input(Input DC Level) and Output frequency.
Please help. Thanks.
Hobby Circuits and Small Projects Problems :: 08-04-2010 02:41 :: info_req :: Replies: 0 :: Views: 1809
any one who know about how to design the digital pid controller using counter method pls give path how to do that.
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-18-2010 03:07 :: hareshcooleng :: Replies: 0 :: Views: 521
hi VHDL Lover ,
i want to design the sound recognisation system using vhdl , can anybody suggest how to start with it . i knoe the basic vhdl coding
Digital Signal Processing :: 10-05-2010 00:37 :: kalpanakundalwal :: Replies: 1 :: Views: 491
Can anyone provide matlab/c source code for design of rectangular microstrip antenna using cavity model?
Electromagnetic Design and Simulation :: 03-28-2011 09:14 :: dmf :: Replies: 1 :: Views: 2067
guys i need help urgently
plz can anybody tell me how to design a shunt voltage regulator using pd and pid controll with variable reference input.
Power Electronics :: 11-25-2011 00:14 :: hina184 :: Replies: 0 :: Views: 416
it is very very simple in designing circular patch in ie3d.
you need the dielectric constant, its height,
and i think you are new to antenna so you should study "balanis" 1st learn basic things and after you will definately get help here on edaboard.
i can easily help you in about IE3D because i have good command on it.
RF, Microwave, Antennas and Optics :: 03-27-2012 12:06 :: vishal_sonam :: Replies: 4 :: Views: 994
could someone teach me how to design a single stub tuner using awr design environment. I need a step by step example as i am new to this software and this rf and microwave analysis subject, thx
RF, Microwave, Antennas and Optics :: 04-21-2012 13:12 :: johnsonong :: Replies: 1 :: Views: 781
Hi i want to know how to design a printed dipole antenna using hfss 13 .
It doesn't matter the parameters of the antenna .I just want an explanation of (how) or an explained example
any thing that will teach me how to design it on this program .
Electromagnetic Design and Simulation :: 12-01-2012 07:11 :: lionmking :: Replies: 2 :: Views: 576
Can anybody help to put light on how to design a battery charger device using pressure generated through motion
Professional Hardware and Electronics Design :: 01-23-2013 09:46 :: Abbey80 :: Replies: 5 :: Views: 407
I'm Looking for design coax to rectangular waveguide using T bar, including method and equation.
here are dimensions on a 4-8 ghz tbar horn antenna. The coax is not shown in the sketch, but the center conductor comes down from the top waveguide wall to the exact middle of the crossbar.
RF, Microwave, Antennas and Optics :: 04-02-2013 16:23 :: biff44 :: Replies: 1 :: Views: 277
Can you help me to design a band pass filter using ADS and microstrip technology. The parameters of the band pass filter are:
1. Center frequency: 1.575GHz
and the following is parameters of the substrate:
1. εr=4.6 (Fr-4)
2. H=1.59 mm
3. T=0.035 mm
5. Match Impedance = 50 Ohm
RF, Microwave, Antennas and Optics :: 04-23-2013 15:08 :: khungbopro :: Replies: 1 :: Views: 664
I have to code a routing logic using train algorithm, in vhdl.
Details regarding the routing logic:
The 2-D mesh structure is span in form of tree, as shown in the figure99076
The top is the root and addressed as 000, the branches below it are given address 100 and 200 respectively. and all the node
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-27-2013 01:12 :: manasic :: Replies: 0 :: Views: 281
actually this is not my own question
mux contain ,. gates
anybody can design.gates by xor
we are not able to build gate by using xor
Main aspect is to design 'or' using xor..
tis was the question asked by TTM(time to market)
Tata elxsi..and sirs from cdac
can any body .. (...)
ASIC Design Methodologies and Tools (Digital) :: 08-01-2007 01:06 :: naaj_ila :: Replies: 3 :: Views: 2783
can any one design D flip flop and T flip flop using 2:1 mux
ASIC Design Methodologies and Tools (Digital) :: 08-31-2007 03:30 :: anantha_09 :: Replies: 2 :: Views: 4143
Check these links:
Electronic Elementary Questions :: 03-05-2012 02:39 :: yadavvlsi :: Replies: 2 :: Views: 2340
Can anyone tell me how to design a XOR gate using 2:1 mux and an inverter. I have tried all ways and couldnt find a solution.
ASIC Design Methodologies and Tools (Digital) :: 07-14-2005 16:17 :: Radhika iyer :: Replies: 2 :: Views: 2488
u can design xor by giving the select line of mux as B input of xor and input at '0' pin of mux as A and input at '1' as Abar. Then the complete design is xor using 2:1 mux
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-16-2006 13:06 :: haneet :: Replies: 8 :: Views: 1982
Hi guys ,
I am designing a mux, i want the select line to be set to 1 on every rising edge and 0 on every falling edge, that way the mux is changing twice every clock cycle. I seem to be having problems getting this to work, any one have any simple code that will do what i require.
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-29-2007 06:51 :: suddy72 :: Replies: 12 :: Views: 1053