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Hi, I am using vivado 2015.2.1 . I designed up-down counter. I am getting error. (mentioned below) Find my code below: module counter(reset,clk,uphdnl,count,sseg,an); input wire reset,clk, uphdnl,count; //output reg out0,out1; output reg sseg; output reg an; reg out0_temp,out1_temp; reg
Tricky question because if you use some conceptual design as shown it is not real design, then all you can use are block diagrams. Then you must dream up your own logic symbols using standard shapes and text. Not very good for detail oriented Engineers but perhaps ok for your purposes. For example the Johnson counter you have (...)
Hi, This is my first post on this forum, so bear with me! First some background: I'm currently studying Electrical and Electronic Engineering and I've been tasked by my company to design a prototype PCIe card for testing PCIe connection functionality on our products. This is part of my final project for the course, which has to be work-based
What is up with all the vague questions lately that require clarification? I think a sticky note is needed which can contain explanations regarding 1> How to ask question related to h/w design & its implementation, what things need to be included in the Qs for others to better and quickly understand the scenario
I assume this is some kind of homework assignment that I assume would want you to use a counter, because in a real life design you would never do anything like this. What have you done so far, and what problems are you having with it?
Looks like some asynchronous logic/glitches thats affecting the design. An easy way to ensure a simulation/hardware missmatch. Is your design fully synchronous and latch free? Please post the code
Hello, I assume that you have learnt the concept of testbench environment in System Verilog. I mean you are now aware of main testbench components like monitor, driver, stimulus generator,.... if so you need only to pick any ready design (gray counter, FIFO,..) then start creating testbench for it using System Verilog. If your target is to use sys
Formal tools called property checkers can mathematically prove that, given an RTL design and some assumptions about the relationships of the input signals, an assertion will always hold true. If a counter example is found, the formal tool will provide details on the sequence of events that leads to the assertion violation. If this is true, do we
am going to design a programmable divider it includes prescalar(P), main counter(M) and swallow counter(S). i need to clarify what are the values we need to give for P,M and S (ratio).
Hi all! I used the add net constraint in my rtl design. However, the conformal tool still has a passing result even i constrained the LSB(counter_c) of my counter. add net constraints one_hot counter_c -golden report net constraint Why is this?? Thanks..
Considering that you are making the poor design decision to generate a clock from the output of a counter, you should at the very least synchronize the inputs to the FSM driven by that clock.
Hello everybody, I designed and implemented an 8-bit microprocessor including ALU, Program counter, Accumulator, Memory, Instruction Register and MUX modules. I partially reconfigured ALU and Program counter. My concern is that the implemented design must be on-the fly (must not STOP) while one module is partially (...)
Mod means modulo. It could be anything decimal. Contrary is the binary counter. Here a more deatils description: . Enjoy your design work!
I fear the problem is still poorly specified. What does "read as 5 bunches at a time" exactly mean? Read in one clock cycle? In the latter case, you need a FIFO with different read and write data widths, a feature that is probably unsupported in standard SCFIFO or DCFIFO IP. So you'll either make your own FIFO design (the resource effcient solut
He didn't ask a question. He gave you some information. 75 us is 3750 clock periods at 50 MHz (I'm assuming it isn't 50 milliHertz as the diagram indicates). So design a counter in Verilog that counts to 3750. When it gets there, it outputs a pulse, resets to zero and counts again. That will give you your 75us timing marker. r.b.
EN1 = high always MR goes low when U2(+) exceeds 2V switching on Q1 to dump C Voltage and then (+) goes low , then counting is Reset. I think MR needs to be inverted.or counter disabled with EN1=0 until counter is read, then do reset Q1 and MR=1 not sure where you got design, I did not verify completely, but I recall Labs using RCA app (...)
If you are you working at very high speed, you will need probably work with a synchronous design. At standard counter based on cascaded FFs, the clock for the next one is the output from the previous one, and this means that a propagation delay of each device will be cumulatively accounted, generating transient logic states.
Building logic with FFs and gates is structural design. it can be described in Verilog, but doesn't use states. Or you write a behavioral description, define states and the transition conditions. The Verilog compiler translates the design to FFs and gates.
Hi , the below code uses dff for mod3 counter design . rst generated (using expression1) does not work,where as rst generated (using expression 2) works . what is the reason ? module dff(output reg q,output qn,input d,clk,reset); always @(posedge clk or negedge reset) begin if(!reset) q<=1'b0; else q<=d; end assign qn=~
Hello everyone, i have the following problem: i designed an analog PLL, a basic one. Composed by a PFD-CP, a passive filter, a VCO and a frequency divider (not programable). The reference frequency is 32.786kHz and the output frequency is 33.5544MHz (N_div = 1024). The corners of the transient simulation are ok, the frequency synthesized by th
Hi, You can refer this link: in this link there is a counter (test) which have inputs clk and reset and output is a count which is similar to your design (corr), in your design also there are clock and reset as inputs and csum as output. J
first define all your unknowns before you ask how to design something. Interrupter time =? Accuracy required=? % frequency resolution =?
can anyone help me to design a circuit, which glows led when it detects 10Mhz lvds differential signal. note: once it detects the signal led should on.(i mean to say that it should nt be on and off). if there is no signal, then led should off.
I presume the test bench could simply consist on provide initial state conditions for QS not allowable on predicted truth table used for design regular operation of such counter. +++
If you actually did the tutorial everything but the reconfigurable portion of the design is the static part. So just add the counter/decoder to the portion of the design that isn't getting reconfigured. Unless there is already a counter and decoder in the XPS then you'll have to create your own component to add. regards
Hello, I am acquiring pulse signal from micro controller sampled at a rate of 100Hz. I want to filter the lowfrequency components pulse signal below 4Hz. I tried like this but it is not working perfectly. Can someone guide me with the lowpass design the data1 here is used is attached below in the text file. d = fdesign.lowpass('N,Fc',31,4
Can any help me to design a 4 bit counter in vhdl.I want that counter gives 0 for count 0 t0 7 and 1 for 8 to 15.please reply fast
Hi guys noob here, first post. I need to design a program counter to satisfy the following schematic. 101185 and here is my code so far. Now I'm pretty sure this is wrong. But I don't even know how to test this yet using QuartusII, hoping my TA will explain it this Monday. Would someone with more experience take a loo
Almost EVERY student made an electronic clock in university. But since you are not designing a circuit then are you simply learning how to copy and to solder? There are thousands of digital stopwatch, digital counter and electronic clock projects in Google. Copy one then learn how to solder. Oh, you will use a breadboard with wires all over the pla
The following is one simple 4 bit up counter verilog code I made using a 4 bit adder verilog code ( a working file , tested). I happens that when I include the adder instantiation the clock stops working and hence entire code stops working. Any suggestions of what possibly went wrong???? module four_bit_counter( output reg [3:
this might be a question of ambient light suppression. What is typically used is a pulsed operation with optical filters( ). Enjoy your design work!
Dear experts, I have a design needs to run on variable clock rates (400KHz to 100MHz). Currently I use a generated clock from counter logic. I am thinking about using the generated clock to connect directly to those dependent logics (not very big, just some shift registers and FSMs). I understood when clock is fast > 20MHz, generated clock
This is very simple timer logic, power up 500us, reset 200us, and the cke.... If you want to make generic/programmable logic to control such process, you have to write several timers/counter to do it. How to create/synthesize a power up sequence for a specific design? Let's take for example a DDR3 memory controller
hi all sorry for my bad English. i want to make a frequency meter Circuit only using Logic gate's ,ttl ic's. and use 7-segment's for displaying. I do not want ,and haven't allow to use avr or cmos IC's. i cant find any Schematic from internet, please help me. tnx
hi all can we design a mod-3 counter with 30% duty cycle please let me know
In VHDL, I don't have any good idea. But I can suggest you use your friend Google to look for "single event upset design harden" for more general information on methods. There's more to it than just trying to duplicate and vote everything. You have to have a way to check the design for things like state-machine (incl counter) states that (...)
it generates a pulse everytime the value of the counter is reached To create a register, the flag must be set in synchronous (clock edge controlled) code. You also need to initialize the register. In a real design, there would be a means to reset the output, otherwise it's pretty meaningless.
Hello there can you please help me to collect my circuit,I design a digital clock in proteus the counts of minutes 00-59 is ok,but for hours I am not able to design the 24hours counter but in proteus the circuit is running very well,can you please help me. Thanks.
Try to find out which parameter variation(s) (vth ?) mainly affect the propagation delay time - then you can venture for design counter action.
Hi Sunil, At what level do you design? In general, append an additional bit with 0 value to the output of the binary counter. For example, if you had 10-bit binary counter, you'll have 11-bit counter. LSB bit will be tied to 0. assign cnt_out = {counter, 1'b0}; Regards, Vardan
Hi, I am going through the Altium tutorial here on implementing an FPGA design (simple counter) in Altium. I am having trouble with the "Wiring the design" portion in that I cannot seem to connect U5 and U1 to the Q bus on U2, which drives some L
What kind of help do you need? Do you want somebody to design it for you, or do you have a specific question?
Hi i want a verilog hdl code for a 4 bit asynchronous counter using reversible logic gates.
Having no details on pedometer circuit and possible electrical output, I cannot advise. It may be possible but you must find if such output is available from your device. You can design a 1-15 step counter driven from the pedometer sensor, to get the control pulse you need.
Hello, I design a system where I have to switch a PSU line to different devices (about 16 of them), in order to enable or disable them. This switching has to be done using a microcontroller, with the least use of pins possible. Finally, two or more devices have to be enabled simultaneously, so the simple decade counter solution is not good.
Definitely not the right way. The counter can't work at all in a level triggered (asynchronous) always block. Think about a synchronous design based on the clock input. After synchronizing the button input in a register chain, count it#s high and low states, etc.
Hello friends, i'm working on a wheel speed measurement circuit. I'm stuck. The algo goes like this the rotating wheel generates 8 pulses per rotation and I'm supposed to measure the speed. What I am doing is that I took 2 counters one 4 bit and another 32 bit, both the counter starts at one time(the moment we start measuring speed) lets say for
adriang, The approach you must take is tracking, which is based on top view image recognition, due must predict : --> Return of the same person back to the path, without recount, but just once. --> Multiple persons crossing the counter section. This is not a simple design, and some companies are developing to some applications. For
Why don't you start to write down the intended functionality as behavioral code? A small hint for free: You can implement the "divider" by adding or substracting (depending on your preferred design style) ND instead of 1 to/from the counter. ND=1000 can't be represented in 8 bit, by the way.
I did my Fisrt FPGA project, that is a free running 4 digit counter, Is working like a charm but I think is to much for to litle. Is my design ok, ? Have any way to optimize for less resource. I'm a newby on FPGA, but a experienced microprocessor programer, I'm afraid to use old stuff that is not the best for Fpga world. Please coment a