768 Threads found on edaboard.com: Design Counter
hello guys ,
how to design counter usign combinational circuits
pls urgent for my design
ASIC Design Methodologies and Tools (Digital) :: 27.12.2007 01:12 :: venkatesankalidass :: Replies: 2 :: Views: 802
I am facing sometime my counter is stuck at 0 during simple 3bits upcounter by using 7474 IC.
After I reconnect again. It is work. It is happen quite often. So I need to clearify myknowledge.
Normally I connect all PREset pins to VCC and all CLeaR pins to switch. When ever switch on the counter will run from 000o 111.
Electronic Elementary Questions :: 17.09.2005 05:31 :: MRFGUY :: Replies: 2 :: Views: 1055
We are analog designers but sometimes we also need to do some digital work.
My current project need a digital phase detector and a 5-bit counter. I've pretty few experience in digital. Advice needed!
Analog Circuit Design :: 18.11.2005 04:29 :: Alles Gute :: Replies: 1 :: Views: 1274
Can any body help me regarding analog design interview questions
Thanks to all
Analog Circuit Design :: 15.02.2007 00:34 :: satyakumar :: Replies: 18 :: Views: 37472
i wish to design counter which can count upto both integer and integer +decimal part like for 3,6,7.2, 11.87,etc???
i do not understand how will the shifting help me and in this case what will happen to the integar part....
ASIC Design Methodologies and Tools (Digital) :: 06.09.2012 07:07 :: mohi@608 :: Replies: 14 :: Views: 399
how to design PLL circuit?
20Hz-20Khz multiplier with 360.
I use 74HC4046 and CD4059,It not work!!
Help me design with other IC.
Other Design :: 22.03.2002 10:48 :: microelek :: Replies: 1 :: Views: 3664
You can use, as wrote alledauser, a T1/E1 framer after a line interface component.
Generaly , a framer include registers (counters) for :
- Framing errors F bit (T1) or TS0 (E1).
- Line code violation.
- CRC6 (T1) or CRC4 (E1) errors.
- Loss of frame alignment.
- Changes in frame alignment.
With a ?C like 8031, you only need to i
Professional Hardware and Electronics Design :: 23.01.2003 12:25 :: papyaki :: Replies: 4 :: Views: 1099
can any body tell me how to design ADPLL component ,i.e PD, loop filter and ID counter
Professional Hardware and Electronics Design :: 05.02.2003 22:25 :: shahrol_hisham :: Replies: 2 :: Views: 1825
In DPLL design, two frequency should be input: one is reference frequency, the other is the frequency to operate counter and inc_dec module, which is much higher, 8 times(or higher) of reference frequency. So in the USB design where the data rate is 12Mb/s or 1.5Mb/s, there is no problem. But if the reference frequency is much higher, then (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 23.02.2003 20:30 :: snakebites :: Replies: 2 :: Views: 2262
How to design DPLL. if you have doc about DPLL, please send it to me .
Professional Hardware and Electronics Design :: 10.04.2003 09:51 :: cslover :: Replies: 5 :: Views: 1169
i want cheap design. yes pic is good choose.but i dont understand asm code. :( and how is create schematic?
Hobby Circuits and Small Projects Problems :: 15.04.2003 17:28 :: SeTRoX :: Replies: 8 :: Views: 2044
i am working on designing an energy meter
this shall be designed in vlsi , not using a microcontroller
the idea of project is to use ade7757 chip and inteface this chip with xilinx cpld
the o/p of this cpld shall be given to an eeprom , where all the energy readings shall be saved.
this readings can later be used for calculatin
Professional Hardware and Electronics Design :: 19.05.2003 05:55 :: fusion :: Replies: 2 :: Views: 1337
You can refer the FIFO design.
I think it will help you.
Or simply use a RAM to store the data, a counter to count the data number in RAM, you can make it work easily.
PLD, SPLD, GAL, CPLD, FPGA Design :: 23.05.2003 23:39 :: leon :: Replies: 3 :: Views: 1733
Can anyone help me out on this, i need to design a frequency counter for the range 1Hz to 2Mhz using 82C54 and 89C55wd. I have designed a circuit but it gives an error of 1Hz @ 1000-3000, which keeps on increasing as the measurement frequency is increased. Currently i have mazimum range of 132Khz and the circuit is designed (...)
Professional Hardware and Electronics Design :: 07.10.2003 06:19 :: provision :: Replies: 0 :: Views: 1229
Finaly i get solution and design my own circiut for divide by ten hope help full for other also
Professional Hardware and Electronics Design :: 31.10.2003 04:14 :: Fragrance :: Replies: 1 :: Views: 1771
For short info you can check here: go down to July 2000.
I haven't build this design but a similar from elektor with same chip, I am satisfied. I think it is good for hobby/semi pro use.
If you have problem DL this file the asm and hex code is available at thei HP, if you like to check.
Microcontrollers :: 27.10.2003 13:48 :: Cluricaun :: Replies: 33 :: Views: 21428
Any idea about a 2ghz oscillator design to feed an binary counter? The output should have at least 500mv peak to peak to drive the input. Thanks,
RF, Microwave, Antennas and Optics :: 29.01.2004 07:33 :: pisoiu :: Replies: 7 :: Views: 2030
I implemented some up/down resettable counters in my CPLD with Verilog. I routed bits of the counters to the pins of CPLD, they are working fine... Now I want to read the contents of these counters using a simple (simplest) serial interface with a microcontroller.
I've to select counter number, then read it (16bits)... (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 19.03.2004 17:06 :: Sobakava :: Replies: 1 :: Views: 1856
and search papers on IEEE Xplore website. including the classical one by Riley, Copeland and Kwasniewski
You can also take a look at the Synthesizer course notes on Professor P.Allen's website at Georgia tech. don't have the link handy now.
have fun and give feedback so t
Analog IC Design and Layout :: 28.03.2004 16:27 :: uncle_urfi :: Replies: 27 :: Views: 10575
I am about to implement an vhdl ADPLL in the next weeks.
i found a good explanation about adplls adpll code can be found at:
if you find out how good or bad the example implementation is let me know plea
Other Design :: 16.07.2004 05:06 :: hanstarro :: Replies: 2 :: Views: 3261
Electronic Elementary Questions :: 25.04.2004 07:13 :: ddt694 :: Replies: 14 :: Views: 18934
Have the counter with the same specifications if the clock is negative triggered better use a not gate before it
design a counter such that the modulus is such that the output is clearly identifiable by using the led at the out put
Better use TTL as it has less Propagation Delay
Analog Circuit Design :: 04.05.2004 06:39 :: vempus :: Replies: 4 :: Views: 2332
I am learning LFSR, for its application, can it be used as a counter?
e.g. If I want to count from 0000 to 1111, how to use LFSR? I have thought much on it. But I can't find a way to use it. Maybe it can only be applied on some specific counters instead of all kinds of counters. Am I right?
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.06.2004 01:35 :: hover :: Replies: 2 :: Views: 1045
How can I design a converter that will take 100mV p-p sine wave at 20 MHz and convert to TLL level square wave to drive digitial circuits.
RF, Microwave, Antennas and Optics :: 23.06.2004 14:32 :: vco96 :: Replies: 2 :: Views: 1152
I'm a beginner of the RF design.
I want to design a *5 mulitlier.
I have a 1.945Ghz signal.
I want to get a 9.725GHz signal use the Ma-com MA44621A.
Thank you!! :?:
RF, Microwave, Antennas and Optics :: 04.07.2004 23:37 :: mmm0524 :: Replies: 2 :: Views: 672
anyone have the original pcb design?
Microcontrollers :: 22.07.2004 05:34 :: leemarrow :: Replies: 6 :: Views: 2433
I am planning to design a microcontroller trainer, can the members suggest what devices can I include with it.
Start from the simplest such as LEDs.
Btw, can the members also post here a link for Microcontroller Manual used for laboratory exercises.
Professional Hardware and Electronics Design :: 24.07.2004 07:37 :: glenjoy :: Replies: 3 :: Views: 1117
I am useing PIC16F87A to detect the frequncy change on RA4 by counting the input pulse of TMR0. The frequency is around 80KHz depending on the sensor and the OSC is 8MHz. In every 160ms, the number of pulses is 0x36B5 or 0x36B6 which means the frequency is stable.
I want to detect one or two more pulses in this period as quick as possible. So, I
Microcontrollers :: 26.07.2004 13:00 :: HeiFelix :: Replies: 4 :: Views: 1225
Here is what I would like to do for the incoming Bit stream of 0's and 1's.
The moment I see '01' I need to jump (or skip) the next incoming 45 bits and check if the next 3 bits are '1'. If yes then I need to print a "Success" message.
Could anyone please tell me if its possible for me to jump (or skip) 45 bits and check the next
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.07.2004 00:30 :: EEEngineer :: Replies: 3 :: Views: 767
fpga based system could be simplest like counter design or hardest like high-speed transceiver design. verilog or vhdl is recommended to build your career in this field. besides, the skill of logic optimization, timing tuning need to be study to establish high performance design.
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.08.2004 07:09 :: cawan :: Replies: 14 :: Views: 1348
Yes, you have to design prescaler by hand for operating at 4GHz
You may need use CML flip-flop for your prescaler.
RF, Microwave, Antennas and Optics :: 10.09.2004 10:36 :: computer_terminator :: Replies: 8 :: Views: 1483
The period is 1 second, duty is 10%(100ms).
How to design such square wave osc and integrated on one chip?
Analog IC Design and Layout :: 18.09.2004 03:27 :: leonken :: Replies: 4 :: Views: 1384
Here is an application where you can find the answer:
design, Construction, and Testing of a Microwave Radar System for Through-Wall Surveillance
Electronic Elementary Questions :: 12.10.2004 10:29 :: vfone :: Replies: 4 :: Views: 1169
I am just design a DDS and decides to use the pipeling adder to implement the phase adder of DDS. But the problem is that for a pipeling adder, it may take n clocks to get the adding result, while the adder in fact needs to result of the first adding clock to be ready when the second adding clock begins. So it is contraversive, I cannot solve it, w
PLD, SPLD, GAL, CPLD, FPGA Design :: 13.11.2004 06:43 :: wizardyhnr :: Replies: 4 :: Views: 846
actually, how many approaches are there to design a divide by n counter?
Depends how do you want to look at it. There are many ways. I am putting a figure using 7490 decade counter IC.
Electronic Elementary Questions :: 22.11.2004 15:49 :: djalli :: Replies: 15 :: Views: 4733
Out of your discussions Im going to point one issue.
May be this is the reason of malfunction of the advised circuit.
The input of the relay must be shunt with a reverse diode. Because reverse current from the relay can demage the switching transistor.
Agree... as a good practise, we need a diode across input of the relay
Analog Circuit Design :: 05.12.2004 05:49 :: nicleo :: Replies: 45 :: Views: 4812
First off, I took a class in IC design a few years ago, but most of it is pretty foggy. I know my way around, but remembering how to build specific circuits is a wash. For all of you, this will be an easy one.
Here is what I want to do, I want to build a simple counter. Basically I have two inputs, A & B. They will control 10 outputs.
Analog IC Design and Layout :: 30.12.2004 03:14 :: nightdesigns :: Replies: 6 :: Views: 710
Any good document about arbitrary Sample Rate Conversion filter design?especially about fractional ratio conversion,and be efficiency to implement.
Digital Signal Processing :: 19.01.2005 00:50 :: blueteeth :: Replies: 5 :: Views: 1551
why do you no post here as attachment?
I had made one for my old vacuum tube receiver. It uses PIC microcontroller, the highest working frequency is 50MHz, and could be reach 1G by freq devide chip. If anyone needs the total design, please contact me by email or message, I will send the P*otel design files to you.
Professional Hardware and Electronics Design :: 02.03.2005 08:22 :: leemarrow :: Replies: 12 :: Views: 5683
You can generate a variable width pulse train as follows: In your design
define a counter which can hold a value >= max value of pulse width required in clock cycles. then declare a register which stores the value of the reqd pulse width in clock cycles. Then write the logic so that the counter while counting is reset whenever its (...)
ASIC Design Methodologies and Tools (Digital) :: 27.01.2005 01:12 :: masai_mara :: Replies: 2 :: Views: 885
please help me for design of 24h clock /3 digit counter just with gate & BCD counter IC
Microcontrollers :: 05.02.2005 04:41 :: MHML :: Replies: 1 :: Views: 1282
I'm trying to build a beats-per-minute counter.
I've got the microcontroller part all ready and done, however, I'm having trouble with the circuit which is supposed to generate a nice digital wave form (with a change from down to up on a beat). Here is what I did, and it works fine as long as there's a steady and simple beat :/
Analog Circuit Design :: 13.02.2005 12:02 :: eranrund :: Replies: 0 :: Views: 592
im looking for a circuit design plan or pcb track pattern annotated, for a backward counting circuit from 9, the tricky part is the next need, i would like a push to break switch to be used, and when the button is pressed the count stops on the number it was at.
i have given thought to the use of BCD counting and or decade countin
Analog Circuit Design :: 14.02.2005 14:12 :: cole7011 :: Replies: 7 :: Views: 772
Hello everyones !
I'm a new member on this forum. I come from Vietnam as a electronics engineer.
I've tried to design a RTOS kernels on 89c52 with 8KB ext RAM. It just the way to learn Real-time Linux.
My evalution board consist a 89c52 with 8K RAM (6264) at 0x8000. There are 16 task in my design, each task has a 256 bytes external memory.
Embedded Systems and Real-Time OS :: 15.02.2005 05:09 :: opentdoors :: Replies: 16 :: Views: 6125
I have an RF counter by Radio Shack 22-305. I was wondering if you could explain to me how to use it properly? I'm just getting started in antenna technology and want to have some idea of how to tune the antenna that I'm working on and would like to know how to use and set the RF counter.
I actually came up with an idea to build an antenna t
RF, Microwave, Antennas and Optics :: 18.02.2005 11:29 :: Robert A. Patterson :: Replies: 0 :: Views: 770
Instead of using all those scary asynchronous counters and resets, you should redesign using only synchronous counters.
Here is a two-digit synchronous BCD counter that counts from 00 to 66 then back to 00:
module top (clk, bcd);
output reg bcd = 0;
always @ (posedge clk)
bcd <= bcd == 8'h66 ? (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 01.03.2005 02:21 :: echo47 :: Replies: 3 :: Views: 2310
There is a tutorial for this, here:
For logic diagrams, you just need a bunch of T registers, with extra logic if you need a synchronous counter. See these:
Microcontrollers :: 05.04.2005 12:16 :: FoxyRick :: Replies: 2 :: Views: 1316
this can be done with two schemes,
A-adding an extra bit on the counter used as a flag, for example if you have a 16 word FIFO, then you use a 5 bit counter rather than 4-bit counter, this way comparing this extra bit will flag you if you are going to full or empty.
B-to use a direction flag according to the position of the (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 14.04.2005 03:09 :: bibo1978 :: Replies: 4 :: Views: 3512
I'm assigned an exercise to program an AT89C51 for automatic door project.
I'm facing a problem: TIMEOUT
if the outer sensor detects people available, it will open the door and waiting the inner sensor detects people available. After 20s, if no signal is detected, it automatically close the door and return to the beginning of the program (wai
Microcontrollers :: 27.04.2005 13:02 :: semiconductor :: Replies: 3 :: Views: 849
The simplest decimator it is a counter - first order digital filer+ decimator.
For this case modulator must be also first order. design is very
simple - 1 OpAmp, 3 capacitors, 1 comparator-latch.
Analog IC Design and Layout :: 09.05.2005 10:09 :: sergeyr77 :: Replies: 6 :: Views: 1725