411 Threads found on edaboard.com: Design Counter
My name is Alex and I'm currently working on a datapath design. The instructions are: design a system that sum the values stored in a memory from a specific address. The sum system includes the design of and finite state machine (FSM) and a datapath. A test bench is provided to validate your system.
I have already search and (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-28-2016 22:24 :: Alex_Ivan :: Replies: 4 :: Views: 273
No, there's no counter involved in SRAM design, just row and column address decoder. Where did you get the idea?
ASIC Design Methodologies and Tools (Digital) :: 11-19-2016 15:16 :: FvM :: Replies: 4 :: Views: 451
I am trying to debug my ALU design in FPGA. I am using trigger immediate option after downloading the bit stream to FPGA. But the chipscope never displays the signal values starting from program counter=0 and the waveform starts from some other value of program counter. How to resolve this issue, I need to capture real time data.
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-14-2016 12:28 :: DeepikaA :: Replies: 5 :: Views: 444
I am trying to design a Mod 6 3-Bit D-type asynchronous down counter using Pspice and I am having difficulty with the Nand gate in order to make the count go from 5-0. In its present state it is counting from 7-0 and I know with the addition of adding a NAND gate I can reduce the count to the desire 5-0 but I have no idea how to connect the g
Elementary Electronic Questions :: 09-01-2016 20:36 :: TunerPhish :: Replies: 7 :: Views: 1296
I have a design created in Hspice. I want to verify this hspice netlist against some input stimuli. Is there a tool that I can use for this?
For example, Suppose I designed a 4 bit counter using T FFs. Is it possible to verify if the counter is functionally working correct using some tool given the (...)
ASIC Design Methodologies and Tools (Digital) :: 07-14-2016 00:06 :: maestroharsh :: Replies: 4 :: Views: 438
There are 2 ways to design synchronous FIFO that I know:
1. Using n+1 bit counters for write pointer and read pointer. In this case, since it is 8 location FIFO, you can use 3+1 = 4 bit counter. To detect full and empty is simple:
FULL: WP-RP = 4'b1000
We cannot decide full and empty conditions based on MSB. This (...)
ASIC Design Methodologies and Tools (Digital) :: 06-21-2016 18:55 :: abhiverma812 :: Replies: 2 :: Views: 760
FPGA synthesis tools have timing analysis to check if a design is able to run at the intended clock frequency and usually also implement timing driven synthesis to tune the design for maximum speed if required. So the first step would be to write suitable timing constraints and determine the achievable counter speed.
Not knowing the used (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-31-2016 22:03 :: FvM :: Replies: 13 :: Views: 464
There are special design methodologies for sequential asynchronous circuits. Following these methods, it can be possible.
You only mentioned a bare idea instead of giving a logic circuit. Thus we can't see how your design fails.
ASIC Design Methodologies and Tools (Digital) :: 05-30-2016 10:25 :: FvM :: Replies: 2 :: Views: 323
I am trying to synthesize a counter which has 16 instances only.while doing cts it is giving high utilization more than 100% so it is aborting.
I have started the design with 20% util because it gave problem with 40% util.please some one say me the fix.
ASIC Design Methodologies and Tools (Digital) :: 05-28-2016 16:01 :: cyrax747 :: Replies: 3 :: Views: 470
Hello Dave, please find my code below:
always@(posedge clk,negedge reset)
dout <= 0;
dout <= din;
ASIC Design Methodologies and Tools (Digital) :: 04-18-2016 04:10 :: spandus :: Replies: 2 :: Views: 409
You should probably have range checks on the CNT value. Maybe SHORT = 2-4 and LONG = 5-7.
Restart the decoder if you get a value outside of these ranges.
Do the development and debugging with a simulator and a test bench (the Altera version of Modelsim). It is a waste of time to do all of the debugging on the real hardware.
When you go to the
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-07-2016 07:48 :: std_match :: Replies: 9 :: Views: 918
Your question doesn't make sense and also it is in the wrong community! No wonder till now there were no replies.
How can you write a TB for just ANY example netlist? If you don't know the functionality of the netlist you cannot write a TB.
Create a simple design (say a 3 bit counter) and generate its netlist. Then write the TB for it (in fact eve
Software Links :: 03-02-2016 10:22 :: dpaul :: Replies: 3 :: Views: 42
You should be able to get the details from a processor design manual/spec. At a very high level, instruction cache is the cache memory which stores the instructions that will be executed sequentially in a processor. The program counter will point to the memory address of the instruction that needs to be fetched, the I-cache controller looks up the
ASIC Design Methodologies and Tools (Digital) :: 01-25-2016 22:37 :: saurabhr8here :: Replies: 1 :: Views: 449
Your tff component doesn't work, because input t isn't used in the logic. And it won't compile in your design because it has an unconnected reset input without default value.
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-20-2015 23:18 :: FvM :: Replies: 11 :: Views: 824
The code in post #1 isn't related to UART, just sending 8-bit words. It's neither implementing a 32-bit counter.
Apparently you copied a third parties code that is loosely related to the thread topic, but doesn't actually help to solve it.
Writing a programmable logic design starts with a specification:
- input and output signals
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-18-2015 07:46 :: FvM :: Replies: 4 :: Views: 418
This is probably a timing issue from poor design practice. Generating a clock with logic can be prone to timing issues. I would move the counter in to the clock domain and your problems may go away
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-12-2015 16:54 :: TrickyDicky :: Replies: 4 :: Views: 554
Although variable usage for tx_reg and counter reduces the achievable design speed (creates large combinational pathes), the design looks functional.
How did you stimulate tx_data_bus in your hardware test?
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-10-2015 13:00 :: FvM :: Replies: 5 :: Views: 541
I am using vivado 2015.2.1 . I designed up-down counter. I am getting error. (mentioned below)
Find my code below:
input wire reset,clk, uphdnl,count;
//output reg out0,out1;
output reg sseg;
output reg an;
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-11-2015 20:45 :: Kuldeepluvani :: Replies: 3 :: Views: 1427
Tricky question because if you use some conceptual design as shown it is not real design, then all you can use are block diagrams.
Then you must dream up your own logic symbols using standard shapes and text.
Not very good for detail oriented Engineers but perhaps ok for your purposes.
For example the Johnson counter you have (...)
Software Recommendations :: 08-09-2015 21:23 :: SunnySkyguy :: Replies: 10 :: Views: 124
This is my first post on this forum, so bear with me!
First some background:
I'm currently studying Electrical and Electronic Engineering and I've been tasked by my company to design a prototype PCIe card for testing PCIe connection functionality on our products. This is part of my final project for the course, which has to be work-based
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-06-2015 10:33 :: Andy Seager :: Replies: 2 :: Views: 384
What is up with all the vague questions lately that require clarification?
I think a sticky note is needed which can contain explanations regarding
1> How to ask question related to h/w design & its implementation, what things need to be included in the Qs for others to better and quickly understand the scenario
ASIC Design Methodologies and Tools (Digital) :: 08-05-2015 08:44 :: dpaul :: Replies: 4 :: Views: 571
I assume this is some kind of homework assignment that I assume would want you to use a counter, because in a real life design you would never do anything like this.
What have you done so far, and what problems are you having with it?
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-15-2015 13:11 :: TrickyDicky :: Replies: 1 :: Views: 537
I have used three clocks in my design (40, 160 & 800HMz). The Fmax for the design was estimated 300.82MHz by ISE XST. Will it be a problem for the design ?...actually only a counter in running at 800MHz that too of 4bits only. I had done PAR simulation for each module of the design and individually there (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-01-2015 08:25 :: dpaul :: Replies: 12 :: Views: 650
I assume that you have learnt the concept of testbench environment in System Verilog. I mean you are now aware of main testbench components like monitor, driver, stimulus generator,.... if so you need only to pick any ready design (gray counter, FIFO,..) then start creating testbench for it using System Verilog.
If your target is to use sys
ASIC Design Methodologies and Tools (Digital) :: 04-12-2015 07:08 :: muhammad_ali :: Replies: 3 :: Views: 829
Formal tools called property checkers can mathematically prove that, given an RTL design and some assumptions about the relationships of the input signals, an assertion will always hold true. If a counter example is found, the formal tool will provide details on the sequence of events that leads to the assertion violation.
If this is true, do we
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-25-2015 09:22 :: matrixofdynamism :: Replies: 1 :: Views: 354
am going to design a programmable divider it includes prescalar(P), main counter(M) and swallow counter(S). i need to clarify what are the values we need to give for P,M and S (ratio).
Software Problems, Hints and Reviews :: 02-12-2015 09:06 :: ramya15 :: Replies: 0 :: Views: 441
I used the add net constraint in my rtl design. However, the conformal tool still has a passing result even i constrained the LSB(counter_c) of my counter.
add net constraints one_hot counter_c -golden
report net constraint
Why is this??
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-03-2015 03:07 :: nohj_yar :: Replies: 0 :: Views: 587
Considering that you are making the poor design decision to generate a clock from the output of a counter, you should at the very least synchronize the inputs to the FSM driven by that clock.
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-21-2015 03:27 :: ads-ee :: Replies: 3 :: Views: 826
I designed and implemented an 8-bit microprocessor including ALU, Program counter, Accumulator, Memory, Instruction Register and MUX modules. I partially reconfigured ALU and Program counter. My concern is that the implemented design must be on-the fly (must not STOP) while one module is partially (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-19-2015 15:04 :: msdarvishi :: Replies: 1 :: Views: 463
Mod means modulo. It could be anything decimal. Contrary is the binary counter. Here a more deatils description: .
Enjoy your design work!
Elementary Electronic Questions :: 12-08-2014 17:17 :: HTA :: Replies: 2 :: Views: 649
I fear the problem is still poorly specified. What does "read as 5 bunches at a time" exactly mean? Read in one clock cycle?
In the latter case, you need a FIFO with different read and write data widths, a feature that is probably unsupported in standard SCFIFO or DCFIFO IP. So you'll either make your own FIFO design (the resource effcient solut
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-16-2014 16:03 :: FvM :: Replies: 38 :: Views: 2976
He didn't ask a question. He gave you some information. 75 us is 3750 clock periods at 50 MHz (I'm assuming it isn't 50 milliHertz as the diagram indicates).
So design a counter in Verilog that counts to 3750. When it gets there, it outputs a pulse, resets to zero and counts again. That will give you your 75us timing marker.
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-22-2014 12:12 :: rberek :: Replies: 7 :: Views: 975
EN1 = high always
MR goes low when U2(+) exceeds 2V switching on Q1 to dump C Voltage and then (+) goes low , then counting is Reset.
I think MR needs to be inverted.or counter disabled with EN1=0 until counter is read, then do reset Q1 and MR=1
not sure where you got design, I did not verify completely, but I recall Labs using RCA app (...)
Elementary Electronic Questions :: 10-18-2014 19:24 :: SunnySkyguy :: Replies: 8 :: Views: 792
If you are you working at very high speed, you will need probably work with a synchronous design.
At standard counter based on cascaded FFs, the clock for the next one is the output from the previous one, and this means that a propagation delay of each device will be cumulatively accounted, generating transient logic states.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 08-31-2014 11:12 :: andre_teprom :: Replies: 16 :: Views: 699
Building logic with FFs and gates is structural design. it can be described in Verilog, but doesn't use states. Or you write a behavioral description, define states and the transition conditions. The Verilog compiler translates the design to FFs and gates.
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-24-2014 21:12 :: FvM :: Replies: 5 :: Views: 4119
the below code uses dff for mod3 counter design . rst generated (using expression1) does not work,where as rst generated (using expression 2) works . what is the reason ?
module dff(output reg q,output qn,input d,clk,reset);
always @(posedge clk or negedge reset)
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-20-2014 08:28 :: strangesiva :: Replies: 3 :: Views: 803
If VCO is too high and loop design uses negative feedback correctly, it tells me input frequency is too noisy or too many transitions OR the /1024 counter is not working with null output and VCO is trying to go higher to create a matched frequency same as reference. In either case it is "unlocked or open loop" and V(vco control) is stuck high.
Analog Circuit Design :: 08-05-2014 22:12 :: SunnySkyguy :: Replies: 11 :: Views: 711
You can refer this link:
in this link there is a counter (test) which have inputs clk and reset and output is a count
which is similar to your design (corr), in your design also there are clock and reset as inputs and csum as output.
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-09-2014 03:36 :: imbichie :: Replies: 3 :: Views: 616
first define all your unknowns before you ask how to design something.
Interrupter time =?
Accuracy required=? %
frequency resolution =?
Microcontrollers :: 04-08-2014 00:17 :: SunnySkyguy :: Replies: 11 :: Views: 655
can anyone help me to design a circuit, which glows led when it detects 10Mhz lvds differential signal.
note: once it detects the signal led should on.(i mean to say that it should nt be on and off). if there is no signal, then led should off.
Many ways are lie a head !
one of the simplest ones is using a filt
Analog Circuit Design :: 03-25-2014 17:03 :: goldsmith :: Replies: 7 :: Views: 879
I presume the test bench could simply consist on provide initial state conditions for QS not allowable on predicted truth table used for design regular operation of such counter.
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-07-2014 02:58 :: andre_teprom :: Replies: 12 :: Views: 2938
If you actually did the tutorial everything but the reconfigurable portion of the design is the static part. So just add the counter/decoder to the portion of the design that isn't getting reconfigured.
Unless there is already a counter and decoder in the XPS then you'll have to create your own component to add.
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-27-2014 18:00 :: ads-ee :: Replies: 1 :: Views: 567
Hello, I am acquiring pulse signal from micro controller sampled at a rate of 100Hz. I want to filter the lowfrequency components pulse signal below 4Hz. I tried like this but it is not working perfectly. Can someone guide me with the lowpass design
the data1 here is used is attached below in the text file.
d = fdesign.lowpass('N,Fc',31,4
Digital Signal Processing :: 02-26-2014 18:02 :: patan.gova :: Replies: 16 :: Views: 905
Can any help me to design a 4 bit counter in vhdl.I want that counter gives 0 for count 0 t0 7 and 1 for 8 to 15.please reply fast
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-28-2014 09:44 :: Deepak.akon :: Replies: 6 :: Views: 448
Hi guys noob here, first post. I need to design a program counter to satisfy the following schematic.
and here is my code so far. Now I'm pretty sure this is wrong. But I don't even know how to test this yet using QuartusII, hoping my TA will explain it this Monday. Would someone with more experience take a loo
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-18-2014 22:41 :: thoughtmaze :: Replies: 1 :: Views: 1106
Almost EVERY student made an electronic clock in university.
But since you are not designing a circuit then are you simply learning how to copy and to solder?
There are thousands of digital stopwatch, digital counter and electronic clock projects in Google. Copy one then learn how to solder.
Oh, you will use a breadboard with wires all over the pla
Elementary Electronic Questions :: 01-15-2014 16:35 :: Audioguru :: Replies: 4 :: Views: 3507
The following is one simple 4 bit up counter verilog code I made using a 4 bit adder verilog code ( a working file , tested). I happens that when I include the adder instantiation the clock stops working and hence entire code stops working. Any suggestions of what possibly went wrong????
output reg [3:
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-11-2014 20:20 :: akipro :: Replies: 5 :: Views: 768
this might be a question of ambient light suppression. What is typically used is a pulsed operation with optical filters( ).
Enjoy your design work!
Robotics and Automation Forum :: 12-22-2013 08:00 :: HTA :: Replies: 1 :: Views: 681
I have a design needs to run on variable clock rates (400KHz to 100MHz). Currently I use a generated clock from counter logic.
I am thinking about using the generated clock to connect directly to those dependent logics (not very big, just some shift registers and FSMs).
I understood when clock is fast > 20MHz, generated clock
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-17-2013 16:28 :: legendbb :: Replies: 2 :: Views: 465
This is very simple timer logic, power up 500us, reset 200us, and the cke....
If you want to make generic/programmable logic to control such process, you have to write several timers/counter to do it.
How to create/synthesize a power up sequence for a specific design?
Let's take for example a DDR3 memory controller
ASIC Design Methodologies and Tools (Digital) :: 11-07-2013 09:45 :: littlebu :: Replies: 3 :: Views: 637