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look up any basic logic design book
We are analog designers but sometimes we also need to do some digital work. My current project need a digital phase detector and a 5-bit counter. I've pretty few experience in digital. Advice needed!
I am facing sometime my counter is stuck at 0 during simple 3bits upcounter by using 7474 IC. After I reconnect again. It is work. It is happen quite often. So I need to clearify myknowledge. Normally I connect all PREset pins to VCC and all CLeaR pins to switch. When ever switch on the counter will run from 000o 111.
For typical interviews, I think some questions relating to the following maybe necessary (1) Understanding of 2-stage Op-Amp design (2) Understanding of current bias and bandgap reference design (3) Understanding of simple inverter transfer function and the operation region w.r.t. each input voltage range. (4) Understanding of layout matching e
i wish to design counter which can count upto both integer and integer +decimal part like for 3,6,7.2, 11.87,etc??? i do not understand how will the shifting help me and in this case what will happen to the integar part....
The following is one simple 4 bit up counter verilog code I made using a 4 bit adder verilog code ( a working file , tested). I happens that when I include the adder instantiation the clock stops working and hence entire code stops working. Any suggestions of what possibly went wrong???? module four_bit_counter( output reg [3:
#15 reg_a = 1'b1; 2) design counter,the counter should display even and odd number? any num of bit we like we can construct we need counter 3) tasks enable functions but not functions? why,explanation needed leave the difference,explanation needed in coding style 4) what is race
Hi wael_moharam, You MUST HAVE , generally, ALL INPUTS in "CMOS-World" at fixed potentials (on GND or VDD_ direct or with for ex. min. 50/100KOhm if you must overlist its level)_THIS IS VERY IMPORTANT, then you dont have controlled logic levels on their with time... If it counts around 0`clock; I think RST can be fix at GND too. CMOS circuits
Try to find out which parameter variation(s) (vth ?) mainly affect the propagation delay time - then you can venture for design counter action.
actually, how many approaches are there to design a divide by n counter? Depends how do you want to look at it. There are many ways. I am putting a figure using 7490 decade counter IC.
Hi friend please help me for design of 24h clock /3 digit counter just with gate & BCD counter IC thanks
hi all, i am trying to design 74192 counter in VHDL but i am unable to understand how to genrate o/p, because as in datasheet they are trying to say-- when countup is having clk and countdn is kept high counter counts in up direction when countup is high and countdn is having clk then counter counts in dn direction (...)
hi iam ravi.i have douts in design of counters.that is design a counter to count from 15 to 63 like to do i have tried this ,i design it as to count from zero to 63 then after 63 i have loaded 15 to it there any good method to solve this type of problems
As another way, you can use HDL based design methodology!
I want to design a programmable counter works at GHz and I do not have a clear idea about that yet. Can you recommend some books or papers or anything related?
I agree with whizkid Very high fequency chip, It is easy to design with method of analog. The synthesis method is very difficult when your design is very huge.
counter --> POWER METER ??? Accurate power meters are not easy to build; have a look at this project: However, if you would like to roughly estimate power drawn by your houshold you can construct this simple circuit:
A classmate and I are designing a count down counter. We have the design for the count down part, we wanted to add a feature that would speed up the counter when a switch was turned on. We basically have two input "clocks", one with regular frequency and one with a multiplied frequency. We just cannot figure out the logic (...)
Hi, I want to design a counter with these conditions: - When en = 1 counter start to count. - After the counter count up to 36, stop. - And then when en = 1 again, it begin to count. But I couldnt make it start and stop as my desire. Does any one has prete ideal for this?
hi evrey one; i need some Vhdl Files about 7 Segment counter(4 digit). and Moris Mano Cpu's design in vhdl. also any other kind of ALU's are wellcom. tnx to all
Hello Almira, I have attached a word document explaining the divide by 5 counter design. For more clearity, you can also refer to the link:
plz help me out in design of mod 5 counter and deccade counter using cmos
The exact problem specification still isn't clear. As already mentioned, the normal way is to define the counter operation in a hardware description language of your choice and let the synthesis tool implement it. You can inspect the gate level netlist to check how it fit's into LUTs and registers. I assume, that you have been given a homework p
Dear experts, I want to design a counter which will depend on a input 8 bit bus . if bus is "10011010" , my counter sequence is 1 ->3->4->7 ->1->3->4->7 loop . if bus is "10000001" , counter sequence is 0->7->0->7 ... loop My bus is random changed . Would you please give me a advise or a reference information (...)
hi, if our design works on some X MHz. then how to design a counter by deriving that clock?
Hi guys , I am designing a mux, i want the select line to be set to 1 on every rising edge and 0 on every falling edge, that way the mux is changing twice every clock cycle. I seem to be having problems getting this to work, any one have any simple code that will do what i require. thanks stuart
design 4 bit counter using hald adder circuit
Hi, Have you any E-book help me for design and layout of up-down counter .
Hi. I'm undertaking a project in school and i've been tasked to design a 9999 counter. I'm new to verilog and thus, i need some help regarding the counter. I'm trying to use if-else and i'm stuck at this part: if(counter<4'd10) begin digit1=counter; end else if (...)
how can i design a program wherein it it connected to a sensor in a stair of buses so everytime a passenger comes in the timer count up and when the passenger goes down the timer countdown,....its like a passenger counter in a bus....kindly help me..
hi all.pls i need someone to help me with a design of a decade counter or any useful link.thanks
hi guys, i need to design a mod n bit counter for my project. how to reset the counter when the desired count. help me. thank you
HI I want to know the way of designing a counter using both the positive and negative edgse of the clock to get output waveforms which are not of 50% duty cycle. Regards
design a 2bit up/down counter with clear using only with gates Pls dont write verilog or vhdl code...
Please any body have idea about car counter how to design it. and the various component to use?
Hi everyone, Having problem with these questions, can someone help me please. Using the JK FF, design a ripple counter capable of implementing the counting sequence as below: F(x)={0,1,2,3,4,6,7} and repeats itself a) Explain the workings of the circuit with special emphasis on the additional circuit required to reset
How can I design a gray code counter using Verilog without using a binary-gray converter?
Hi I know a design for both up-down counter (with two inputs). You might use it also only for down counter, I guess :-) Under thema "up/down counters"
i need to do a project in verilog> design an 8-bit bcd counter using 2 74163 counters and multiplexer 4:1 TABLE OF CONTENTS 1. Project theme -design an 8-bit bcd counter using two 74163 counters and multiplexer 4:1 2. Theoretical approach 3. Structural description of the (...)
The basic idea for any frequency counter is to set a timer, wait till the input on a pin change, calculate the time taken and find the inverse. There are lots of schematics on the net, use google. A very crude design can be found here : Try searching for PIC frequency cou
I think you need two processes in this design. process(clk) --divide this clock by some value so that the counter speed is properly set. end process; process(clk_divided) --a typical counter program clocked at clk_divided. end process; the idea for the freq divider in the first process can be done understood from the following (...)
Hi, I`m working on a DRAM design and can`t find any reference design for a refresh counter. Can anyone point me to a transistor / gate level implementation of a refresh counter? Thank you!
hi any one who know about how to design the digital pid controller using counter method pls give path how to do that.
Hi everyone I have a train of pulses coming in at a varying frequency. I want to design a circuit with a counter that counts these clock cycles on an 8 bit counter, having the counter end/reset every second, sending what has been counted to a processor. Any suggestions?
can any one help me to design a mod 5 counter transistor level nd its layout diagram.......
Hi All, Can anybody help me in answering this question. How can i design 3-Bit Binary counter From 2-Bit Binary counter.
... always @ (posedge clk or posedge reset) begin if (reset) counter <=6'b0; else if (invalid) counter <= counter +1; end .. I wanted a counter which is innitially at zero state and when the invalidgoes high , counter increases by one. What is the wrong with this code? I am unable to get it (...)
Can you please guide me about counter design for sequence 8-4-2-1-2-4? NOT Vhdl or verilog code. Digital circuit design only.... Thanks....
Hello, I'm new to VHDL. I have designed the 2 bit up counter using JK flip flop. But the test bench is not producing the results i need. Please find attached the vhdl code and the test bench. --- 2 bit counter with JK FF library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_unsigned.ALL; -- Uncomment the following (...)
I wonder is it a good idea to design 4 bits up down counter using JK flip flop instead of D flip flop? Sure, why not? See these commercial products (pp. 2 & 3) : 64116