Search Engine www.edaboard.com

Digital Time Delay Circuits

Add Question

8 Threads found on edaboard.com: Digital Time Delay Circuits
I can't really help you with proving whatever you're looking to prove, but I can say that minimum average delay is not necessarily what you care most about, in designing a high performance digital circuit. I've spent a lot of time tweaking logic gates' N and P widths to get the -critical- transition where it needs to be, and averages don't (...)
"a fraction of a second" seems a correct timescale for mechanical relay circuits. digital logic possibly needs a few 10 ns of delay (of course a nanosecond is also a fraction of a second...).
In digital circuits, clock latency is clock delay, which may be clock delay from out of the chip. or clock delay inside the chip by clock buffer insertion.
are you talking about digital circuits or analog circuits.....
digital Integrated circuits A Design Perspective(Senond Edition), Jan M.Rabaey, Anantha Chandrakasan, Borivoje Nikolic
NOT, NAND and NOR are the base of modern digital design. The reasons are: 1. NAND and NOR have smaller area than AND and OR 2. NAND and NOR are faster working 3. All of more dificult devices are built from theese elements. Look for any trigger.
All of are familiar with Propogation delay in digital circuits. But what is contamination delay and how does it occur? Any insights? Does contamination delay also play a part in the total delay of the circuit?
it depond on you process and topology of the digital. normal the logic delay should less than one clock , pay attention to the setup and hold time