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56 Threads found on edaboard.com: Digital Time Delay
Hi , or Hi Mr. Peter (tpetar), I have PIC18F45k22 with DAC MCP4922, I need to design a feedback controller for my INverter 12V Dc to out put of max 9v peak AC 50Hz, sinewave, I use LC filters and at the output to make read by PICMICROPIC 18f45k22 at AN2 channel , I use feedback gain of =0.1 and a noninverting level shifter my circuit I a
Hello, sorry if this is a bit vague, but could anyone give me some tips on how to implement a TDC (based on tapped delay structure) in Simulink. There seems to be very little information online on how to simulate such a device in Simulink. I need it for simulation of an All-digital Phase Locked Loop.
There's no general solution without considerable restrictions of voltage and frequency range. You can't directly create a phase shift for a time domain waveform, you have to measure the pulse period and calculate a time shift. A digital delay of the sampled waveform might be the most simple way. Practically, use a (...)
Hello, I need some assistance in writing the code for a time to digital converter with high resolution for an FPGA in verilog using delay carries. I haven't used verilog in a while so any help would be useful.
In Synchronous digital design, signals are sampled and changed at the clock edge. If a signal change at the clock edge, doesn't the register receiving this signal violate the hold time because the signal changes shortly after the clock edge?Is c to q delay + propagation generally greater than the hold time or do we have to d
Hello every one, Please help me in understanding of digital cicuit design. What are the factors should be considered while designing a Board particularly for Communication protocol. For example time delay of ICS etc., Please send me the link if any, Thanking you, Regards, Bhagavan
Analog audio delay chips for ms delays have been previously manufactured, based on CCD structures. They have been superseded by digital signal processing since 10 or 20 years. Audio delay in a microsecond order of magnitude can be achieved by a few LC stages.
Hi, Well done, its always great to see things start for the first time. Cannot help with the C code detail, but most of the Ports default to Analogue Inputs at power on, suggest you turn then to digital before making them Outputs using ANSEL
HI I am using AD7705 for Analog to digital conversion in my is 16 bit resolution,2 channel,8 input,Sigma-Delta Configuration ADC.I am having doubt that how much time(in ms)it will take to change from one channel to another channel (CH 1 to CH 2) or vice versa.Can you please explain with its calculation....
Hi, I am doing a digital timer using AT89C4051 and DS1307 RTC. time is displayed on 16x2 LCD. I have enabled 1 HZ square wave output and updating the time on LCD every rising edge. The problem i am facing is the RTC time is not accurate. For every 24 hours i observed a delay of 2 (...)
I can't really help you with proving whatever you're looking to prove, but I can say that minimum average delay is not necessarily what you care most about, in designing a high performance digital circuit. I've spent a lot of time tweaking logic gates' N and P widths to get the -critical- transition where it needs to be, and averages don't (...)
Hello, For testing purposes, we' ll need to show some kind of a time delay between RF and LVDS signals on different lines. Can this be done on oscilloscope(a 4-channel digital Phosphor Oscilloscope) without any unforeseeable impact on time characteristics or would I need any type of LVDS-something conversion[/B
Can someone please describe the effect of input delay and output delay on the maximum operating frequency of a circuit ? I knew that max operating frequency of a given digital circuit depends on Tclktoq of launching flop + net delay + combo delay + setup time of receiving flop +/- clock (...)
ECL is fastest among the three because the transistors are used in difference amplifier configuration, in which they are never driven into saturation and thereby the storage time is eliminated. The digital logic family which has the lowest propagation delay time is ECL (Lowest propagation delay (...)
Have you got a delay line between the audio input and the noise gate? Points to a basic dilemma. A classical analog noise gate has no option to implement a delay line with acceptable signal quality. If you think about a state-of-the-art digital delay, you'll end up with a fully digital effect processor. (...)
pls check this digital clock using RTC DS12C887.. this will certainly help.
Hello all, I want to carry out an experiment which consists of "operating" a digital TV channel in the UHF band in order to remove/add contents. The DTV channel is 64QAM, 8MHz bandwidth, 8K subcarriers. After de decoder, the DSP/FPGA will deal with the streams, and then will be encoded again: Will anyone expect an appreciable delayed effect in
Possible yes, but limited in terms of signal bandwith and dynamic. Assuming you mean an analog signal, the best way is most likely by digital processing. Previously, magnetic tape loops have been used for delays in the seconds range.
"a fraction of a second" seems a correct timescale for mechanical relay circuits. digital logic possibly needs a few 10 ns of delay (of course a nanosecond is also a fraction of a second...).
hello all,i faced an interview yesterday and was stuck with one particular question of digital design. the question is as design a Combinational logic which takes a train of pulses with different pulse width (1ns - 5ns) and produces pulses of only 5ns as should discard pulse widths less than 5ns. help appreciated. i have attached a
I did digital clock using 7 segment and 89c52. But delay is incremented when clock hardware working. Its fall to behind about 4 second after 1 hour. If known anyone please tell me. the delay code is: void delay_asec(void) { unsigned char d; for (d = 0; d < 20; d++){ delay_50ms(); } } void (...)
It isn't the frequency of the digital signal that matters on a PCB - it's the risetime (or fall time) of the edge because that's where the data is contained. The critical length is approximately where the roundtrip propagation delay on the trace equals the risetime. For FR4 with a typical Er that works out (...)
i designed a digital circuit,but i don't know the way to evaluate the power and area in Hspice , so i have no idea to compare it with the specification,i know the speed can used the delay time to evaluate ,but how about the power and area of the circuit? is the numbers of the MOS can be used to evaluate the area?can anyone give me some (...)
Hi Sir/Madam, Can anyone share the best method to determine the leakage current for digital block? Thanks.
Hi, Could any one tell me how to compute group delay in matlab for a continuous time filter? I think the command grpdelay() works only for digital filter based on my understandin g of www.google.c
there is a digital input signal to control the turn on/off state of the chip. SPEC of the control input circuit: power supply +5V logical Input high voltage 1.5V (min) logital Input low voltage 0.6V (max) delay time <10ns (best <5ns) a conventional Schmitt (...)
Hi, To calculate the maximum frequency of the digital circuit, you will use the following formula. tCLOCK = tCHQV + tPD(max) + tSETUP. Here, in all FFs, normally tHOLD < tCHQV, means Clock to Q output delay includes the hold time. So we are not considering the hold time for calculating the max. frequency. visit (...)
Hi, I need wary simple telecommand i any frequency. Only thing that it matters is that there is no pll or any delay element like quartz filters. I need it in one direction so it would be one transmitter and one receiver. It is necessary to delay time from moment i enable transmitter to time i detect change on (...)
Real time means that the signal processing does not break the temporal continuity of the output signal e.g. a system acquire 1 ms of base band/ IF/ RF signal and produces as output 1 ms of output signal. Signal processing takes part both in the analog and digital domain: the analog processing is mainly characterized by a delay but the (...)
In digital circuits, clock latency is clock delay, which may be clock delay from out of the chip. or clock delay inside the chip by clock buffer insertion.
are you talking about digital circuits or analog circuits.....
digital Integrated Circuits A Design Perspective(Senond Edition), Jan M.Rabaey, Anantha Chandrakasan, Borivoje Nikolic
Deley spread is the time interval between arival of the first and the last delayed path of a signal in the receiver , and is denoted by Td.The coherence BW of a multipath channel is equal to 1/Td. Channel length is the length of deley intensity profile of a channel which is equal to Tm in analog digital (sampled) channels it is equal
the clock skew is defined by the arriving time difference between two DFF's clock edage. best regards what is the exact defination of clock skew related to digital /VLSI system?
NOT, NAND and NOR are the base of modern digital design. The reasons are: 1. NAND and NOR have smaller area than AND and OR 2. NAND and NOR are faster working 3. All of more dificult devices are built from theese elements. Look for any trigger.
The synthesizer doesn't support "wait for" because today's FPGAs and CPLDs don't contain hardware for implementing an arbitrary time delay. Instead, you can build a digital timer using sequential logic such as a counter. You can use "wait for" in your simulation test bench. Related info:
What is the meaning of this parameter setting? assume we set Trigger delay as 1ns. Does it mean that scope's trigger events will be seperated by 1ns, or it means that scope will show data 1ns after triggering events? One thing I observed is that scope update waveform very slowly, when I set Trigger delay to 1 second. Thanks, Neof
dear all : I design a all-digital dll now, I use inverter as delay cell, but when i simulate each stage of inverter , the delay time is different, even when the input different clock, the delay time is different, too. Can any help to solve it or tell how to simulate (...)
how to set the value for Vpulse in order to become a digital clock for a diffrential amplifier? v=3.3V lOW time = 3MS HIGHtime =3MS IF THERE IS RISE time, THEN SET THAT AS WELL.....
Hello all, I'm new in digital design for synthsis. My Manager asked me for a clock constraint diagram and input/output delay constraint diagram for my design. For the delay constraint diagram, I read in some ASIC book that it's related to time required for the input to be available after the clock edge, and for the (...)
Hi, What is the most efficent digital delay line out there?
is a depiction from Synopsys DC document. But I really can not understand why "min = min_path - hold". Let's think about the ideal case which the min_path equal to zero. In this case, the output_delay value is negative. Negative output_delay value means that the data could be change
You better read digital Design by John Rabaay , It seems it is a very basic question.
hi world! i am biulding a digital speed0meter where the pulses from the sensor will be detected and counteed by the counter. the number of pulses will then be multiplied to a constant number to convert it into the unit of speed and finally diplayed using 7-seg. well the question is how to do this multiplication that is pulses per sec * const. s
Raised Cosine pulse is the practical solution for baseband digital comm'n. But isn't raised cosine pulse non casual???
Dear ALL, In a digital circuit, when temperature increase, which component will introduce the most delay? inverter? or capacitor? or NMOS/ N-type BJT? or PMOS/ P-type BJT? Thanks rdgs tok
hi thankyou for reading my letter. please guide me to design currentcell for two LSB and six MSB? what is delay element in digital? the answer is inverter. dummy decoder? how suggest for design 14bit dac? thank you.
In number of digital communication system block diagram, I see a "delay" block. The block is supposed to delay the signal by, lets say Ts time. So how do I implement this block from circuit point of view? magnetra
All of are familiar with Propogation delay in digital circuits. But what is contamination delay and how does it occur? Any insights? Does contamination delay also play a part in the total delay of the circuit?
it depond on you process and topology of the digital. normal the logic delay should less than one clock , pay attention to the setup and hold time