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Dll Low Frequency

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6 Threads found on edaboard.com: Dll Low Frequency
You can use the internal PLL or dll in an FPGA (it will add some jitter) to generate your clocks. I don't like the XOR idea because you probably won't get a 50% duty cycle. If you use a counter, your clock edges won't be aligned due to propagation delay.
Restrictions are for clock frequency, not "data transfer rate". DDR3 RAM has a restricted clock frequency range depending on the timing settings. Review your datasheet. 100 MHz is most likely not possible. DDR3 RAM have an option to run with disabled dll at low clock speed for debugging purposes.
I don't think you can do that, as the low-frequency limit of the Spartan dll is 5 MHz. Why such a low clock frequency?
I'm studying about PLL and dll. But, I have no idea how to select between dll and PLL? dll is for low freqneucy? PLL is for high frequency? how? Please, let me know that.
PLL or dll?
The DCM and the BUFG do not really compare. They serve two different purposes. The DCM is a digital clock manager which is a fancy name for a dll or PLL. This is a complex block and shift clocks in phase, it can change the frequency of the input clock. A BUFG is just a global buffer that can connect to the low skew routing lines. (...)