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61 Threads found on edaboard.com: Dynamic Comparator
hello guys. I just have desined a SAR ADC with a 12-bit resolution and 1mhz sampling rate. but i find some problem with it : when i simulated the ENOB with it and i found the enob droped when the frequency of the input sinewave rises. can anyone tell me why this happens and how i can make it solved? thank you all!
Is there a design methodology one can follow to design a conventional dynamic comparator? 133900
I am designing a low power 100MHz SAR ADC ; but I can not find an accurate differential dynamic comparator for it. Non of the recently published structures work good. Would any one introduce me a proper structure? Thanks
Thanks all, I am using cadence. I mean the simulation method. Currently what I am thinking is DC voltage to one input, sawtooth waveform to another input, check comparator output. Next, increase DC voltage for both input and observe output till comparator not working (output no change). This mean that comparator already out of input (...)
Hi, I am desinging ADCs using cadence and I want to simulate the PSRR of dynamic comparator and ADCs. Anyone knows how to simulate PSRR of dynamic comparator and ADCs?
Pretty simple design. Precision OA peak detector with variable gain. Selected dynamic filter, amplitude controlled envelope to comparator. with PWM 1. fast attack , slow decay, 2. auto ,max peak and hold controlled brightness with slow attack and decay. 3.same as 1 except trigger advances MUX'd output on leading edge 4 differentiate
I am trying to simulate dynamic comparator in Candence, but getting working result I have attached circuit and result, can any one tell me where I am getting wrong.
hai all, I have designed a conventional dynamic and a double tail comparator in 180nm tecnology. To measure the offset voltage I did DC analysis by setting one of my input at .9V and other as a ramp signal of amplitude 1.8V. The clock frequency is 500 MHz and the supply voltage is 1.8V. I got the transient analysis as expected. But in the DC analys
how can we analyse kickback noise of dynamic comparator in cadence?? steps? how can we measure different types of noise in comparators?? how can we differentiate total noise from kickback noise component??
hello, i need a dynamic comparator IC . can u please name some kinds of it? thank you
Hi, Iam going to design a dynamic comparator for an Adc, 3 inputs, one for the input signal, one for the threshold voltage, and one clock and 2 differentials outputs, I would like to know how to simulate input offset in dynamic comparator Can I use a ramp for the input signal in transcient simulation , but how to (...)
Hello, I have a basic question, but it seems that i cannot find it's answer. Assuming we would have a dynamic latched comparator such as the one presented in Figure 2(a). How would you quantify the hysteresis of such a circuit (because of the latch) and add hysteresis?
I am designing a dynamic comparator as shown in figure. This circuit works as follows. When phi is 0, the voutn and voutp are held at vdd and when phi is 1, one of the side is pulled down and finally the cross coupled inverters settle to a stable state. Now I want to find static and dynamic resolution. I found the static resolution by (...)
Hi all Can anyone tell me how delaying of a clock in a dynamic comparator makes its performance better?? also How the offset is reduced in a dynamic comparator by delaying the clock???
Hi All, Can any one tell me or provide reference papers or book on how to characterize dynamic comparator using cadence
Can anyone let me know to calculate dynamic power & delay in tanner 13 ? And any schematics for Current comparators using CMOS logic?
Hello all; In pipeline ADCs where charge distribution dynamic comparators are used, the design of the different comparators is the same, they are only fed with different references to make them get exercised at different input voltage values.....When applying a ramp to the ADC each comparator exhibits a certain value of (...)
Dear Friends, I am going to simulate the kickback noise of a dynamic comparator. Can any of you help me what is the testbench of measuring kickback noise? Shall I use resistive ladder (similar to Flash ADCs) to see the effect of kickback ? are the value of resistances important in kickback? Thank you. Regards, Samaneh
Dear Friends, Recently I am going to perform a Transient noise analysis of a dynamic comparator. I have some questions: 1. How to set the parameters such as: noisefmax, noisefmin , noise scale , etc. 2. In output results how to draw the power density of noise at the output versus time? Now I do the simulations and in the output waveform of com
hI we are designing a 7 bit flash ADC using dual-tail dynamic comparator. our common mode ref voltage is 600mV. but our comparator is showing an offset of a few mV. is it due to kickback noise? how to remove it? the comparators at the top and bottom end (among 127 comparators) are working well. the (...)
Hi, I am a beginner for analog circuit design. I try to design a dynamic comparator, schematic shown in figure. Single supply voltage Vdd=1.8V, (Vcm=0.9V), 0.18um cmos technology(600MHz frequency). I have following question: 1. How to size ration nmos and pmos in this circuit? Any reply will be appreciated. Thank you very much! mohsen [AT
hi i am a beginner in analog circuit design.. I am designing a dynamic comparator for pipeline ADC in 90nm Cmos technology shown in the figure.. 1.8V supply voltage(Vcm=0.9V).. This dynamic comparator is to be designed for 2.5 bits flash sub-ADC.. I have several questions.. 1) How to choose the value of Vrn and Vrp? (...)
in dynamic comparator design of differential pair, i have some questions here. 65665fig1 is the schematic, fig2 is the design equation. d=ID5/ID6, e=Vin/Vref, W1=W2, W3=W4. but how to decide the value of ID5, ID6, d? because M5 and M6 are controled by clock signal Vclock, so the current of M5, M6 is difficult to set
Hi frds, recently i'm researching the offset of dynamic comparator, during the mc simulation with Hspice, I can't get the right results of MOS mismatch,could anyone tell me how to simulate the offset voltage of a dynamic regenerative latch comparator with Mont-carlo method? How to measure the offset during the simulation? (...)
1) use transient simulation 2) use dc sweep input voltage 3) dc sweep 4) quiescent current with dc sweep. transient simulation for dynamic power
Hi all, I'm using sense amplifier based comparator in my ADC.please post some reading materials explaining various aspects (and design)of comparator like dynamic offset,mismatch,parasitics,hysteresis etc., This is the
For this comparator, does it have latch? When I was designing this comparator, I found when the CLK=0, the output will directly change to 0, no matter what the input is, so I am wondering it does not have a latch to maintain the outp
The systematic offset of comparators/opamps are usually only in the uV range, but the random offset from MC analysis often shows it to be in the mV range. In other words, your typical simulation is not indicative of real offset. For dynamic comparators, you run your MC on transient simulation. It will just take a longer time.
in my project we have to design dual tail latch compaparator... i want something about dual tail latch operation
if you want to save power you should use dynamic comparator, but it can have really big offset ~100mV , and you will not be able to simulate all effects... problem is that offset is usually not constant and directlly affects on adc performances... comparator has to be much beter than 8 bits... if you want to achieve 8 bit adc resolution...
hi,there i have designed a comparator and the pre-amp is given in pic1.The top mos pair is working in triode region when the CLK signal is low and act as resistors.And the mos pair below the resistors are just switch to perform the dynamic compare. Recently I found there are some problems in my pre-amp. In the pic2,I found that the (...)
hi,there Recently I am designing comparator for a pipelined ADC. In the first stage which resolution is 4 bit,the subadc has a flashdc architecture with resistor string reference voltage divider.The comparator using in this subadc contains a static pre-amplifier followed by a dynamic-comparator which used in the latter (...)
Hi, Can i ask how to achieve the below specs for a latched comparator in cadence? Currently looking at the dynamic latched comparator topology. See attached picture. How do we size it? TSMC18 supply: VDD,GND resolution: Δvin < 1mV Operating freq: >1MHz Please help... Or any other topologies that will achieve the specs..
hi there, Does anyone know why is dynamic comparator (rather than preamp+latch) frequently used in pipeline ADC design? what is the advantage of it compared to other structures?
i am trying to simulate a fully differential dynamic comparator in 0.13um process, vdd=1.2v, when the threshold is zero i have only one error when the ramp is falling below the zero( threshold) attached is my simulation ; the ramp is the positive input,the purple line is the clock and the blue line is the positive output the clock switching th
Yes, you can latch the comparator earlier. Your output from your Sha at the time will not be as accurate, but since you are probably using redundancy, you can tolerate some error in your flash ADC. OR you can add a separate path for the your flash ADC. Sample the signal on the sha and for your flash adc at the same time in separate circuits.
in per stage 1.5bit pipelined ADC, dynamic comparator can be used to decrease power consumption; as we know , dynamic comparator has three types: resistive dynamic comparator, differential pair dynamic comparator and capacitive dynamic (...)
Hi, A question on offset calculation for a comparator. I have the preamp followed by dynamic latch type comparator for which i wuold like to calculate the offset . I have looked up the document on calculating offsets and seen the dc simulation, monte carlo methods for offset calculation. these rely on the parameter process mismatch (...)
1\when in spectre,i can use ocnPrint to convert wave to txt file.but there is another problem, when i simulate the circuit in background, i can't get the txt file as i can (not in always says nil.why? how to get the txt file in background simulation ? thanks. 2\how to simualte the offset of dynamic latched comparator? because the
in spectre,how to simulate voffset of dynamic latched comparator(built-in threshold)? is monte carlo analysis needed? if there is no offset,what is the value of vout+ and vout-?is it vdd/2 seperately? but when in simulation, i find that it is not vdd/2.why? pls help me.
i made simulations of dynamic latch comparator. i connected vin- and vref- to vdd/2. if vin+ is greater than vref+, output is high but when vref+ is greater than vin+, output does not stay on zero, it follows clock signal. How can a solve this problem???
Yes bubble error detection and correction is standard and helps to reduce static and dynamic accuracy requirements for the comparator stages. I did not have a number but some sources say that the area could be reduced by a factor 2 or more for the same yield spec by correcting one bubble errors. By the way the coding is straight binary and th
I am designing a dynamic comparator which is composed of a preamp and a latch, i.e. the attached figure. the input signal is differential and it is sampled and subtracts Vthreshold with a swithed capacitance circuit (omitted in the figure). the process i use is 0.18um, and the parameter Vth0=0.4. the question is: is this architecture approp
I am designing a comparator which allows +- 50mV offset, is the architecture attached here easy to achieve the specification? the process is 0.18um, and the power supply is 1.8V. thank you in advance!
could anybody please teach me: how to simulate the offset voltage of a dynamic regenerative latch comparator with Mont-carlo method??? looking forward to your help!!! thank a lot!!!
Friends, Herewith i have attched the circuit.... which is nothing but 2 dynamic comparator..both are identical. i want to build the first stage(sub ADC) of pipelined ADC.... can anyone tell me how do i make the connection??? how will i decide the vrefp and vrefn.... my FS voltage is 1v? Thanks
how to simulate the offset of dynamic latched comparator? the comp has one input,one threshold,two output(vout+ and vout-)
how to caculate the delay and dissipation of dynamic latched comparator in theory? because the current only exists in the beginning of the regeneration ,and variate with time ,so i'm confused about the caculation of the delay and dissipation of dynamic latched comparator in theory. pls help me.
this terminology is also used from power dissipation point of view. static comparators needs a dc current for its operation... but can be used as a continuous time comaprator. ie no need of a strobe signal. dynamic comparators does not require dc current... but this needs a strobe signal to latch the input. hope this helps fred
am not able to increase the gain of the pre-amplifier stage beyond 2V/V. is this gain sufficient for the design. gain is low because the load for M1 and M2 transisters are in trode region(according to the design). how can I design the dynamic latch.


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