Search Engine www.edaboard.com

Dynamic Latch Comparator

Add Question

15 Threads found on edaboard.com: Dynamic Latch Comparator
Hi frds, recently i'm researching the offset of dynamic comparator, during the mc simulation with Hspice, I can't get the right results of MOS mismatch,could anyone tell me how to simulate the offset voltage of a dynamic regenerative latch comparator with Mont-carlo method? How to measure the offset during (...)
For this comparator, does it have latch? When I was designing this comparator, I found when the CLK=0, the output will directly change to 0, no matter what the input is, so I am wondering it does not have a latch to maintain the outp
in my project we have to design dual tail latch compaparator... i want something about dual tail latch operation
hi there, Does anyone know why is dynamic comparator (rather than preamp+latch) frequently used in pipeline ADC design? what is the advantage of it compared to other structures?
i am trying to simulate a fully differential dynamic comparator in 0.13um process, vdd=1.2v, when the threshold is zero i have only one error when the ramp is falling below the zero( threshold) attached is my simulation ; the ramp is the positive input,the purple line is the clock and the blue line is the positive output the clock switching th
Yes, you can latch the comparator earlier. Your output from your Sha at the time will not be as accurate, but since you are probably using redundancy, you can tolerate some error in your flash ADC. OR you can add a separate path for the your flash ADC. Sample the signal on the sha and for your flash adc at the same time in separate circuits.
Hi, A question on offset calculation for a comparator. I have the preamp followed by dynamic latch type comparator for which i wuold like to calculate the offset . I have looked up the document on calculating offsets and seen the dc simulation, monte carlo methods for offset calculation. these rely on the parameter (...)
i made simulations of dynamic latch comparator. i connected vin- and vref- to vdd/2. if vin+ is greater than vref+, output is high but when vref+ is greater than vin+, output does not stay on zero, it follows clock signal. How can a solve this problem???
I am designing a dynamic comparator which is composed of a preamp and a latch, i.e. the attached figure. the input signal is differential and it is sampled and subtracts Vthreshold with a swithed capacitance circuit (omitted in the figure). the process i use is 0.18um, and the parameter Vth0=0.4. the question is: is this architecture (...)
could anybody please teach me: how to simulate the offset voltage of a dynamic regenerative latch comparator with Mont-carlo method??? looking forward to your help!!! thank a lot!!!
how to caculate the delay and dissipation of dynamic latched comparator in theory? because the current only exists in the beginning of the regeneration ,and variate with time ,so i'm confused about the caculation of the delay and dissipation of dynamic latched (...)
here the one i/p of comparator is fixed in static one.... in the case of dynamic it changes wrt o/p..... dynamic ones are generally done so improve their noise immunity......
am not able to increase the gain of the pre-amplifier stage beyond 2V/V. is this gain sufficient for the design. gain is low because the load for M1 and M2 transisters are in trode region(according to the design). how can I design the dynamic latch.
hi, I believe Vref+,- are decidec by application, or some external restrictions, not your circuit. They are inputs to your circuit. if you remove the most upper left PMOS, the most upper right PMOS, the most upper two NMOSs, there will be two inverters left. They form a latch up circuit. The sizes are up to the DC current, switching speed...
Hi, guys For the comparator with a dynamic latch, how to simulate it's gain? Thanks very much!