342 Threads found on edaboard.com: Dynamic Power
I am doing a custom design with Xilinx CPLD and xilinx FPGA. Now I am working with power requirements. I am using xilinx XC2C32A CPLD. I suppose to use 3.3V voltage as VCCIO and VCC=1.8V as voltage. But how can I get to know the maximum current rating for the corresponding voltages. What is meant by ICC(dynamic current) ?
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-28-2017 10:11 :: viyaaloth :: Replies: 1 :: Views: 300
power report from DC should have Total dynamic power ( switching power ) and Cell Leakage power ( Static ) separately.
ASIC Design Methodologies and Tools (Digital) :: 03-21-2017 03:56 :: slutarius :: Replies: 8 :: Views: 593
I am new to the tool Apache RedHawk. I set up power analysis for Static and dynamic (only vectorless) mode. But I am facing a strange problem. During Static analysis, I have values of wire & via voltage drops. But, during the dynamic analysis, I have no values for voltage drop maps.
ASIC Design Methodologies and Tools (Digital) :: 01-16-2017 11:56 :: tarjina :: Replies: 5 :: Views: 856
RF, Microwave, Antennas and Optics :: 12-30-2016 09:23 :: vfone :: Replies: 3 :: Views: 371
I will use the SCR like a diode between the capacitors and the load.
Sounds erroneous. A SCR can't switch-off DC current, at least not without a second commutating switch.
The problem of instantaneous current limiting refers to inherent limitations of a switched mode power supply in achieving current and voltage dynamic. Most mo
Power Electronics :: 12-20-2016 08:32 :: FvM :: Replies: 25 :: Views: 1809
Can you please guide how to find Peak power in Xilinx 13.2. I can find the leakage and dynamic power using Xilinx power Analyzer (XPA) with vcd file input. But could not find how to get the peak power?
In the previous versions the peak power was also available in XPA?
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-17-2016 13:17 :: sajjad.hussain :: Replies: 0 :: Views: 390
Is there a design methodology one can follow to design a conventional dynamic comparator? 133900
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-26-2016 22:07 :: qwerty99 :: Replies: 2 :: Views: 868
Each component has its own internal (core) current draw,
and also each of its outputs has some load on it. Both
vary with frequency of operation (you may see a dynamic
IDD spec, or you may not, depending on the part and its
In modern Big Digital parts like FPGAs and microprocessors
it is now common to see (say) 10A of current on
Elementary Electronic Questions :: 08-09-2016 03:14 :: dick_freebird :: Replies: 2 :: Views: 356
Separating GND kinds (power, analog, digital) is always welcome for signal integrity purpose, but how strict and how efficient necessary, it depend on design requirements, component specifications and dynamic aspects such as energy level involved and bandwidth of signals.
Analog Circuit Design :: 08-05-2016 14:38 :: andre_teprom :: Replies: 12 :: Views: 451
What voltage is available? +\-50?
Line output is usually 1Vrms and fixed , is that avail?
This will be a convenient power source and determine array configuration of 3.2V LEDs in ser/par.
What dynamic response do you expect? There are many kinds which can be smooth, logarithmic, fast attack, slow decay, glow intensity with voice speakers with f
Hobby Circuits and Small Projects Problems :: 07-15-2016 16:32 :: SunnySkyguy :: Replies: 160 :: Views: 6239
I know that the topic seem not suitable for this board due to it is more related to digital circuit.
But I think this topic could be simply as "How does the parasitic capacitance shrinks as process scale down? "
So, Those who good at design Analog circuit design must know(or care) device parasitic capacitance very well.
Analog Circuit Design :: 07-14-2016 12:54 :: Josephchiang :: Replies: 5 :: Views: 577
I have a HF transceiver (Input RF signal, Output audio signal). Please help me how to measure IP3 and Blocking dynamic Range!?
Thanks in advance
RF, Microwave, Antennas and Optics :: 07-07-2016 01:45 :: khungbopro :: Replies: 5 :: Views: 820
RapidIO and Time-Triggered Ethernet are used in many overlapping applications including Avionics. While TTEthernet has deterministic transfer delays, RapidiO provides extremely high data rates. Both standards provide significant flow control, priority based transfer, and virtual link mechanism. To select the right standard for the target applicatio
Business, Promotions, Advertising :: 06-13-2016 08:36 :: zeebri :: Replies: 0 :: Views: 399
It's most likely an estimate based on the SDC constraints for the clock and a 12.5% toggle rate of all FFs that use that clock. It's therefore likely to be very inaccurate, probably in excess of +/-30% off.
FPGA dynamic power analysis tools for both Altera and Xilinx do exactly this type of calculation and report that the results have very low acc
ASIC Design Methodologies and Tools (Digital) :: 06-02-2016 15:55 :: ads-ee :: Replies: 2 :: Views: 642
Many people use SAR ADC, some stick to delta-sigma and some like pipelined ADC
People decide between ADC techniques based on application parameters like resolution, sample rate, dynamic range, power consumption.
i want a quick answer with prose and cones
Without some ideas about your application and their requir
Analog Circuit Design :: 05-15-2016 12:10 :: FvM :: Replies: 3 :: Views: 442
I am designing a low power 100MHz SAR ADC ; but I can not find an accurate differential dynamic comparator for it. Non of the recently published structures work good. Would any one introduce me a proper structure?
Analog Circuit Design :: 05-06-2016 01:43 :: mahshidkardan :: Replies: 0 :: Views: 238
1)can someone please explain what is the X-transition power that i see in the power report?
2)Also i get that Total power= 5.045e-05 (100.00%) and i know that
power-specific unit information :
Voltage Units = 1 V
Capacitance Units = 1 pf
Time Units = 1 ns
ASIC Design Methodologies and Tools (Digital) :: 05-02-2016 11:40 :: draser :: Replies: 1 :: Views: 417
..Electronic loads cannot be used for much power supply testing because of the very significant capacitance they present.
Depends on the application requirements. If you are on the way with multi 100 kW power supply and energy storage systems, energy recuperation is a must. Some compromises regarding dynamic tester behavior may be
Power Electronics :: 05-01-2016 08:41 :: FvM :: Replies: 9 :: Views: 762
Can anyone post a script in Primetime that targets dynamic power other than fix_eco_power?
ASIC Design Methodologies and Tools (Digital) :: 04-26-2016 01:53 :: LamdaChi :: Replies: 0 :: Views: 491
I would not use linear technology linear power detectors I would use analog devices log power detectors. You will get another 30 dB of dynamic range, and the small levels will still be detectable due to the log detector transfer curve. use something like the AD8307
RF, Microwave, Antennas and Optics :: 04-18-2016 21:41 :: biff44 :: Replies: 36 :: Views: 5930
Did you set toggle rates for all the "inputs" (I'm assuming you mean pins). If nothing is toggling then there is no dynamic power being used.
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-04-2016 15:29 :: ads-ee :: Replies: 1 :: Views: 428
Can anyone explain what's the IDD current?
And what't the IDD power consumption?
How to test them?
So,what's the meaning of IDD ?dynamic power consumption or standby power consumption?
ASIC Design Methodologies and Tools (Digital) :: 03-28-2016 04:28 :: u24c02 :: Replies: 1 :: Views: 694
what is Xpower analyzer? What is SAIF file? What is dynamic power? what is the role of dynamic power and what are the factors involved in dynamic power change?
In Xilinx if I run the simulation for longer time duration I get a smaller value of (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-16-2015 18:16 :: QMA :: Replies: 3 :: Views: 716
The stability of any feedback system for voltage and current is challenging from no load to full load or dynamic non-linear loads, lab supplies with these features tend to be more complex. This is similar to the feedback gain going from 0 to
Service Manuals, Requests, Repair Tips :: 10-24-2015 19:41 :: SunnySkyguy :: Replies: 2 :: Views: 768
I would like to know which tools are nowadays available for dynamic power consumption calculation. I have access to cadence tools (not all of them, for example not Palladium).
Some "requirements", hoping that somebody has experience on the field:
- it is important to simulate under realistic conditions (e.g. I know that I can import v
ASIC Design Methodologies and Tools (Digital) :: 10-06-2015 10:29 :: smarconi :: Replies: 4 :: Views: 618
I have some data for the dynamic power of an ASIC for a given workload. These measurements go through a range of voltages (all other factors are constant, like frequency, etc). Is it possible to develop a model to fit this set of data with the traditional formulae used for switching and short circuit power, i.e:
P = (...)
ASIC Design Methodologies and Tools (Digital) :: 09-22-2015 03:10 :: czhe :: Replies: 0 :: Views: 581
So I have this 9V 2.5A power supply and a flash unit which needs 6V. I use LM7806 to drop voltage, but when the flash is charging up it overload regulator, thus further dropping voltage to megger 2.5V. I think I need to somehow limit max current draw to 1.5A. Surprisingly I couldn't find a solution in google, so maybe you guys can help me out?
Hobby Circuits and Small Projects Problems :: 09-17-2015 20:19 :: HagenK :: Replies: 1 :: Views: 546
It depends on your load regulation spec. If you need dynamic load regulation noise to be < 1% then the series R must be <1% of the change in load R.
For effective filtering the ripple is the Step current * Source ESR including cap parallel.
Ultra low ESR Caps can be expensive depending on ripple current and voltage.
What are your spe
Analog Circuit Design :: 09-10-2015 02:25 :: SunnySkyguy :: Replies: 5 :: Views: 585
Is there a way that I can measure dynamic power variance and leakage power variance separately for a given FinFET based circuit?
Analog Circuit Design :: 08-26-2015 15:26 :: Lijitha Vegi :: Replies: 2 :: Views: 626
It depends on your power budget for conduction loss on diode vs dynamic loss during recovery. Often dynamic losses exceed conduction losses forcing designers with 100kW SMPS to use very expensive HV low Trr parts to get 98% efficiency.
Power Electronics :: 08-22-2015 16:12 :: SunnySkyguy :: Replies: 7 :: Views: 652
which are the reports generated in voltus for observing peak power consumption?
thanx in advance
ASIC Design Methodologies and Tools (Digital) :: 08-13-2015 13:58 :: argha :: Replies: 0 :: Views: 457
If you've got the output of one opamp driving the EXTREMELY HIGH INPUT IMPEDANCE of the next op amp, how much current does that output need to supply? Just about nothing, dynamic or otherwise. If you've got feedback resistors, those will also draw some current, as will capacitors (dynamically!). Without seeing a schematic there's no way we can pr
Analog Circuit Design :: 08-06-2015 21:52 :: barry :: Replies: 2 :: Views: 575
I do not think so. Poynting vector is used with Maxwell Elecromagnetic theory on dynamic power transfer by EM alternating field. Static DC fields do not transmit any energy, so no Poynting applies.
DC fields do NOT transmit any waves as they are static. There is no link between electric and magnetic field when the field is not changing.
RF, Microwave, Antennas and Optics :: 07-29-2015 14:52 :: jiripolivka :: Replies: 1 :: Views: 314
Can you offer the battery type and backlight current in your design details?
I would hope you designed it for low power consumption such as 3V and use 3.7V LiPo but not sure of LCD requirements.
dynamic power is affected by clock frequency.
Microcontrollers :: 07-27-2015 21:42 :: SunnySkyguy :: Replies: 81 :: Views: 4404
I am trying do the noise margin analysis of a dynamic CMOS logic circuit (Domino) which is run by a clock signal. Now, what should be the procedure to do that? I am trying to follow something similar to standard method of measuring noise margin for an inverter using VTC curve.
Thank you for your time and co-operation!
Analog Circuit Design :: 07-16-2015 21:00 :: sazjad :: Replies: 1 :: Views: 472
You are wiser to use 2 transducers in simplex mode that try to share 1 in half-duplex mode due to wide dynamic range disparity in power levels at transition time.
Analog Circuit Design :: 07-10-2015 16:26 :: SunnySkyguy :: Replies: 1 :: Views: 645
Why dynamic power after compilation equal to zero, any idea how can I calculate dynamic power at max freq in Quartus?
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-09-2015 12:49 :: abd_elhamid_ :: Replies: 1 :: Views: 401
I am looking for an smd version or equivalent of the 2n5109.
It will be used in an HF preamplifier with high dynamic range, because this is a power transistor.
RF, Microwave, Antennas and Optics :: 07-04-2015 00:12 :: neazoi :: Replies: 0 :: Views: 1045
i have written a hspice code for d flipflop and i want to calculate the delay of the circuit i.e. high to low and low to high propagation delay but my code is running but not able to give the values of delay
* Parameters and models
Software Problems, Hints and Reviews :: 06-26-2015 04:16 :: Upadhyay Prachi :: Replies: 0 :: Views: 982
If I am using VoltageStorm for IR drop ( both static and dynamic) analysis at the internal block levels of a chip, and a top level chip integrator (will be integrating into a package with I/O and alos dropping in a power mesh at the too) will be using RedHawk, will the power model generated by Voltage storm be compatible with Redhawk? (...)
ASIC Design Methodologies and Tools (Digital) :: 06-17-2015 18:40 :: moulirama :: Replies: 0 :: Views: 869
Both: dynamic and leakage. Of course, it is useful if power optimization was swithed on during synthesis.
ASIC Design Methodologies and Tools (Digital) :: 06-13-2015 17:51 :: oratie :: Replies: 5 :: Views: 790
I want to help me to use the benchmark circuits in my work for power calculations ( dynamic and static). how can modify the benchmark to meet my design? and how can I obtain the final hspice netlist to simulate the modified circuit?
ASIC Design Methodologies and Tools (Digital) :: 06-02-2015 08:34 :: Shakir_mano :: Replies: 0 :: Views: 352
When the Rf power signal is applied to the Schottky diode,the dynamic resistance changes. It sometimes increases and then again decreases. I want to know why the dynamic resistance changes on increasing the RF power supply? Please help me. What is the relation of power signal with the (...)
Elementary Electronic Questions :: 05-11-2015 06:39 :: bhatt_190487 :: Replies: 3 :: Views: 607
This camera kit has 2 parts: STM32F103RB main board and a OV7725 high speed CMOS camera sensor module. With this kit any one with a little electronics knowledge can make a camera in a few minutes. Just plug-in the camera module on the main board, power the board by USB cable or external power supply, the dynamic video will appears on the (...)
Business, Promotions, Advertising :: 04-29-2015 07:29 :: EzPCB-Nila :: Replies: 0 :: Views: 744
As a simple charge reservoir, you would like the supply
voltage to remain in spec (+/-5%) without demanding
that the charge taken by switching events be put back
instantaneously by the remote source (it can't).
If you took the dynamic Idd (less static) at the clock
rate the spec is tied to, you could calculate a charge
slug per clock (rememberin
Elementary Electronic Questions :: 03-12-2015 00:09 :: dick_freebird :: Replies: 2 :: Views: 1348
Every time a signal (clk) changes state, current is required to charge parasitic capacitances (I=C*dv/dt). If there's no change in signal level, no current is drawn. This is called dynamic current, as opposed to static, or idle, current. A clock is continuous, a latch control is not.
ASIC Design Methodologies and Tools (Digital) :: 03-11-2015 23:39 :: barry :: Replies: 3 :: Views: 555
I am modelling the nonlinear diode in ADS to get the characteristics of Agilent's 5082 -2800 Schottky Diode. I am getting I-V curve but when I apply RF power signal to the diode , the RF resistance is not changing . The dynamic resistance remains constant with the increasing input power. Please help me out to solve the problem. My model (...)
Software Problems, Hints and Reviews :: 03-05-2015 04:55 :: bhatt_190487 :: Replies: 7 :: Views: 1326
I would like to know how a dynamic power depends upon the Load capacitance? If this is so then Please let me know how the dynamic power is reduced due to less loading effect in Pseudo NMOS logic.
Does Load capacitance depends upon the NMOS transistors? If this is so then it would be correct, but if it (...)
ASIC Design Methodologies and Tools (Digital) :: 01-22-2015 07:59 :: mujju433 :: Replies: 2 :: Views: 588
I want to calculate dynamic power dissipation of 6T SRAM cell using HSPICE.
Hi oly ;-)
use the usual procedure: run a transient analysis with either read or write (or both mixed) cycles at your required frequency for many (10..100) cycles, measure the integrated (or medium) current consumption and from that c
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-27-2014 19:39 :: erikl :: Replies: 1 :: Views: 1090
I'm working with the BSIM-CMG (version 108) from Berkelery university using the PTM modelcards from ASU to simulate multigate transistors and I have a couple questions that probably somebody have come across.
First, in the BSIM-CMG model there is a parameter called GEOMOD, which allows to select double, triple(FinFET) an quadruple gates
Analog Circuit Design :: 11-18-2014 23:56 :: gtaice :: Replies: 0 :: Views: 990