1000 Threads found on edaboard.com: Elastic Buffer
What are elastic buffers, how can i design an elastic buffer?
ASIC Design Methodologies and Tools (Digital) :: 01-07-2005 04:34 :: gold_kiss :: Replies: 3 :: Views: 8395
I want to implement E1 framer using vhdl.Now after receiving the frame I am storing the frame in an asynchronous fifo,as I have to write the data using E1 clk and read the data using system clk.Here I am getting timing some datasheet I have seen that they are using elastic buffer.Can some one please explain me what is ela
Professional Hardware and Electronics Design :: 03-12-2008 00:53 :: anuradha_vxl :: Replies: 0 :: Views: 1760
Hi , I need some good documents about implementation of elastic buffer / 8b/10b encoder - decoder . It will be great if you could point me to relevant stuffs of these topics.
Thanks in advance , Niraj
ASIC Design Methodologies and Tools (Digital) :: 05-28-2010 15:25 :: niraj_m :: Replies: 0 :: Views: 1349
I am currently working on USB 3.0. I have finished some of the modules in the receiver, However I have stuck up in designing the elastic buffer of the type Full Empty.
Please guide me in knowing the design for the same. Your help would be much appreciated.
ASIC Design Methodologies and Tools (Digital) :: 04-30-2012 05:21 :: shyam1285 :: Replies: 2 :: Views: 1144
Need help in understanding how to design USB3 Rx elastic buffer
ASIC Design Methodologies and Tools (Digital) :: 08-16-2012 13:39 :: dftrtl :: Replies: 0 :: Views: 539
The elastic buffer is a buffer for which u need to write the received data using the recovered RX clock and the read from this buffer should be on the RX lock clock. You need elastic buffers as a method for clock skew tolerance. Max value of which can be 600ppm.
I think you can get (...)
ASIC Design Methodologies and Tools (Digital) :: 12-23-2004 02:47 :: gold_kiss :: Replies: 1 :: Views: 2226
I wanna ask a question about the design of USB2.0 Phy. We know that the USB Phy can sample the 480Mb/s (high speed mode) and the 12Mb/s (full speed mode) serial data using two CDR circuits, and the the recoverred data rate has not been changed out of the CDR circuits. Then the 480Mb/s data flow into the elastic buffer
ASIC Design Methodologies and Tools (Digital) :: 03-18-2007 00:35 :: Thomson :: Replies: 3 :: Views: 6744
I need the buffer IC to connect two difference voltage level device.One is altera CPLD Max3256 (3.3 Voltage),the other is Digital Input Output Card(5 Voltage).
I had tried the logic IC ,such as 7404,74244,and 74245.
My design works at 20MHz,AND the test result is not good.
I think the current of the buffer drive IC is not high
Professional Hardware and Electronics Design :: 07-24-2002 11:09 :: cssheu :: Replies: 4 :: Views: 1903
I need help for output dac 0-10v and 4-20ma
Professional Hardware and Electronics Design :: 12-26-2002 05:03 :: LIVIU :: Replies: 6 :: Views: 2221
When Synopsys says a signal is buffered (such as the clock), what is added to the net?
Is the buffer a pair of inverters? Any other structures?
ASIC Design Methodologies and Tools (Digital) :: 01-24-2003 10:46 :: asicer :: Replies: 16 :: Views: 3159
Why we need to add input buffer for amplifier?
Is that for impedance matching and level shifting? I want to make sure that I am not missing anything important.
Can any one introduce some good document for me on that topic?
RF, Microwave, Antennas and Optics :: 07-22-2003 19:31 :: mike_bihan :: Replies: 8 :: Views: 2615
I know thar usualy when data is being transmitted into a comm channel, is stored previously into a buffer.
Now, I wonder that how can I program that ?
PC Programming and Interfacing :: 10-25-2003 16:48 :: Bukitoo :: Replies: 3 :: Views: 1440
The buffer of d2a circuit need to provide swing capability. The buffer was actually a 2 stage OP-Amp, with unity gain feedback.
The first stage was very typical differential N-pair with Pmos current mirror load. The 2nd stage was a little wierd.
It is consists of one push-pull stage with a current source. The circuit structure was attached in
Analog IC Design and Layout :: 01-11-2004 20:13 :: mike_bihan :: Replies: 8 :: Views: 2576
I am synthezing my design for Xilinx device. I find that one of my input signal which is not a clock is being through the global clk buffer. How can I force the synthesis tool to not use the clk buffer for this input.
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-16-2004 14:45 :: efundas :: Replies: 5 :: Views: 1276
I'd like to transfer a file of 4MB from the host (computer) to one buffer of the target (TMS320C6711 Board) in order to read it after.
Can it be done ? (I know that the RAM memory of this board is 16MB)
And if yes, do you know any example of algorithm ?
Thanks very much for Help.
Digital Signal Processing :: 01-27-2004 06:10 :: leboutdumonde :: Replies: 1 :: Views: 1305
RF, Microwave, Antennas and Optics :: 02-19-2004 07:26 :: microstrip_line :: Replies: 10 :: Views: 2093
Is it recommendable to use a MAX7000AE CPLD for databus buffer in a design?
Want to implement simple pc-card controller for a coldfire CPU (50MHz) and since I need some internal registers to be read/writable anyway I want also to include the databus on the pc-card side...
Or better to stay with normal logic family for it?
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-20-2004 06:56 :: davorin :: Replies: 2 :: Views: 920
I need design high speed DAC (like RAMDAC --> 200Mhz )
and I need a high speed buffer ..
who can tell me where can I find paper or any good analog book
allens books have highspeed OPA but I think I need high speed
buffer (BW > 200MHz)
Analog IC Design and Layout :: 03-03-2004 18:45 :: andy2000a :: Replies: 1 :: Views: 1005
There are various ways by which you can avoid any kind of disasterous results in your hardware due to multiple clock domain. Few way to address such design are
1) We can have a buffer or fifo inbetween these 2 clock domains. So incase if on one clock read happens the there clock write can take place. But the depth of the fifo is an issue and
ASIC Design Methodologies and Tools (Digital) :: 03-17-2004 09:51 :: gold_kiss :: Replies: 8 :: Views: 2068
My circuit need a driving buffer because it not drive a larger capacitive load, it need to drive a 400f F capacitive load with 2.4GHz frequency,
because frequency is very high, so structure of buffer need as simple as possible, please gvie me a design scheme.
RF, Microwave, Antennas and Optics :: 04-01-2004 04:56 :: fallangel :: Replies: 0 :: Views: 599
Is there any buffer memeory available on XC4010 IC.
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-23-2004 13:18 :: Usman Hai :: Replies: 1 :: Views: 694
How can I decide whether to insert a buffer or upsize the cell during delay optimization? Anyone knows the algorithms used in modern EDA tools?
ASIC Design Methodologies and Tools (Digital) :: 04-29-2004 22:31 :: goodhope :: Replies: 5 :: Views: 1845
I met a problem about the differential delay buffer, which uses for Ring VCO. The structure of the buffer is just as the figure.
From the paper--R.J. Betancourt-Zamora, T.H. Lee, ?CMOS VCOs for Frequency Synthesis in Wireless Biotelemetry?, Int?l Symp. Low Power Electronics & Design, pp. 91-93, August 1998.--I know the (...)
Analog Circuit Design :: 05-27-2004 09:23 :: flyinspace :: Replies: 6 :: Views: 2032
I want to used Reset IC and Video buffer in my application .please recommend these IC for me.thanks you very much!
Hobby Circuits and Small Projects Problems :: 08-13-2004 02:15 :: fyjin :: Replies: 1 :: Views: 837
If we just want input port only connecting with one cell in the design,then this cell maybe drives a lot of cells.How to add constrain when synthesissing in PKS?
ASIC Design Methodologies and Tools (Digital) :: 08-20-2004 03:11 :: kermit :: Replies: 2 :: Views: 640
When I use Cadence's spectraquest to simulate one circuit topology include only one driver and one reciever,I found that the results include
buffer delay. It seems that this buffer means the buffer in the driver. In the waveform results, I can see the "buffdly" waveform. Can anybody tell me why exist buffer delay and the (...)
PCB Routing Schematic Layout software and Simulation :: 08-26-2004 04:01 :: redtide :: Replies: 0 :: Views: 742
what is the concept of zero delay buffer ?
for what purpose it is used and what is the logic ?
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-07-2004 05:40 :: jay_ec_engg :: Replies: 5 :: Views: 1537
Hi dear friends
what is difference between buffer and signal and register and bus in vhdl?
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-08-2004 08:19 :: ahmadagha23 :: Replies: 2 :: Views: 1679
In designing analog buffer, is it better to use one stage or two stage amplifer ? I think two stage amplifier is better, because it can provide
higher gain and output almost equal to input in unity gain configuration.
Am i right?
Analog Circuit Design :: 09-15-2004 03:51 :: surianova :: Replies: 14 :: Views: 1663
Anyone help with this, not very good at C yet. What I have is an AT89s8252 programmed with k**l and tiny rtos. I have one task that that sits and uses _getkey and assigns it to an 8 bit int global variable. This variable is then read by another task that processes it if > 0. The problem I have is that if more than one number is received in a period
Microcontrollers :: 11-10-2004 08:37 :: GrandAlf :: Replies: 3 :: Views: 8108
What circuit topology is usually used to design good input buffer for driving 1)capacitance 2) passive S/H? Source follower or Unity-gain diff-amp? And how to size the transistors so a low output distortion is obtained.
Analog Circuit Design :: 11-10-2004 23:26 :: ccw27 :: Replies: 2 :: Views: 893
I found a sentence " The Op Amp has high input impedance, this mean that its input are buffered". As far as I know, buffer means large current, but high input impedence means little current, am I right?
Electronic Elementary Questions :: 11-13-2004 11:31 :: davyzhu :: Replies: 3 :: Views: 740
Now I design differential Ring OSC 170Mhz,
but I don't know how to design buffer to pad .
I try to use Inverter for testing buffer , but when add package model
it will ringing , so somebody can help me ?
RF, Microwave, Antennas and Optics :: 11-29-2004 23:40 :: super :: Replies: 1 :: Views: 565
I am reading the book "Reuse Methodology Manual for SOC Designs". It is mentioned in the book that a RESET signal needs a buffer tree just like the clock signal does. I think the RESET does need a buffer tree. But how? Did anyone have done the "RESET tree synthesis" or something like this in practical? Which EDA tools can do this job? I will be ver
ASIC Design Methodologies and Tools (Digital) :: 11-30-2004 07:52 :: monsoom :: Replies: 33 :: Views: 4675
I have designed a crosscoupled LC oscillator as shown in the following picture which operates at 1.8GHz, in 3V supply voltage and has a sinusoidal peak to peak voltage swing of 2V. My question concerns the output buffer that follows the oscillator core.
What kind of buffer should I use in order to have a 50 Ohm termination?
Will the larg
Analog Circuit Design :: 12-02-2004 09:25 :: tromeros :: Replies: 1 :: Views: 1932
Just want to confirm the way we measure the bandwidth for a buffer.
For buffer, the gain is normally almost 0 dB. Is it correct we measure
the bandwidth as 0-3dB= -3 dB. The frequency at gain -3dB is the
bandwidth, is it corerct?
Analog Circuit Design :: 12-09-2004 21:06 :: surianova :: Replies: 4 :: Views: 704
Dear all :
I have question about unit gain buffer.
There are three type op.
1. General 2 to 1 op
2. telescopic op
3. folded cascode op
if I connect these op to unit gain buffer ,
what's the different both of them ?
Analog Circuit Design :: 01-01-2005 03:37 :: super :: Replies: 3 :: Views: 1048
Is some body explain me about functionality of I/O buffer Pad
ASIC Design Methodologies and Tools (Digital) :: 01-26-2005 07:42 :: spauls :: Replies: 0 :: Views: 799
If I want to design an inverter buffer to drive a 1pF capacitance. What is the minimum fan-out of the inverter to make the output waveform ok if don't consider the speed. how to calculate the needed fanout? or do it by simulation?
Added after 3 minutes:
is it usually the minimum fanout should be 1?
ASIC Design Methodologies and Tools (Digital) :: 02-01-2005 23:25 :: triquent :: Replies: 7 :: Views: 1457
is there any buffer that provide the best unity gain? for S/H circuit say 20Mhz sampling rate?
Analog Circuit Design :: 02-02-2005 18:59 :: ug02048 :: Replies: 8 :: Views: 1838
can you ppl tell me the similarity or difference in Analog & Digital buffer on the basis of their function.i'm confused coz sometims i read buffers can be used for amplification of signal on the other hand some says it can be used to add delays in clocks.
ASIC Design Methodologies and Tools (Digital) :: 02-05-2005 00:02 :: smith_kang :: Replies: 3 :: Views: 3519
Why do we use buffer After Parallel port and before our circuit..
and m going to interface my all 8 parallel bits .. which buffer Ic will be best.. thanks
PC Programming and Interfacing :: 02-18-2005 02:57 :: Compy :: Replies: 7 :: Views: 2537
ie what is the gain typically ?
output resistance etc
Analog IC Design and Layout :: 03-01-2005 18:11 :: ug02048 :: Replies: 4 :: Views: 919
why do v need a buffer for bidirectional bus alone and not for unidirectional bus?
Digital Signal Processing :: 03-05-2005 07:43 :: karthy :: Replies: 1 :: Views: 752
I need to design a buffer for the sample and hold circuit with unit gain< 10Mhz
any sort of buffer
Any help is appreciated
Analog IC Design and Layout :: 03-08-2005 10:48 :: ug02048 :: Replies: 1 :: Views: 888
how to design a cmos buffer using simply inverters.Are there any rules to size the MOS-FET?
can anybody guide me to some materials about this topic.
Thx in advance.
Analog Circuit Design :: 04-06-2005 23:22 :: marlboro_x :: Replies: 12 :: Views: 6982
I want to insert several buffer in order to delay a signal, about 2ns at least, but 3ns at most.
After I insert buffers, and do STA, the delay at best case is 2.01ns, but reach 4ns at worst case , more than 3ns :-(
So anyone can help me how to insert delay, that can meet timing at both best case and worst case.
I dont know whether some special
ASIC Design Methodologies and Tools (Digital) :: 04-12-2005 03:27 :: tavidu :: Replies: 9 :: Views: 1991
I am designing a PLL and I need to design a buffer to isolate the LPF and the conrol voltage into my MOSCAPs. How can I design a buffer in CMOS, I have been told not to use a regular source follower at high frequency, but a common source with an inductive this it, or is there also a resistor at the drain? Thank you
RF, Microwave, Antennas and Optics :: 04-22-2005 07:45 :: jayxman51 :: Replies: 1 :: Views: 955
I want design a buffer 8 input(?20V) 8 output(?10V),GAIN=0.5.Which IC can I use?
Analog Circuit Design :: 04-28-2005 11:03 :: adek :: Replies: 8 :: Views: 1122
If I want to measure the bandgap voltage is it necessary to build a buffer before connecting it to a pad? Seems like I don't need one since it is just a DC value.
Analog IC Design and Layout :: 04-29-2005 05:47 :: ccw27 :: Replies: 4 :: Views: 701