9 Threads found on edaboard.com: Elastic Buffer
What are elastic buffers, how can i design an elastic buffer?
ASIC Design Methodologies and Tools (Digital) :: 07.01.2005 04:34 :: gold_kiss :: Replies: 3 :: Views: 7936
I want to implement E1 framer using vhdl.Now after receiving the frame I am storing the frame in an asynchronous fifo,as I have to write the data using E1 clk and read the data using system clk.Here I am getting timing some datasheet I have seen that they are using elastic buffer.Can some one please explain me what is ela
Professional Hardware and Electronics Design :: 12.03.2008 00:53 :: anuradha_vxl :: Replies: 0 :: Views: 1718
Hi , I need some good documents about implementation of elastic buffer / 8b/10b encoder - decoder . It will be great if you could point me to relevant stuffs of these topics.
Thanks in advance , Niraj
ASIC Design Methodologies and Tools (Digital) :: 28.05.2010 15:25 :: niraj_m :: Replies: 0 :: Views: 1284
I am currently working on USB 3.0. I have finished some of the modules in the receiver, However I have stuck up in designing the elastic buffer of the type Full Empty.
Please guide me in knowing the design for the same. Your help would be much appreciated.
ASIC Design Methodologies and Tools (Digital) :: 30.04.2012 05:21 :: shyam1285 :: Replies: 2 :: Views: 912
Need help in understanding how to design USB3 Rx elastic buffer
ASIC Design Methodologies and Tools (Digital) :: 16.08.2012 13:39 :: dftrtl :: Replies: 0 :: Views: 502
The elastic buffer is a buffer for which u need to write the received data using the recovered RX clock and the read from this buffer should be on the RX lock clock. You need elastic buffers as a method for clock skew tolerance. Max value of which can be 600ppm.
I think you can get (...)
ASIC Design Methodologies and Tools (Digital) :: 23.12.2004 02:47 :: gold_kiss :: Replies: 1 :: Views: 2123
I wanna ask a question about the design of USB2.0 Phy. We know that the USB Phy can sample the 480Mb/s (high speed mode) and the 12Mb/s (full speed mode) serial data using two CDR circuits, and the the recoverred data rate has not been changed out of the CDR circuits. Then the 480Mb/s data flow into the elastic buffer
ASIC Design Methodologies and Tools (Digital) :: 18.03.2007 00:35 :: Thomson :: Replies: 3 :: Views: 6252
There are various ways by which you can avoid any kind of disasterous results in your hardware due to multiple clock domain. Few way to address such design are
1) We can have a buffer or fifo inbetween these 2 clock domains. So incase if on one clock read happens the there clock write can take place. But the depth of the fifo is an issue and
ASIC Design Methodologies and Tools (Digital) :: 17.03.2004 09:51 :: gold_kiss :: Replies: 8 :: Views: 2025
A FIFO (first-in-first-out) buffer is an ?elastic? storage between two subsystems, as shown in the conceptual diagram of Figure 1. It has two control signals, w r and rd,for write and read operations. When w r is asserted, the input data is written into the buffer. The read operation is somewhat misleading. The (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 14.11.2008 12:21 :: user1111 :: Replies: 1 :: Views: 841