13 Threads found on edaboard.com: Elastic Buffer
What are elastic buffers, how can i design an elastic buffer?
ASIC Design Methodologies and Tools (Digital) :: 07.01.2005 10:34 :: gold_kiss :: Replies: 3 :: Views: 5758
I want to implement E1 framer using vhdl.Now after receiving the frame I am storing the frame in an asynchronous fifo,as I have to write the data using E1 clk and read the data using system clk.Here I am getting timing some datasheet I have seen that they are using elastic buffer.Can some one please explain me what is ela
Professional Hardware and Electronics Design :: 12.03.2008 05:53 :: anuradha_vxl :: Replies: 0 :: Views: 1473
Hi , I need some good documents about implementation of elastic buffer / 8b/10b encoder - decoder . It will be great if you could point me to relevant stuffs of these topics.
Thanks in advance , Niraj
ASIC Design Methodologies and Tools (Digital) :: 28.05.2010 21:25 :: niraj_m :: Replies: 0 :: Views: 964
I am currently working on USB 3.0. I have finished some of the modules in the receiver, However I have stuck up in designing the elastic buffer of the type Full Empty.
Please guide me in knowing the design for the same. Your help would be much appreciated.
ASIC Design Methodologies and Tools (Digital) :: 30.04.2012 11:21 :: shyam1285 :: Replies: 2 :: Views: 379
Need help in understanding how to design USB3 Rx elastic buffer
ASIC Design Methodologies and Tools (Digital) :: 16.08.2012 19:39 :: dftrtl :: Replies: 0 :: Views: 235
The elastic buffer is a buffer for which u need to write the received data using the recovered RX clock and the read from this buffer should be on the RX lock clock. You need elastic buffers as a method for clock skew tolerance. Max value of which can be 600ppm.
I think you can get (...)
ASIC Design Methodologies and Tools (Digital) :: 23.12.2004 08:47 :: gold_kiss :: Replies: 1 :: Views: 1414
It is often the case in data communication that two systems on both side have similar clock frequency with small offset.
One way to overcome this problem is by nyquist sampling and introduce a circuitry called "elastic buffer" or "elasticity buffer" to obsorb those 'extra' or 'missing' chips.
Another way to do (...)
Analog IC Design and Layout :: 09.03.2005 13:55 :: wencent :: Replies: 6 :: Views: 931
Well, as I said for a buffer, a 'FIFO' (first in first out) sort of thing. Its basically (correct me of I'm wrong people) and elastic buffer. Say you have 20 registers set aside, named, temp1- temp20 for exmaple, every time you get data coming in from your serial port (the micro will take care of this on its own if set up (...)
Microcontrollers :: 16.05.2005 06:33 :: Buriedcode :: Replies: 3 :: Views: 882
I wanna ask a question about the design of USB2.0 Phy. We know that the USB Phy can sample the 480Mb/s (high speed mode) and the 12Mb/s (full speed mode) serial data using two CDR circuits, and the the recoverred data rate has not been changed out of the CDR circuits. Then the 480Mb/s data flow into the elastic buffer
ASIC Design Methodologies and Tools (Digital) :: 18.03.2007 05:35 :: Thomson :: Replies: 3 :: Views: 2611
You are right, I actually meant that all recent 1GBit copper implementations are 1000BASE-T.
you can connect 1000 Base-x and 1000 Base-t via GMII interface. this sentence says that u need a converter for the same.
In fact both sides need a converter which is represented by the respective PHY. An elastic buffer may be required for
PLD, SPLD, GAL, CPLD, FPGA Design :: 23.02.2012 16:56 :: FvM :: Replies: 9 :: Views: 733
There are various ways by which you can avoid any kind of disasterous results in your hardware due to multiple clock domain. Few way to address such design are
1) We can have a buffer or fifo inbetween these 2 clock domains. So incase if on one clock read happens the there clock write can take place. But the depth of the fifo is an issue and
ASIC Design Methodologies and Tools (Digital) :: 17.03.2004 15:51 :: gold_kiss :: Replies: 8 :: Views: 1753
A FIFO (first-in-first-out) buffer is an ?elastic? storage between two subsystems, as shown in the conceptual diagram of Figure 1. It has two control signals, w r and rd,for write and read operations. When w r is asserted, the input data is written into the buffer. The read operation is somewhat misleading. The (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 14.11.2008 18:21 :: user1111 :: Replies: 1 :: Views: 730
70 db comes from either the rhode or wenzel circuit--I forget which one. Obviously, you only need enough feedback control loop gain to degernate the 1/f noise, and any extra just causes trouble.
That's about right - the DC current loop gain of a resistor-biased transistor with a beta of 100 is already 40-dB![COLOR="S
RF, Microwave, Antennas and Optics :: 26.01.2011 17:13 :: stromer :: Replies: 110 :: Views: 16460