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36 Threads found on edaboard.com: Error Lef
During post-route timing optimization in Encounter, I get the error message, "Power/Ground pin is floating!". What does this error message mean? Verify -> Geometry reports no violations. I also ran the following command, "globalNetConnect VDD -pin VDD -inst * -type pgpin -all -override" (and same for GND) before special route of the power rings. Th
Hi all, I am loading a design in innovus by following commands and it is working fine source xyz.globals init_design but when i do it in older version of encounter while readding tech lef the below error messages are coming.i need a fix to this problem, Loading lef file pqrs.lef... error (...)
Hi, when i am trying to use generatelef command from encounter to get lef from a file,the tool is crashing and exiting. here is the below error log. generatelef -techFile saed.lef Reading ATF ... Unsupported capacitance unit name: ff ATF db unit = 1000 line 403: parse error at 'l
Hi i am unable to do design optimization in cadence encounter, i am getting an error regarding that the timing library is not included. During design import i add the following files 1) synthesized (.v) file 2) lef file 3) timing constraint file (.sdc) that got from synopsys. I do have the timing lib file (.lib) to include for timing constra
Hello, I want to use QRC for extraction of a digital design. I saved .def file from soc encounter, and plan to extract rc. But I got such an error that it seems I can only use lef or libgen. But I think DEF should be fine for extraction. Is there anything wrong ? 127905 Here is my command file. I lunched the qrc
Hi, I am using Cadence SoC Encounter. While loading the lef files I am getting the following error: ENCSYT - 16013 Load lef file sc12_tech.lef sc12_cmos28lpp_base_rvt.lef failed As, you can see I am first loading the technology lef having the specifications for POLY, (...)
Hi All, I plan to do a fabrication in a digital design technology for the first time( I have only experience in analog before). When I am done with my design in encounter and attempt to import my design in virtuoso to do the claibre DRC check, I get so many errors on the NW and BP spacing. 114919 114922[
You do not have error messages?, only warning? well you need to fix the map file used to map the layers between the lef/GDSand DEF files.
Usually you need to read the tech file first, then the macros. If you want some help, post the exact error message and the command you've used.
Hello, First I exported File-> export-> stream. and .lef file of inverter designed using cms9flp technology Once the file were exported then i invoked abstract generator and i gave library, when i was trying to import gdsii file i am getting the following errors. error ABS-216: There are insufficient metal layers defined in the (...)
Hi all, During my redhawk runs, i'm getting error related to APL, PAD, lef & DEF.. pls go through the attached snap and kindly provide me some information on fixing those errors. Regards, vinay
hi all i was created .lef file with abstract generator but when SOC read this file, i get two error: SOCLF-121: you need to have cut layer after 'METAL1' SOCLF-3 : error found when processing lef file './abstact.lef' anyone could tell me why?
1. Check if you have included the physical views of the buffers/inverters (lef view) 2. check if the functionality definition defined in .libs 3. Check for the log file, (Normally while loading the design, Encounter would specify the list of usable buffers/inverters). If not,it should give out warning/error, and start debugging based on the error.
hai friends when i am trying to load a lef file containing bondpad in encounter the following error arise The bump macro "PBP_" does not have geometry on metal layers so it will be ignored can anybody say what is the error here
I have a problem about the OpenAccess (OA). I have used the tools lef2oa and verilog2oa converting the lef and verilog file into oa library, and then send them into a tool, which is developed by UCLA. However, there is a error: error: Tech database contains features defined in OpenAccess data model version 4 (release (...)
Hi all, When I trying to do Special route for Pad pins after the power ring has done, the terminal shows following err msg: Reading lef technology information... *error* "data_files/macro/dp_rf_256x8/dp_rf_256x8.vclef", line 374: cannot add PIN QA to MACRO dp_rf_256x8 at or near "QA" *error* (...)
Hi I am trying to import an Gate level design in Encounter but while reading the file it shows following error **error: (ENCVL-319): vinst (buf_dummy__859) for pcell (iu3_nwin8_isets4_dsets2_fpu0_v850_cp0_mac0_dsu1_nwp2_pclow2_notag0_index0_lddel1_irfwt0_disas1_tbuf1_pwd2_svt0_rstaddr0_smp3_fabtech29_clk2x0_1) cell (0) has 0 VTerms.
Check the lef file version first & see whether the lef version is supported by the EDA tool. Check How these error message affect the lef quality. The Tech-lef should have all the Layers ( Metal, Via and etc) defined in it. If not, ask the Vendor to provide the correct lef file.
Hi, I suspect your first lef loaded is not a technology lef as the 2nd error message suggests. It could also be due to conflicting lef versions (unlikely, though). You can do minor modifications to lef as long as you know what you are doing (but do NOT modify co-ordinates w/out consulting with foundry). (...)
Halo, Can anyone tell me where to define the RULE lef-DEFAULT settings for Encounter or Nanoroute? I need to do this for defining the default via settings. I get an error saying that the default via between Metal1 and Metal2 is not defined when I run the Verify Step of Cadence Abstract Generator?
i have had problems in the past using encounter to verify drc and antennas. the tool reported several false errors. if possible use some virtuoso integrated tool.
Hi all I get the following error while trying to stream in the lef file: "Constraint minSpacing does not match the referenced technology database:Cannot modify a read-only technology database.Technology information was ignored" Anybody has any idea as to what needs to be done here? Regards Brittoo
error: (SOCTS-136): buffer footprint is not defined. What is the meaning of the above error and what should i do to get rid this message?
dear all, i couldn't able to import the design in SOC.getting error after giving OK such as bad option "**error:(SOCSYT-6729): bad option "**error: technology file or a lef FILE. ":must be blank, cget, configure, copy, data, get,put, read, redither, transparencey, or write ":must be blank, (...)
Hi all, I got a lot of errors when reading Bond pad lef information in Encounter. It happened during special routing.All these errors are relative to supporting POLYGON with 45 degree edges. I am using Encounter 7.1. Reading lef technology info... *error* (...)
you can use abstract generator to dump the lef file. But for that, your tech file should have P & R rules, otherwise you will end up in error.
Hi all, I am using cadence soc encounter 4.1 and I have the following problem: I got a clf file generated by TSMC memory compiler, while using the (generatelef) command in soc encounter to generate a .lef file, I got a warning and no lef files generated. syntax: generatelef -clfFile /ram/fft_dpram_ant.clf (...)
Hi everyone, I am using SoC Encounter and I have an annoying error appears when I load lef file, I am facing this error for the first time and I performed the layout process for many designs, the error is like this: **error: Load lef file (...)
**error: (SOCDB-1221): No PG pin 'gnd' in any cell in the lef files. can some one explain the possible mistake i am doing which is giving me this error wen i run soc encounter and also let me know how can i clear this error . Suresh
When I do back end design with SOC encounter,it reports the error of IO lef file. said: Antenna gate area must be a positive value at or near 0. I found in the lef file,the Antenna gate area of some pin are just set to 0. What does "Antenna gate area" used for?? Can I just delete all 0 Antenna gate areas ,since 0 means (...)
I use Abstract to genetate the lef files from a layout. when I read the technology file, there are a lot of errors and warnings, as follow: error (ABS-216): There are insufficient metal layers defined in the current design. You must define at least two metal layers in the prRoutingLayers class of the technology file.3F WARNING (...)
error : Technology section is missing entirely. (line 1292) (TFCHK-040) error: Failed to read from file ../tech_files/tsmc13fsg_8lm_tech.lef. (TFCHK-001) this is the error which i get when i am tryign to create a llbrary using milkyway..... reply oon hw i can overcome this ...?
Hi, when i try to do sroute, i get the following error in vclef file. SITE memory not defined at or near "memory" The flow i tried out is, design import, set power rings, stripes, place the macros manually sroute. in sroute, i get the error. on verifying the particular line mentioned in the error, there is (...)
I have try cadence script to trasform RTL 2 GDSII (pci_crt - OpenCores project), now when I execute it I receive a error: "I can't find libgen" ? For this process I use SOC33 and GSLib ... where I can find libgen program ? thanks
I tried to import the nondefault rule lef file, but I couldn't import it. I got following error information. what is the problem? What is the exact step to use the nondefault rule to chang the clock wire width after routing? -------------------------------------------------------- ** EXCHANGEFORMATS-USER-113 error ** Cannot create (...)
hi friends im facing problem pks(cadence) when run this command read_tlf error message is error : tlf version is 4.1 only version 4.3 is support or highter version are supported. pls help to fix it thanks