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I'm using TANNER v14.1 & TSPICE. I have designed a ckt in S-Edit. 1) I want to convert the schematic into a good quality TIFF image. I used the option of "Capture Window" but the image quality is very poor. What should I do? 2) After simulating the ckt using TSPICE, I want to find the estimated chip area. How to find it?
After placement it should be apporimately 70% . using checkPlace command u can see that percent.. Based on this we can estimate. And ater full flow based on routing and placement congestion, we can increase or decrease the block size.
hi,everyone,I want to know how to estimate sram area in ASIC for example, I want to implement a two port (one for read ,one for write ) sram in ASIC , and the depth is D, words width is W , in a certain technology, how to estimate the area ?
Somewhere in your PDK docu (e.g. in the "analog characterization" description of your process) you should find metal-to-metal and metal-to-substrate capacitance values for each metal layer. Together with the calculated area of the route - if necessary including its fringing capacitance - you can estimate its total capacitance. A simpler method w
RC extraction from a tool like Synopsys Star-RC will spit out an HSPICE SUBCKT netlist with Resistances and capacitances corresponding to the different layers in your layout in addition to the transistors. It might include the area/perimeter of your transistors but the best estimate of your net area should come from looking at layout (...)
Salaam Your design could be power estimated by general flow: Simulate your design as the simulator log nets switching activities in a VCD file. Then with your design, standard cell library and the VCD file, you could estimate the power consumption with PrimeTime PX.
I want to implement a FSK reciever on an FPGA for 4 channels in (600-2k) hz range. The FPGA has a maximum gate count of about 300k. Would the area be enough to implement this. Are there any rules of thumb regarding an FSK reciever and gate count?
Hi, I need to know if i can use COST 231 model to estimate the path loss for a wireless sensor actor network deployed in an urban area. The sensors and actors both are static but the actors has mobility potentials?
Hi, I need to know if i can use COST 231 model to estimate the path loss for a wireless sensor actor network deployed in an urban area. The sensors and actors both are static but the actors has mobility potentials?
Specific resistance of power devices is very often given in these strange units of r=mOhm*mm2 so that people can quickly estimate device area A for the required Rdson value: Rdson = r / A A more fundamental parameter is specific resistance of the device in Ohms per one micron of gate width - rch. If you have SPICE model of the device, rch can be
finding the mathematical equation that can be used to estimate the coverage area of the electromagnetic waveFor the switching speed respectively the frequency range achieved by your circuit, you can simply treat the problem as magnetostatic one. No electromagnetic properties (coupling of electrical and magnetical field) have to be co
For approximate estimate, pls try capacitor equation:C= εS/(4πkd). S is overlap area, d is gap between Metal and poly layer (it can be found in process document). ε is for oxide.
Unfortunately you need to specify the photodiode to some extent. As I said, the range of capacitance, for example, can be huge. Leakage currents can vary enormously. The photodiode area would be one starting point to estimate the photodiode characteristics. Keith.
Hi everyone!!! I'm studying of estimate time delay which signal transmitted from mobile to base station (BS) using some methods: TOA, DOA, TDOA. I need some Matlab Code about Matrix Pencil algorithm!!! Please help me!!! Thanks so much!!!!
I don't think you should read too much on what DC reports as interconnect area. This number is largely exaggerated and not correct. If you want a better estimate of the wire area, you should get it from ASTRO or IC Compiler. I have many times got ridiculously large interconnect numbers from DC and a completely smaller number from their (...)
This is usually just a rough estimate anyway when people toss around "gate count". If you want to see a real gate count you should look at a synthesis report.
Hello friends, I want to estimate the aria of the layout of my circuit. I know the size of transistors but I don't know the size of the aria to be occupied by routing signals and power. Please can any one help me how I can estimate the aria of my circuit. Thanks. Firas.
I would like to know how to do the rough estimate of the required area to fabricate the layout of a inductor. Requesting to attach some materials regarding this. thanks in advance.
How can estimate the layout area from schematic? me use cadence tool thanks
I believe you first need to do a dynamic IR drop analysis to come up with the estimate of the amount of decaps required and the area where they are required. In the process above 130nm actually lot of people just go ahead and add decaps similiar to fillers without actually calculating the IR. The reason it works at this technology is that the leaka
I'm design in 0.35um TSMC technology How can i estimate the size of NMOS, PMOS, Capacitor and Resistor that i used Should the wire be included inthe calculation of size?
Hi all, I would like to estimate the area of a circuit using the following formula: "area = gate count * area of NAND2X1" But I only know the values of 90nm/.13/.18 tech(tsmc). Is there anyone can tell me what's the area of .25/.35/65nm tech? Thanks!
Floorplanning: Arrange the blocks of the netlist on the chip. In floorplanning we estimate sizes and set the initial relative locations of the various blocks for our soc. The goal of FP is to calculate the sizes of all the blocks and assign them locations (x-y co-ordinates). The Objective is to Keep the highly connected blocks physically close to
hi, my 2 cents gate count is a rough prediction before the real place and route how much cells would be like Total area / Nand2 area = gate count Ths will give a rough idea, this is needed to estimate how big the chip would be, what would be the Xand Y and all.. but the value of the placeable instances would give an actual idea (...)
How to get the gate count number after synthesis? How to estimate the raft die size?
Does anybody know how much it's gonna cost for a 12-layer PCB with a total area of 4050 mm^2, and around 400 vias, I need a rough estimate ASAP, please help!!!
Hi, I want to know more about low power DRAM design,how to estimate it's power and it's area? Thx.
there is no need to calculate die size after you get the def file, since the number is there already. it is good to estimate the die size in the spec-defining stage and watch the die size in synthesis and STA stage. Consider if it's a pad limited chip. If yes, Die Size(um2)=SUM(one side pad widths)*SUM(one side pad widths) If core limited, D
Dear all, Suppose my size of the power transistor is w=900um l=0.7um If I use the "waffle" style of layout method, how do I estimate the layout area of the power transistor? (the spacing in a contact to poly gate is 0.4um, the min. gate poly is 0.5um)
There are a number of ways to estimate the gain of an antenna. Here is one: G dbi = 10 log10 ( 4 Π (effective aperture area) / λ?) * efficiency The distance on the surface of the earth may be calculated using spherical trig. Look up the details is Bowditch ( a bible in the boating world). Added after 7 m
hi all, I need to estimate the area taken by 8K and 16 K memories in 0.13IBM technology. need this estimation for a proposal work actually. Please advise me what should I do to know about the memory cell area in IBM0.13 technology. best regards, mirza
Hi, When I design a circuit, how to estimate gate count? Is there any reference? And is it related to the technology like 180nm or 90nm? Thanks! Davy
Q: Is it possible to use the copper traces in the PCB (printed circuit board) as a heat sink? If so, how would I estimate the heat sink capability of the PCB, assuming that I know the pattern of copper traces and the thermal resistance of the component package? A:
can anyone help me how to select the right ultrasonic sensor for my project.(what variable have to consider? How to estimate the area covered by the ultrasonic signal at given distance, for example 1 meter?) if i want to build the ultrasonic sensor myself, can anyone teach me how to do
Floorplanning is the process of defining the chip-size, placing the macrocell and placing I/O pads. At this stage you can do an estimate for routing requirements etc.
Hi, How do I calculate or estimate roughly the metal line capacitance per unit area? Someone told me it is roughly 1fF/um? in modern process. Anyone? Thanks
Does the device model include the cap between nwell to sub? If it dosen't, how to estimate the capacitance by rule of thumb? Thanks,
hi, does anybody have an approximate equation describing the chip/die area depending on the gate counts and ssrams or other compiled macros to estimate the die area (without IO pad) since this gross estimation will help me to decide whether the chip is pad limited or core limited. Thanks in advance, Thomson
how does one estimate offset voltage in the design process (i.e., opamp)? As a rule of thumb any technologie has a certain offset intrinsic per um . The offset of a diff input pair is proportional with 1/sqrt(W*L) so ..the first aprox you can do is : biger area means lower offset The layout can increase this or keep it
Hi, They estimate according to your board area,thru hole devices,layer stackup,smd,impedance,thickness of copper etc... You can look into the site called Sanmina and collect data's from the site.... Regards Rame
Hi, I am designing a chip, it's process is .13. I want to estimate die size for my chip. The chip gate count is 700,000, how much die size should i choose(no including IO)
This is usally the case - top plate is gate material, and bottom plate is the mosfet tub which is always bigger than the top plate.. You can estimate it simply by using just the area of the gate region, or if you want to get fancy, you can include the fringing capacitance around the periphery of the gate region.
Usually under 1 GHz humidity and rain don't paly a big role in attenuation, you can estimate some 0,2 dB /Km. Take instead a lot of care at the link margin; if you have to transmit data at least 20 dB margin, for voice 10 to 15 dB is enough. Mandi
Hi all can anybody tell how to estimate the total number of decap cells in a design. and what are the disadvantage of having many decap cells in design thanks
You can estimate current rating of secondary winding by measuring wire diameter of it. Formula for 4A/mm? current density is I=2*d?. Measured in mm. If your transformer is EI type you may allso measure iron core area and use formula P=S?, S is measured in cm?. This is just to give you an orientation. At thoroid cores power rating estimation is diff
I'd like to ask one question too. I'm using PSS to estimate IIP3 of IF filter, but as every people meet, the 3rd-order curve in low-power area isn't correct. Anyway, in my case, this incorrectness occured up to the high power area that make me very hard to find the 3 dB/dB slope of the curve, compare to PSS+PAC simulation. I have to set (...)
ITs free download. given the details , it can estimate power, area etc rgds
yeah, just estimate value you can get from dc.
Does anyone have a formula/method to estimate die area of an analog part from a spice netlist ? OkGuy