1000 Threads found on edaboard.com: Estimate Area
Does anybody know how capable is Leonardo to extract routing estimates? I know that this is backend work primarily.
So if (most probably) Leonardo doesn't imply even the simplest methods for routing (early-level) estimation, i have another question. Is this possible with their new tool, Precision Synthesis?
Plus: is Leonardo a DeaD tool? Caus
ASIC Design Methodologies and Tools (Digital) :: 09-23-2004 09:24 :: the_penetrator :: Replies: 1 :: Views: 810
I was wondering what is the different, area wise, between >= and ==.
Lets say I want to start switch state in FSM (verilog, asic) with the condition cntr_t >= 4'h8.
(the counting is with a bit faster clock, so in the edge I'm checking it, it sometimes will be 8 and sometimes 9; there is sync).
Isn't it better to check only one bit with =
ASIC Design Methodologies and Tools (Digital) :: 07-03-2013 15:25 :: suquid29 :: Replies: 2 :: Views: 270
After placement it should be apporimately 70% . using checkPlace command u can see that percent.. Based on this we can estimate. And ater full flow based on routing and placement congestion, we can increase or decrease the block size.
ASIC Design Methodologies and Tools (Digital) :: 10-09-2013 01:14 :: vijayR15 :: Replies: 1 :: Views: 250
Suppose my size of the power transistor is w=900um l=0.7um
If I use the "waffle" style of layout method, how do I estimate the layout area of the power transistor?
(the spacing in a contact to poly gate is 0.4um, the min. gate poly is 0.5um)
Analog IC Design and Layout :: 09-21-2007 09:07 :: shaq :: Replies: 4 :: Views: 1266
I want to know more about low power DRAM design,how to estimate it's power and it's area?
ASIC Design Methodologies and Tools (Digital) :: 02-24-2008 22:40 :: rz56 :: Replies: 1 :: Views: 542
How can estimate the layout area from schematic?
me use cadence tool
Analog IC Design and Layout :: 09-08-2009 21:09 :: ramaro :: Replies: 4 :: Views: 2287
hi,everyone,I want to know how to estimate sram area in ASIC
for example, I want to implement a two port (one for read ,one for write ) sram in ASIC , and the depth is D, words width is W , in a certain technology, how to estimate the area ?
ASIC Design Methodologies and Tools (Digital) :: 05-03-2013 23:13 :: aspirinnnnn :: Replies: 5 :: Views: 1014
Does anyone have a formula/method to estimate die area of an analog part from a spice netlist ?
Other Design :: 03-05-2003 08:21 :: okguy :: Replies: 0 :: Views: 1264
can anybody tell how to estimate the total number of decap cells in a design.
and what are the disadvantage of having many decap cells in design
ASIC Design Methodologies and Tools (Digital) :: 06-22-2005 01:52 :: smith_kang :: Replies: 1 :: Views: 1557
Usually under 1 GHz humidity and rain don't paly a big role in attenuation, you can estimate some 0,2 dB /Km.
Take instead a lot of care at the link margin; if you have to transmit data at least 20 dB margin, for voice 10 to 15 dB is enough.
RF, Microwave, Antennas and Optics :: 08-26-2005 08:03 :: FANT :: Replies: 6 :: Views: 1127
I just wanted a rough estimate of the area of 256KB flash on 0.25um and 0.35um technology. Also how much area would a 8-bit successive approximation ADC and DAC occupy in 0.25um and 0.35um?
Analog Circuit Design :: 04-07-2006 03:43 :: suhas_shiv :: Replies: 1 :: Views: 662
you can refer to the ieee paper:
An accurate statistical yield model for CMOS current-steering D/A converters
I am also looking for this paper.
Would you share this paper if you can get it?
For the gate min area, you can estimate using the following steps.
(1) calculate the delta(I)/I from INL requirement and yield requirement.
Analog Circuit Design :: 04-11-2006 02:04 :: lovseed :: Replies: 1 :: Views: 653
They estimate according to your board area,thru hole devices,layer stackup,smd,impedance,thickness of copper etc...
You can look into the site called Sanmina and collect data's from the site....
PCB Routing Schematic Layout software and Simulation :: 06-06-2006 05:23 :: Rame :: Replies: 3 :: Views: 2363
does anybody have an approximate equation describing the chip/die area depending on the gate counts and ssrams or other compiled macros to estimate the die area (without IO pad) since this gross estimation will help me to decide whether the chip is pad limited or core limited.
Thanks in advance,
ASIC Design Methodologies and Tools (Digital) :: 07-05-2006 05:47 :: Thomson :: Replies: 1 :: Views: 723
How do I calculate or estimate roughly the metal line capacitance per unit area? Someone told me it is roughly 1fF/um? in modern process. Anyone?
Analog IC Design and Layout :: 08-08-2006 22:27 :: ccw27 :: Replies: 0 :: Views: 992
nice to meet you in the same physical/structural limitation corner of application circuits!
What do you think is the right business model to work in this area. I am shure if I would post any circuit solution I will do it for compensation or do it opencircuit. These circuit problems I guess are hard and have found solution which are c
Analog Circuit Design :: 02-23-2007 06:45 :: rfsystem :: Replies: 10 :: Views: 1265
If someone knows how to estimate/calculate the power dissapation as a function of the chip temperature, please send a reply or an email.
ASIC Design Methodologies and Tools (Digital) :: 08-17-2007 07:51 :: Bjarredsbon :: Replies: 4 :: Views: 1208
i need to know how to estimate and carry out an industrial and domestic networking layout on electric power distributions
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-10-2008 09:26 :: edem martins.g. :: Replies: 4 :: Views: 1958
You need to ask yourself a couple of questions first:
1. What is my decimation factor? Which you've stated as 1024.
2. You are looking at a CIC filter, so how far down does your first side lobe need to be? This will set the number of stages of the CIC filter.
3. Now you know you're number of stages, is your bandwidth small enough compared to y
Digital Signal Processing :: 04-06-2009 19:41 :: RBB :: Replies: 4 :: Views: 1812
I would like to estimate the area of a circuit using the following formula:
"area = gate count * area of NAND2X1"
But I only know the values of 90nm/.13/.18 tech(tsmc).
Is there anyone can tell me what's the area of .25/.35/65nm tech?
ASIC Design Methodologies and Tools (Digital) :: 05-04-2009 08:04 :: littleming :: Replies: 3 :: Views: 1695
I'm design in 0.35um TSMC technology
How can i estimate the size of NMOS, PMOS, Capacitor and Resistor that i used
Should the wire be included inthe calculation of size?
Analog IC Design and Layout :: 06-05-2009 12:34 :: Hitotsu :: Replies: 1 :: Views: 676
I would like to know how to do the rough estimate of the required area to fabricate the layout of a inductor. Requesting to attach some materials regarding this. thanks in advance.
Analog IC Design and Layout :: 09-19-2009 01:25 :: ksooryakrishna1 :: Replies: 2 :: Views: 621
I want to estimate the aria of the layout of my circuit. I know the size of transistors but I don't know the size of the aria to be occupied by routing signals and power.
Please can any one help me how I can estimate the aria of my circuit.
Analog IC Design and Layout :: 10-11-2009 15:10 :: Firas :: Replies: 3 :: Views: 669
I don't think you should read too much on what DC reports as interconnect area. This number is largely exaggerated and not correct. If you want a better estimate of the wire area, you should get it from ASTRO or IC Compiler. I have many times got ridiculously large interconnect numbers from DC and a completely smaller number from their (...)
ASIC Design Methodologies and Tools (Digital) :: 12-20-2009 01:36 :: rakko :: Replies: 15 :: Views: 991
Yes, Radiomobile is a very good software however it is intended for outdoor propagation. If you, instead need to estimate indoor or urban-area coverage you should refere to statistical formulas (eg. COST-231, Okumura-Hata, ecc)
RF, Microwave, Antennas and Optics :: 11-23-2011 06:47 :: albbg :: Replies: 2 :: Views: 416
I don't know what synthesis tool you're using and I'm actually not looking at any synthesis tool manuals at the moment but I'll try to answer some of these.
1. The net area is probably a figure relating to the amount of routing resources used. I'm guessing this defined in the technology section of the library you're using and it's probably just
ASIC Design Methodologies and Tools (Digital) :: 03-29-2012 04:05 :: gliss :: Replies: 8 :: Views: 560
Current density numbers don't help much for extreme designs. It's more reasonable to estimate copper overtemperatures based on thermal models. The cooling concept is the first point to be answered.
PCB Routing Schematic Layout software and Simulation :: 06-05-2012 11:00 :: FvM :: Replies: 7 :: Views: 2649
TLUplus come with foundry tech files (or you may generate them from ITF or GRD tech files).
The floorplan may comes from different sources:
1. You have previous design, so you may use it as reference (scale somehow or manually modify)
2. You did (at first) non-topographical synthesis (with WLM, as example), estimate the cell area, take inot accoun
ASIC Design Methodologies and Tools (Digital) :: 11-26-2012 00:44 :: oratie :: Replies: 4 :: Views: 453
I'm using TANNER v14.1 & TSPICE. I have designed a ckt in S-Edit.
1) I want to convert the schematic into a good quality TIFF image. I used the option of "Capture Window" but the image quality is very poor. What should I do?
2) After simulating the ckt using TSPICE, I want to find the estimated chip area. How to find it?
Analog IC Design and Layout :: 02-03-2014 05:13 :: pavan garate :: Replies: 0 :: Views: 219
I want to estimate the effect of bondpad to my circuit's performance. I think the dominant effect is shunt parasitic capacitance. I used HFSS to simulate antenna, so I tried to simulate parasitic capacitance of bondpad but I don't know is my setting correct or not? When I extended the boundary, the result was changed! Thus how can I k
Analog IC Design and Layout :: 09-06-2014 03:55 :: ktx2222 :: Replies: 0 :: Views: 209
rule of thumb : 1mm bonding length =1nH
So you can roughly estimate what you need.
Other Design :: 09-18-2001 21:18 :: cswang :: Replies: 8 :: Views: 5593
can anyone tell me how to estimate the delay of a clock tree for 500 register.
I have gated clock in my design which have a original clock A.
using dc, I create a clock for that clock B.
but how to set the delay of the clock B relative to clock A.
Or I should set the delay to 0,and I use the clock tree to make sure A and B change a
ASIC Design Methodologies and Tools (Digital) :: 07-26-2002 22:32 :: kinysh :: Replies: 4 :: Views: 1901
This site shows a map of the earth with dark and light areas representing wher the sun is shining. This will prove helpful for hams in selecting frequencies. The gray line area is extremely useful for 160 m propagation.
Software Links :: 12-21-2002 18:32 :: flatulent :: Replies: 0 :: Views: 1439
balancing logic utilization and area efficiency in FPGAs
Available here, found with g00gle:
1 warning sent .
Next time please:
- check on elektroda if doc is present or a link to it is present (use search)
- check if doc is available on the internet (use google).
Other Design :: 02-20-2003 03:12 :: smalloof :: Replies: 0 :: Views: 1087
Imagine that there are two wire wires in the same metal level on chip running in parallel. Than these two wires have a mutual capacitance and a capacitance to substrate. The first one is called coupling and the second one area. If you take into account only one wire its parasitic cap is made of a parallel plate component and a edge component. Ther
ASIC Design Methodologies and Tools (Digital) :: 03-06-2003 09:53 :: rfsystem :: Replies: 2 :: Views: 4374
You will most certainly receive many good hints regarding programs, methods, planning etc. on the topic in time. The design that is in my mind at the moment is a A/D converter, which by its nature consists of analog parts and digital parts. A great danger in this mixing of analog and digital circuits is that the digital parts produce noise that tra
ASIC Design Methodologies and Tools (Digital) :: 07-21-2003 10:03 :: Pim :: Replies: 3 :: Views: 1519
in old in keil c51 i use Far Memory area
in this FAR area user can define self command to access special memory area (write byte Read byte ...)
this very usefull when you ry put data in external serial flash
can IAR C compiler have any way to do same ?
Microcontrollers :: 12-11-2003 00:14 :: maziar :: Replies: 0 :: Views: 1216
To be a better engineer, we must know not only design skill but business. So we must know how to estimate cost of a IC, which includes design cost, manufacture cost, test cost, package cost and others. What do they come from and how to minimize them?
I can't find a free report on IC cost analysis, who can give me a overview or detail description
ASIC Design Methodologies and Tools (Digital) :: 02-23-2004 22:33 :: wwfhm2002 :: Replies: 9 :: Views: 2965
hi,friends, any good spectrum estimate ebook recommended??
It is really difficult to study this.... :(
Digital Signal Processing :: 04-02-2004 18:01 :: speedoak :: Replies: 6 :: Views: 1507
Hi, dear friend, do you know where I can buy the 51 serials MCU simulator at DFW area?
Microcontrollers :: 06-08-2004 14:49 :: saryee :: Replies: 1 :: Views: 661
ahmed osama asked quoting "Electromagnetic Wave is quite a complicated model for the wave equation of the photons best described by maxwell's equations, so it may have cross-section area".
EM wave in guided medium for example a simple TEM wave (lets not complicate with light for now) does for sure have a cross-s
Mathematics and Physics :: 09-04-2004 00:45 :: djalli :: Replies: 9 :: Views: 2278
from DC report_area result, how to convert that unit to gates?
Combinational area: 2503906.000000
Noncombinational area: 16571702.000000
ASIC Design Methodologies and Tools (Digital) :: 07-23-2004 03:01 :: sweesw :: Replies: 5 :: Views: 2245
I am developing a method to estimate semirigid coaxial cable parameters. This method needs a copper disc in order to short circuit the outter conductor and the center conductor. This disc has a hole in its center for the cable inner conductor to penetrate it (the disc is like a copper washer). Once conected to the cable, the current in the disc str
Electromagnetic Design and Simulation :: 07-23-2004 11:23 :: email@example.com :: Replies: 0 :: Views: 968
I' m looking Program for calculate area from 3 GPS points .
PLEASE help me , thank you
PC Programming and Interfacing :: 08-20-2004 04:04 :: nooknikz :: Replies: 2 :: Views: 1129
In the AMBA specs says
"Using tri-state implementation to reduce area"
can anyone justify how exactly are we optimising on area when we use a tristate design.
ASIC Design Methodologies and Tools (Digital) :: 09-08-2004 05:15 :: gold_kiss :: Replies: 4 :: Views: 857
Is it possible to predict the main IC parameters such as chip area,power consumption,throuput only from the architecture of the system?
In generaly not! Also power estiamtion tools exist (most are handwritten). If you are lucky and u use only macro blocks, of course you can estiamte area, power, etc.
ASIC Design Methodologies and Tools (Digital) :: 09-22-2004 05:38 :: eda4you :: Replies: 4 :: Views: 2230
yeah, just estimate value you can get from dc.
ASIC Design Methodologies and Tools (Digital) :: 09-26-2004 22:33 :: z81203 :: Replies: 7 :: Views: 5244
How to minimize area in DC synthesis. Any switches beside set_max_area 0?
ASIC Design Methodologies and Tools (Digital) :: 10-29-2004 02:46 :: mikel262 :: Replies: 2 :: Views: 860
I have a small confusion regarding the area of the MOS transistor. When we use a MOS transistor for simulation in Cadence we set its properties through a property dialog box as shown in the attached image. In this dialog box we have the fields for the Source and Drain diffusion area as
I understand that
Analog IC Design and Layout :: 11-30-2004 05:16 :: aryajur :: Replies: 3 :: Views: 1858
I wanna run drc not including one selected area, and remember calibre can run at this one, but I cannot find how to do it, I can select one area on xcalibre window, but how to select reversed area?
Analog IC Design and Layout :: 12-09-2004 21:38 :: harryzhu :: Replies: 0 :: Views: 668