125 Threads found on edaboard.com: Estimate Area
Does anybody know how capable is Leonardo to extract routing estimates? I know that this is backend work primarily.
So if (most probably) Leonardo doesn't imply even the simplest methods for routing (early-level) estimation, i have another question. Is this possible with their new tool, Precision Synthesis?
Plus: is Leonardo a DeaD tool? Caus
ASIC Design Methodologies and Tools (Digital) :: 23.09.2004 09:24 :: the_penetrator :: Replies: 1 :: Views: 746
I was wondering what is the different, area wise, between >= and ==.
Lets say I want to start switch state in FSM (verilog, asic) with the condition cntr_t >= 4'h8.
(the counting is with a bit faster clock, so in the edge I'm checking it, it sometimes will be 8 and sometimes 9; there is sync).
Isn't it better to check only one bit with =
ASIC Design Methodologies and Tools (Digital) :: 03.07.2013 15:25 :: suquid29 :: Replies: 2 :: Views: 239
Does anyone have a formula/method to estimate die area of an analog part from a spice netlist ?
Other Design :: 05.03.2003 08:21 :: okguy :: Replies: 0 :: Views: 1211
can anybody tell how to estimate the total number of decap cells in a design.
and what are the disadvantage of having many decap cells in design
ASIC Design Methodologies and Tools (Digital) :: 22.06.2005 01:52 :: smith_kang :: Replies: 1 :: Views: 1458
Usually under 1 GHz humidity and rain don't paly a big role in attenuation, you can estimate some 0,2 dB /Km.
Take instead a lot of care at the link margin; if you have to transmit data at least 20 dB margin, for voice 10 to 15 dB is enough.
RF, Microwave, Antennas and Optics :: 26.08.2005 08:03 :: FANT :: Replies: 6 :: Views: 1068
Always keep the cell characterization as the last resort.
The library vendor can always do better than you, even though the parameter are rather conservative in case of the process violation and the yield.
Basically yes, but not always. I have an example:
Standard I/O for crystal oscillator.
Parameter : Power(uW/MHz).
ASIC Design Methodologies and Tools (Digital) :: 08.12.2005 02:12 :: Fom :: Replies: 9 :: Views: 1549
I am designing a chip, it's process is .13.
I want to estimate die size for my chip.
The chip gate count is 700,000, how much die size should i choose(no including IO)
ASIC Design Methodologies and Tools (Digital) :: 19.01.2006 01:08 :: tavidu :: Replies: 11 :: Views: 4313
I just wanted a rough estimate of the area of 256KB flash on 0.25um and 0.35um technology. Also how much area would a 8-bit successive approximation ADC and DAC occupy in 0.25um and 0.35um?
Analog Circuit Design :: 07.04.2006 03:43 :: suhas_shiv :: Replies: 1 :: Views: 636
you can refer to the ieee paper:
An accurate statistical yield model for CMOS current-steering D/A converters
I am also looking for this paper.
Would you share this paper if you can get it?
For the gate min area, you can estimate using the following steps.
(1) calculate the delta(I)/I from INL requirement and yield requirement.
Analog Circuit Design :: 11.04.2006 02:04 :: lovseed :: Replies: 1 :: Views: 627
They estimate according to your board area,thru hole devices,layer stackup,smd,impedance,thickness of copper etc...
You can look into the site called Sanmina and collect data's from the site....
PCB Routing Schematic Layout software and Simulation :: 06.06.2006 05:23 :: Rame :: Replies: 3 :: Views: 2249
When I design a circuit, how to estimate gate count? Is there any reference?
And is it related to the technology like 180nm or 90nm?
ASIC Design Methodologies and Tools (Digital) :: 13.06.2006 09:34 :: davyzhu :: Replies: 6 :: Views: 2900
does anybody have an approximate equation describing the chip/die area depending on the gate counts and ssrams or other compiled macros to estimate the die area (without IO pad) since this gross estimation will help me to decide whether the chip is pad limited or core limited.
Thanks in advance,
ASIC Design Methodologies and Tools (Digital) :: 05.07.2006 05:47 :: Thomson :: Replies: 1 :: Views: 677
How do I calculate or estimate roughly the metal line capacitance per unit area? Someone told me it is roughly 1fF/um? in modern process. Anyone?
Analog IC Design and Layout :: 08.08.2006 22:27 :: ccw27 :: Replies: 0 :: Views: 932
Is it possible to use the copper traces in the PCB (printed circuit board) as a heat sink? If so, how would I estimate the heat sink capability of the PCB, assuming that I know the pattern of copper traces and the thermal resistance of the component package?
Analog Circuit Design :: 02.11.2006 00:53 :: IanP :: Replies: 2 :: Views: 5529
nice to meet you in the same physical/structural limitation corner of application circuits!
What do you think is the right business model to work in this area. I am shure if I would post any circuit solution I will do it for compensation or do it opencircuit. These circuit problems I guess are hard and have found solution which are c
Analog Circuit Design :: 23.02.2007 06:45 :: rfsystem :: Replies: 10 :: Views: 1224
How do designers arrive at the die size, if they know the package size. Say for example the package size is 14*14. ( It is a wire bond design )
ASIC Design Methodologies and Tools (Digital) :: 09.07.2007 20:58 :: vak :: Replies: 2 :: Views: 1260
If someone knows how to estimate/calculate the power dissapation as a function of the chip temperature, please send a reply or an email.
ASIC Design Methodologies and Tools (Digital) :: 17.08.2007 07:51 :: Bjarredsbon :: Replies: 4 :: Views: 1164
Suppose my size of the power transistor is w=900um l=0.7um
If I use the "waffle" style of layout method, how do I estimate the layout area of the power transistor?
(the spacing in a contact to poly gate is 0.4um, the min. gate poly is 0.5um)
Analog IC Design and Layout :: 21.09.2007 09:07 :: shaq :: Replies: 4 :: Views: 1191
I want to know more about low power DRAM design,how to estimate it's power and it's area?
ASIC Design Methodologies and Tools (Digital) :: 24.02.2008 22:40 :: rz56 :: Replies: 1 :: Views: 501
i need to know how to estimate and carry out an industrial and domestic networking layout on electric power distributions
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.05.2008 09:26 :: edem martins.g. :: Replies: 4 :: Views: 1822
You need to ask yourself a couple of questions first:
1. What is my decimation factor? Which you've stated as 1024.
2. You are looking at a CIC filter, so how far down does your first side lobe need to be? This will set the number of stages of the CIC filter.
3. Now you know you're number of stages, is your bandwidth small enough compared to y
Digital Signal Processing :: 06.04.2009 19:41 :: RBB :: Replies: 4 :: Views: 1745
I would like to estimate the area of a circuit using the following formula:
"area = gate count * area of NAND2X1"
But I only know the values of 90nm/.13/.18 tech(tsmc).
Is there anyone can tell me what's the area of .25/.35/65nm tech?
ASIC Design Methodologies and Tools (Digital) :: 04.05.2009 08:04 :: littleming :: Replies: 3 :: Views: 1603
I'm design in 0.35um TSMC technology
How can i estimate the size of NMOS, PMOS, Capacitor and Resistor that i used
Should the wire be included inthe calculation of size?
Analog IC Design and Layout :: 05.06.2009 12:34 :: Hitotsu :: Replies: 1 :: Views: 601
can this diode withstand a constant current of 1.3A?
the datasheet does not give the power is for reverse polarity protection in a circuit.
..though it has 0.875 V forward volt drop and so the power will be 1.3*0.875 = 1.14W....That seems an awaful lot for a diode..
Electronic Elementary Questions :: 18.06.2009 09:16 :: eem2am :: Replies: 3 :: Views: 4683
How can estimate the layout area from schematic?
me use cadence tool
Analog IC Design and Layout :: 08.09.2009 21:09 :: ramaro :: Replies: 4 :: Views: 2144
I would like to know how to do the rough estimate of the required area to fabricate the layout of a inductor. Requesting to attach some materials regarding this. thanks in advance.
Analog IC Design and Layout :: 19.09.2009 01:25 :: ksooryakrishna1 :: Replies: 2 :: Views: 577
I want to estimate the aria of the layout of my circuit. I know the size of transistors but I don't know the size of the aria to be occupied by routing signals and power.
Please can any one help me how I can estimate the aria of my circuit.
Analog IC Design and Layout :: 11.10.2009 15:10 :: Firas :: Replies: 3 :: Views: 642
I don't think you should read too much on what DC reports as interconnect area. This number is largely exaggerated and not correct. If you want a better estimate of the wire area, you should get it from ASTRO or IC Compiler. I have many times got ridiculously large interconnect numbers from DC and a completely smaller number from their (...)
ASIC Design Methodologies and Tools (Digital) :: 20.12.2009 01:36 :: rakko :: Replies: 15 :: Views: 962
Yes, Radiomobile is a very good software however it is intended for outdoor propagation. If you, instead need to estimate indoor or urban-area coverage you should refere to statistical formulas (eg. COST-231, Okumura-Hata, ecc)
RF, Microwave, Antennas and Optics :: 23.11.2011 06:47 :: albbg :: Replies: 2 :: Views: 333
first things first, you need to try and estimate the power loss you need to dissipate... At what frequency are you switching the FETs? as with any high Id FET the trade off is often high Qg meaning slower switching speeds and hence longer time in the linear region = heat! (not to mention much higher gate drive current = more heat!). Also, depending
Power Electronics :: 19.12.2011 09:59 :: thunderdantheman :: Replies: 17 :: Views: 3361
I want to implement a FSK reciever on an FPGA for 4 channels in (600-2k) hz range. The FPGA has a maximum gate count of about 300k.
Would the area be enough to implement this.
Are there any rules of thumb regarding an FSK reciever and gate count?
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.01.2012 22:11 :: warriorwithin :: Replies: 2 :: Views: 349
I don't know what synthesis tool you're using and I'm actually not looking at any synthesis tool manuals at the moment but I'll try to answer some of these.
1. The net area is probably a figure relating to the amount of routing resources used. I'm guessing this defined in the technology section of the library you're using and it's probably just
ASIC Design Methodologies and Tools (Digital) :: 29.03.2012 04:05 :: gliss :: Replies: 8 :: Views: 495
Current density numbers don't help much for extreme designs. It's more reasonable to estimate copper overtemperatures based on thermal models. The cooling concept is the first point to be answered.
PCB Routing Schematic Layout software and Simulation :: 05.06.2012 11:00 :: FvM :: Replies: 7 :: Views: 2323
TLUplus come with foundry tech files (or you may generate them from ITF or GRD tech files).
The floorplan may comes from different sources:
1. You have previous design, so you may use it as reference (scale somehow or manually modify)
2. You did (at first) non-topographical synthesis (with WLM, as example), estimate the cell area, take inot accoun
ASIC Design Methodologies and Tools (Digital) :: 26.11.2012 00:44 :: oratie :: Replies: 4 :: Views: 412
hi,everyone,I want to know how to estimate sram area in ASIC
for example, I want to implement a two port (one for read ,one for write ) sram in ASIC , and the depth is D, words width is W , in a certain technology, how to estimate the area ?
ASIC Design Methodologies and Tools (Digital) :: 03.05.2013 23:13 :: aspirinnnnn :: Replies: 5 :: Views: 864
rule of thumb : 1mm bonding length =1nH
So you can roughly estimate what you need.
Other Design :: 18.09.2001 21:18 :: cswang :: Replies: 8 :: Views: 5382
Imagine that there are two wire wires in the same metal level on chip running in parallel. Than these two wires have a mutual capacitance and a capacitance to substrate. The first one is called coupling and the second one area. If you take into account only one wire its parasitic cap is made of a parallel plate component and a edge component. Ther
ASIC Design Methodologies and Tools (Digital) :: 06.03.2003 09:53 :: rfsystem :: Replies: 2 :: Views: 4108
You will most certainly receive many good hints regarding programs, methods, planning etc. on the topic in time. The design that is in my mind at the moment is a A/D converter, which by its nature consists of analog parts and digital parts. A great danger in this mixing of analog and digital circuits is that the digital parts produce noise that tra
ASIC Design Methodologies and Tools (Digital) :: 21.07.2003 10:03 :: Pim :: Replies: 3 :: Views: 1449
To be a better engineer, we must know not only design skill but business. So we must know how to estimate cost of a IC, which includes design cost, manufacture cost, test cost, package cost and others. What do they come from and how to minimize them?
I can't find a free report on IC cost analysis, who can give me a overview or detail description
ASIC Design Methodologies and Tools (Digital) :: 23.02.2004 22:33 :: wwfhm2002 :: Replies: 9 :: Views: 2877
Is it possible to predict the main IC parameters such as chip area,power consumption,throuput only from the architecture of the system?
In generaly not! Also power estiamtion tools exist (most are handwritten). If you are lucky and u use only macro blocks, of course you can estiamte area, power, etc.
ASIC Design Methodologies and Tools (Digital) :: 22.09.2004 05:38 :: eda4you :: Replies: 4 :: Views: 2116
yeah, just estimate value you can get from dc.
ASIC Design Methodologies and Tools (Digital) :: 26.09.2004 22:33 :: z81203 :: Replies: 7 :: Views: 4993
let tools automatical select.
or estimate your gate number ,then select a model from your db lib.
ASIC Design Methodologies and Tools (Digital) :: 06.01.2005 03:20 :: floatgrass :: Replies: 13 :: Views: 3908
Global Routing: Initial routing that is done to approximately estimate the delays in the design.
It reduces the Synthesis layout Iteration..
The estimated delay is back annotated to PrimeTime for STA.
Detailed Routing. Actual /complete routing of nets in the design. After this process , the actual delays can be extracted(RC extraction) an
ASIC Design Methodologies and Tools (Digital) :: 02.02.2005 09:25 :: eda_wiz :: Replies: 4 :: Views: 1384
ITs free download. given the details , it can estimate power, area etc
Software Links :: 09.02.2005 09:44 :: eda_wiz :: Replies: 0 :: Views: 616
I'd like to ask one question too. I'm using PSS to estimate IIP3 of IF filter, but as every people meet, the 3rd-order curve in low-power area isn't correct. Anyway, in my case, this incorrectness occured up to the high power area that make me very hard to find the 3 dB/dB slope of the curve, compare to PSS+PAC simulation. I have to set (...)
Analog IC Design and Layout :: 11.02.2005 16:42 :: Amuro :: Replies: 8 :: Views: 6381
Can someone give a rough estimate about what developers charge per hour in the US?
Especially hardware related software development/debugging/testing/consulting (o;
Just need to know for a rough quote for US (o;
EDA Jobs :: 13.02.2005 04:43 :: davorin :: Replies: 3 :: Views: 942
Here is an interview question:
Power amplifier modules used in handset generally consists of GaAs HBT amplifiers, CMOS controller and laminate boards. Break down the raw material cost and development cycle for each component. Use your best judgement and state the assumptions used in the estimate.
If somebody has experience with this area,please
RF, Microwave, Antennas and Optics :: 15.02.2005 23:37 :: zmliu :: Replies: 1 :: Views: 606
You can estimate current rating of secondary winding by measuring wire diameter of it. Formula for 4A/mm? current density is I=2*d?. Measured in mm. If your transformer is EI type you may allso measure iron core area and use formula P=S?, S is measured in cm?. This is just to give you an orientation. At thoroid cores power rating estimation is diff
Electronic Elementary Questions :: 06.05.2005 01:49 :: Borber :: Replies: 2 :: Views: 1534
fuzzy logic normally means lots of if ... than else if ... than ... conditional judgement of the method. Basically, you can use interpolation to estimate the blurred area. However, different senario may need different kind of interpolation algorithm. So you need fuzzy logic to adjust.
Digital Signal Processing :: 22.06.2005 05:56 :: zhaoyimiao :: Replies: 5 :: Views: 1342
Generally there is no any standard methodology for gate-count calculation. For macros usually you can find area info in the macro's datasheet. And for any HDL code to estimate gate-count there are 2 main apporaches:
1. Logic synthesis
2. High-level (RTL) estimation methods.
Estimating gate-count via logic synthesis is accurate and you get th
ASIC Design Methodologies and Tools (Digital) :: 15.08.2005 07:05 :: Arik :: Replies: 3 :: Views: 1444