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Expecting Keyword Stimulus

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Hi, why am i getting the following erors? "ERROR -- expecting keyword stimulus, saw SIGNAL." please help me! thanks.
Q1: I use Orcad 16_2, with pspice and when i want to simulate it i have an error. I define the Pspicetemplete: and the part is AD8129(Differential receiver Amplifiers) IC_U3^@REFDES %+IN %-IN %+Vs %-Vs %OUT %P\d\ %FB @MODEL but I have this error: ERROR -- expecting keyword stimulus, saw VDD. I don't know how can write for (...)
Hai, Could anybody please help me while solving my problem. When I am Creating Propositional controller in PSpice,I am getting error in running my my circuit,I am using OPamp of ALD1701/AL type and I provide path for OPamp,because I use Opamp are extra library element.After completion of Simulation settings and Run my circuit,It sho
Hi, I am new with ORCAD and its family of products , I was trying to build a inverter using single electron transistor and the netslist is created fine but when I try to run it using PSpice, i get the following errors : ERROR -- Model 1e5 used by J_J1 is undefined ERROR -- expecting keyword stimulus, saw 0 any one can help me to (...)
M1 1 2 4 4 CMOSP L=500n W=2u VDD 3 4 dc 3V Vin 1 4 pulse(4 3 4 ln ln 100ns 200ns) --------------------$ ERROR -- expecting keyword stimulus, saw ln. any help what that is? or how to solve it
I guess this is a error due to something that I am ignoring while I simulate... The error is -- ERROR -- expecting keyword stimulus, saw SIGNAL. Why do you think I got this error???
Could anyone recomment me how to write USB stimulus for my device core ? It's not easy to write a flexible stimulus code for USB . Someone told me Vera is a good choice but i never used it . How about Vera ?
Hello everybody, I am using verilogA to generate some sort of analog waveform as the stimulus for my system. However, only the output of stimulus block after some time (since there is delay the very beginning and running the whole system is very time-consuming) are useful and I am thinking to write the stimulus data to a file and then use (...)
Dear all, During power analysis in powermill,we should provide stimulus file.However,my test vectors are read into a behavior RAM after system reset and then the fetch part will obtain the input vectors from RAM cycle by cycle. How can I provide my stimulus during powermill analysis? Many thanks in advance!
Hi, all if my simulator is Hspice, and my schematic editor is ICFB, and my schematic contain some voltage source (DC, PULSE, PWL..), and also some behavior models. how to generate netlist for Hspice simulation that contain all the stimulus above in ICFB ? Thanks in advance.
*Error_Message: Invalid command character following '[' in: ' type=pwl '. si:simin didn't completely suessfully *Problem: I am trying to simulate my design using a text stimulus file in spectre. I included this file in the stimulus File field via Setup -> Simulation files from the ADE window. My stimulus file contains
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Hi, Using pSpice demo 10.0, I would like to use the output of one simulation as a stimulus for another one. I tried to export waveform by using the File/export/stimulus_file. As far as i can see, it worked. Now I try to use this file on another simulation schematic. I set a source as VPWL_file and specified the stimulus file I (...)
Hi, I'm new to cadence. But I have been tinkering with it for some time now and I am comfortable working with the Analog Design Environment using specterS. My question is: Can I specify an external input stimulus file (say, samples of a random noise process generated in Matlab) to run the transient response simulation? Or am I limited to the de
Dear all I have a digital design writen in verilog . after synthesis, i want to simulate in the transistor level using nanosim . and i've translate the verilog netlist into spice netlist using nettran command in hercules . and I want to also translate the testcase written in ntb in to spice stimulus or anyother vector file that nano
I don't know wheather what i think is right , so if anybody give me some hints , I will appreciate very much . 1. Verilog-top vcs files.v +ad=vcsAD.init we can add digital stimulus in the verilog-top module in " initial " procesure , and in the vcsAD.init file , add this command choose nanosim -nspi top.subA.spi -nvec file.vec -C cfg Is
In a mixed-signal simulation , how do we add stimulus in to the design ?shall we add digital/analog stimulus seperately ? I don't know wheather what i think is right , so if anybody give me some hints , I will appreciate very much . 1. Verilog-top vcs files.v +ad=vcsAD.init we can add digital stimulus in the verilog-top module in " (...)
i can't understand the concept of user defined attribute keyword used in the function calling, how it will generate the RTL diagram after synthsis. has any one talk about this topic. :|
Hi. all I'm now designing dll. And I want to simulate with ssc(spread spstrum clock) stimulus input. How can I generate spreaded clock input for spectre or hspice. for example.. center freq' : x modulation rate : y% modulation freq' : z thank you.
Hello! I`m need to create clock stimulus with jitter. I think that need to generate random numbers in desired range and add/substract from constant for period. What you think about this? Can anyone share examples of VHDL code? -- Regards, Jack
I am new to Cadence, please help me on this.... I got a schematics which includes input and output data in bus shape, say, input A<3:0>. When I tried to write a PWLF in stimulus file for simulation, how should I write these net names A<0>...A<3>, I googled different ways, none of them worked out...:(, like 1. v1 (A<0> 0) vsource ty
hi, I am wondering if it is possible ? thanks, jf
hai to every body i need some project web sites regarding to microcontroller projects... Intead expecting someone to refer you the site, why dont you find a pile up in google?...Just google with the required keyword. Good luck.
a very basic term question, but often mixed . such as for verilog of systemverilog verification , my understand is stimulus generally contain transactions drive on DUV , and pattern not only contain driven transactions but also responseChecker for DUV . but in reality , seems not distinguish .
Hi. I have a pulse train created by a model in Matlab. It is saves as an ASCII file of hex time values delimited by carriage returns (I can change the delimiter and data type very easily). I have a Verilog-A model that is expecting a leading edge unit pulse in order to cause a p-n junction breakdown event. The ASCII file therefore describes
Hi All, Please tell me how to check the volatile keyword in simplest way so that i can clear. I have tubo C, VC++, and mplab c compiler. please tell me some easy example for understanding the volatile keyword.
Hi, Iam trying to simulate pic code ( and many other program) using 'Real pic Simulator' but results are not coiming out as iam expecting. following program is to on and off LED for 5 sec. but software shows only on LED not getting it off after 5 sec. any help? ;Equates TMR0 equ 01h STATUS equ 03h TRISA equ 85h PORTA equ 05h O
Hi, Please let me know whether "protected" keyword ( Defined in VHDL-2002) is supported by synthesis tools ( Design Compiler)... Thank you all in advance.
Hello All, I am running few ocean scripts to automate the simulations. I am wondering if it is possible to pass command line argument to the ocean script directly like in PERL or TCL scripting. I think the answer is no from my search online. Any input on how to pass input to the script directly from command line is highly appreciated. Thanks,
Hello all, I am trying to use ibis_buffer found in the analogLib library by cadence. i am connecting a differential resistance of 100 ohm between two input pins defined by of two different by using keyword. This is how i have added the series resistance:- pin_2
Dear All, Can I have advice for how stimulus for AD converter using MPLAB SIM. my MCU is 16f877a
register char special; register short int i=0,a=0; register short int c; I used these 4 register variables in my code. Is this helps to speed up my program? how many register variables that i can use? register key word all owes reserve a register for the program?
Can anyone please tell me as how to store an array in the code memory of STM32 using gcc compiler. I don't know the keyword used to indicate that the arry should be stored into the code space. Waiting for an answer... Thank you,
Where can one learn more about the "stimulus File" format for OrCAD PSpice? The file extension should be ".stm". The version of OrCAD that I have does not have the stimulus Editor, so I'm trying to write one in a text file. I have not had much luck finding the format on the web. Thank you, Richard V.
Hey Folks, plz Need a little help here with my VHDL code. I'm new to VHDL so please bear with me. I'm getting the following Error messages for my code posted below. (I'm using the xilinx 8.1.03i and modelsim ) ERROR:HDLParsers:164 - "C:/Xilinx/rcc3/fgh/test.vhd" Line 81. parse error, unexpected IDENTIFIER, expecting SEMICOLON li
Hey Folks, plz Need a little help here with my VHDL code. I'm new to VHDL so please bear with me. I'm getting the following Error messages for my code posted below. (I'm using the xilinx 8.1.03i and modelsim ) ERROR:HDLParsers:164 - "C:/Xilinx/rcc3/fgh/rc5final.vhd" Line 41. parse error, unexpected PORT, expecting OPENPAR or TICK or LSQB
Hi, I am trying to include "tasks.v" file in my testbench file "tb_data.v" . after reg,wire and parameter declarations, I have include this file ('include "tasks.v"). But it is giving error (expecting the keyword 'module', 'macromodule' or 'primitive'.). the tasks.v file looks like this: task prep_req; begin request <
Dear all i am creating DLL using third party API/DLL using labwindows/CVI and getting the following errors in the argument of a functions which is a pointer to structure of structures. the point where i am getting the Error "found '*' expecting ')' " is basically a pointer to structure of structures (of a third party whose definitions have b
What is the VHDL keyword to exit a function ? Does it exit on the first "return" ?
Here is my testbench with syntax error, unexpected wire, expecting";" in line 2, what's wrong? code: module test_project1 wire clk,reset; reg port1; wire port2; reg eof; integer project1; initial project1=$fopen("proj.dat","rb"); always@(posedge clk) begin eof=feof(project1); if(eof==0) $fscanf(project,"%b",port1);
Hello, I'm using Cadence's Conformal Logic Equivalence Check tool, to run equality-check for RTL and Synthesis Netlist. I'm having problem since for the RTL golden reference part, there is one parameter file (params.vh) that is detected to have syntax error in it, thus stopping the tool's run. But I'm not sure whether the parameter file synta
Hello, I am trying to simulate three inverters connected in sequence using cadence ams simulator and a stimulus file that drives the input with a vpulse. I cannot make it work. The input is not driven and stays at 0.3V with vdd at 1v. (All views are schematic) I use the same stimulus file with simulator spectre and the simulation is OK!
Hello, I encountered a error when I use synplify preimier to synthesis a VHDL design. the log is @E: CD505 :"/filepath/file1.vhd:497:30:497:36|type:expecting enumeration literal 1 error parsing file /filepath/file1.vhd and the code in this file1.vhd is: 497 type start is (INIT, DEFAULT, ABORT, NOACT); 498 signal start_stat
I am using Quartus to try and synthesize a design and I keep getting the following errors when trying to use a generate block Error (10170): Verilog HDL syntax error at near text "genvar"; expecting an identifier ("genvar" is a reserved keyword ) Error (10644): Verilog HDL error at this block requires a nam
hi experts i have lot of confusion about the volatile keyword used in front of function in c. i asked this question in many peoples, i did not get any satisfaction answer from their answer. they are simply said you cant access that function from outside of the file.i tried that ,it might be access. i was using codeblocks 12.11 for th
Hello All, I had already headache for the pcb keyword, if you can know&convenient ,pls help me ,thanks!
Hi, I have a design which contains a PLL that generates system clk. Now I want to do gate-level simulation for that design. Since some of the stimulus in the testbench are with respect to the system clk (The testbench only generates reference clk for the design), I wonder how to capture the system clk generated by PLL? If I simply set up ano
HI all, I new to the VHDL please help me to sort out this error. near ";": syntax error, unexpected ';', expecting STRING_LITERAL or a tick-double-quoted string literal
Hello Experts, I have a spectre stimulus file for SRAM read operation , but when i include the file and simulate via the spectre, I am not getting the expected results, can anyone check if my stimulus file is correct or not. simulator lang=spectre global gnd! vdd (vdd! 0) vsource dc=1 gnd (gnd! 0) vsource dc=0 ic Q=1 Qb=0 BL=1 BLB=1 v6
Is there any trick in AC analysis to find the phase margin if the input stimulus is AC current instead of the AC voltage. If the input is AC current, the magnitude response is impedance rather than the intuitive voltage ratio. It seems like the PM in stability criterion does not apply any more for input AC current stimulus. Any idea how to judge