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39 Threads found on edaboard.com: Fast Path
Hi All I need to add a 21-bit signal to a 32-bit signal, and it won't generate carry bit. Since the clock is really fast, I'm trying to figure out how complex the ADDER logic might be, based on standard library from TSMC. For example, will the critical path have more than 21 NAND-like level of combo cells? Can some body shed lights on ho
How are you fixing setup violations? If you are shortening data path to meet setup check, I don't see why that will produce new set up violations. If the data travels fast, then fixing setup may produce hold violations .
Any attempt to change the current flowing through an inductor sets up a counter-emf which opposes and slows down the change. The opposition is called the reactance (X). The faster the change, the higher the reactance: For a sine wave, X = 2pifL. Hence a fast-changing signal passes more easily though a path of low inductance than through one (...)
Yes, both setup & hold violations are possible in the same path. Setup analysis will be done in the slow corner, where as Hold is done in the fast corner. Now, look at this way, the combo path consists of only HVT cells ( which usually gives more delay in slow corner, less delay in fast corner ). This is due to delay (...)
The DC current that can flow in the substrate should be very small. However, a noticeable amount of current can flow through the substrate during transitions specially if you have any fast switching signals and having low resistance path can create large voltage drops. It is good to directly connect the vsub in a star connection to avoid debiasing,
The clock gating hold violation is usually because: the clk_gate_enb reach the gating cell too fast than the clock signal. So, of cause you can add buffer on the clk_gate_enb path to eliminate the hold violation. (Assume the clk_gate_enb and clock signal are SYNC to each other)
Hai ramesh you can set multicycle path for both the conditions i.e from slow clock to fast clock and from fast clock to slow clock for the condition from slow clock to fast clock set_multicycle_path x -setup -from launch_clk(slow) -to capture_clock(fast) -end ---> which will add (...)
1N4001 diode is far to slow. Use 1N4148 or similar fast switching diode .... :wink: IanP
So you need to refer to the other options. Shunt measurement will probably require a fast differential amplifier to pick up the voltage. Current transformer can be easily made: A small, high ?r ferrite torroid of 5 to 10 mm diameter. 10 to 50 turns secondary winding, terminated with a low ohmic resistor or 50 ohm oscilloscope input.
Hi, I am searching for a fast method to find total number of paths in a circuit during synthesis. I am using design compiler and until now the only solution that I have is to write all paths in a file using following command report_timing -nworst HUGE_NUMBER > file.txt and then use a "grep slack file.txt | wc -l" to extract the (...)
Excuse me for bad writing. I'm poor in English language. Is there anyone who is in this field of study? I am study at the Quantum Dot solar cell, in past two months. but I can't find the path to learn it. I need to learn it fast. because I have thesis, and should do it in 9 months. I need help, to know how can I learn it. if I read paper , Ho
Asynchronous Sequential circuits do not use a clock and can change their output state as fast as the signal path's propagation delay from the input allows. This means they can be faster than Synchronous Sequential circuits. However, they are considerably more likely to suffer from race conditions (inputs arriving at different times causing (...)
Hi all !! what is CRPR? I have a basic doubt of why CRPR is is a problem in On Chip variation (OCV) where we take two different corners (i,e fast and slow path delays) actually this can be a true scenario right?? why do we need to remove it? and what do they mean by reconvergence Pls clr my doubts Thanks in advance
But therein lies the rub. It will not be generally possible to meet the timing requirements if the implementation is in LUTs because, depending on the placement and routing, you could very well get a very fast timing path on the feedback loop and some slightly slower other path that will cause the timing to fail, but this won't
In OCV (On Chip Variation), we assume things can be very different within the chip, under single operating condition. So to simulate the most pessimistic case for: - setup: assume data launch path is really slow & data capture path is really fast. - hold: assume data launch path is really fast & data (...)
Well, depends on where most of your critical fast switching signals are routed. If it's TOP, then a TOP-VCC-GND-BOT will have a longer return path for these signals. Otherwise if this is not a very high-speed (fast switching) PCB, then ideally nothing should change..
The main intention for checking hold time is to make sure that the previous data is not over written. So if min path data arrives to fast just after the clock then u will get hold timing violations. u have to fix these by adding delay buffers, so that ur min path is delayed. Hope it clears ur doubt.
Be careful with zenner diodes ; the switching may be too slow. ; the damage might be done already. Use transorbs and or MOVs that will switch on fast.
Hi, I'm working on design the peak and hold detect circuit to catch the 1ns pulse peak. I used the traditional two amplifiers plus diode strategy. But the voltage feed back amplifier has the slew rate limitation here. The holding circuit has the hopping problem. Does anyone design or know any circuit can detect the fast rising edge pulse? Tha
fast slews make paths faster slow slews makes paths slower in your datapath ... fast slews hurt hold and help setup. it's the opposite for slow slews in your clock path it all depends on what type of skews the different slews are causing
Each interconnect is a transmission line with a signal and a return path, regardless of its lenght, shape or signal rise time. A signal sees a instantaneous impedance at each step along its way down an interconnect. For 'fast' signals, the return path will be as close as possible to the signal path. This will be the plane (...)
hold violation is because data path is too fast, you can add delay cell to fix the hold time violation
If we send data from one clock(say slow clk) domain to other clock domain(say fast clk), then what kind of constraint we have to give while doing synthesis or STA. Please refer the diagram given here. There is a general guideline that when ever the data crossing the clk domain in your design, give cosntraints set_false_path -from clk1 -to clk2.
Can give me a pointer to something that clearly explains the output display of the above said "report gate" command in fastscan. I am having T3 and T5 DRC Violations in my design. How can I resolve them without the help of DFT Visualizer? Thanks Prasad.
both will be done. cause setup violation will occur at slow path ,while hold violation will occur at fast path . they will not bother each other
OP_amp + Nmos fast response .but have volt limt OP_amp + Pmos low speed ... Ti have some paper tal about dymanic loading maybe you can modify you regulator add fast response path in OP_AMP .. speed up response time if you have NPN (some Hi volt process have Vnpn) .. it will better than Pmos
Hi Ramesh, You are right, we should not have any hold violation. once i fixed hold in best (fast cornner) case, i should not get hold violation in worst (slow cornner) case.
Hi guys can any one pls tell me how to define false path in ise.. i am having 2 clks slow and fast and i am facing some timing issue in them because of false path. so is there any way to mention a false path for signals which are giving errors with resp to clocks. thanks tama
In Razavi's book.The problem of 9.24 shows a opamp with two pair of input stage,a fast path in parallel wiht a slow path. What's the characteristics of this circuits? and Show me some papers about it ?
Time domain reflectometry works quite well, but implementing it is diifficult and expensive. If you have a digital storage oscilliscope, a fast pulse generator and a calculator you should be able to get a reasonable result. However, if the cable is really long, you will need to know its velocity factor. An easier solution is to use your brain! C
as far as i know, low-vt devices work faster but they consume more power due to subthreshold current leakage. high-vt transistors reduces this leakage significantly but its delay time will be longer than low-vt devices. that is why low-vt device are used in critical path (needs to be fast), whereas high-vt transistors can be employed on (...)
hello, while importing a design in encounter 4.2 , design is not taking up the slow.lib and fast.lib files, even when i am specifying rgt path in design import form, can any one tell why????????? i am getting errors like Modulel not present......, no physical library or wrong dimensions... i am working on 130nm tech ...
Hello Taisun, You can constrain with Generated clocks it is completely safe. You need to get the latency of the master clock, it will automatically perculate to lower level, Else you can constrain with set_max_delay option. You have to set a multi cycle path between fast and slow clock.
Hi, I would say that this structure is not a good one (I have read more than 500 papers about opamp design). There is a very fast path from input to output (from transistors M3 and M7) and also a very slow path thru transistors M10 and M12. The fast path is like a single-stage opamp, and the slow (...)
i have an error when trying to close the verilog text editor to compile using :wq cannot find ncvlog excutable from your path. Please updateyour path to point to the correct excutable or use vmsNcvLogExcutable variable to specify the excutable to use. any fast help plzzz.
in sta,if two clock domain is asyn ,we can set false path to them. if two clock domain is syn, maybe fast to slow,maybe slow to fast, how to constraint the path between them? i see a conculsion ,but i don't understand what it mean. just like in the picture.
Hi,all I used three different operating conditions to check timing , slow ,fast and on_chip_varations. so I did setup timing check . but the data path delay were different in those three conditions , why? I know the fast condition is different with the other two . but the slow and the on_chip_varations data path delay (...)
One: As far as i know, signal in 5GHz decreases faster than in 2.4GHz,why? Two: 802.11a, 802.11b ,802.11g's data rate decreases as the distance increase ,why? there exits some relationship? Three: throughput and data rate,their relationship? Four: What is 54g , and 802.11g?
As we all know, a signal with very fast rise time travel along a path and radiate to other traces or surfaces. The characteristic impedance of a wire in space is generally known to be on the order of 370 Ohms, which means the impedance along another unintended path could be in this range. I have a little confusion that why it does mean (...)