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12 Threads found on edaboard.com: Fault Simulator
This sounds as though you have two ground icons connected together by a plain wire. It is not a fault in the real world but I have seen it called an error by a simulator.
Hello, Our 160W two transistor forward converter simulaton (LTSpice) switches in a noisy and irregular manner when synchronous FETs are used with higher ?Qg?. (the ?synchronous fets? are the secondary side fets) This seems to me that it may be a fault of the simulator(?), because changing the synchronous FETs to an almost similar FET, with a s
I am working in an electronic simulator which is the replica of one of our truck. I am using vector canoe . My first task is to remove all the fault codes from the simulator and to be able to exchange messages . I am using CAN. Vector Canoe 8.1(SP6). Ecu's are not yet connected to the simulator, so I have to create virtual (...)
Hi all, I recently got to know about the free test generation/fault simulator tool called HITEC/proofs developed by university of illinois. I was wondering whether I will be able to install it on my personal laptop(ubuntu). Here is the webpage: Looking forward for your valuable help.
Hello all, I need some suggestions as to how to write a verilog code for stuck at 0 fault and analyse its power behavior using "Xilinx Power Estimator(XPE)... Thanks in advance :)
The scan chain need to be inserted by a Dft engine (generally include in synthesis tool). In the atpg tool, you could list all the fault and you could analyze which faults have not been reported by tetramax. The fault list are created based on the STD cell model.
It is unlikely to be the simulator's fault if the simulations don't match reality. Simulations are only as good as the models and realism of you circuit representation. Run the same circuit through a more expensive simulator with the same models and you will get exactly the same results. Keith
Shyam is correct. Your code works with a simulator so there must be a fault on your chip. Check your soldering also in case of some shorting between pins.
The typical input bias current of the LMV721 is 260nA but that is not enough to cause the problem. I just tried it with my simulator and the results don't look right. I suspect there is a fault in the Spice model. I will see if I can spot the problem, but you may want to try another opamp in the meantime or contact National Semiconductor. Kei
hello, i want to design a simulator for real time fault tolerant system but i don't know how to start can anybody help any reference or already designed simulator thanks in advance
Performing fault simulation lets you determine the test coverage obtained by an externally generated test pattern. For fault simulation, you need functional test patterns that have been developed to test the design and have been previously simulated in a logic simulator to verify correctness. The functional test patterns should contain the (...)
Hi, I had synthesis some logics and got a ATPG results. ATPG tool reports 99.8% fault coverage. And ATPG tools simulated by itself and reported no error. But I have differnet results between ATPG simulator and NC-verilog simulator. when I simulates with NC-verilog, next error messages are coming. I am very compilcated by this point. (...)