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Folded Cascode Compensation

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39 Threads found on edaboard.com: Folded Cascode Compensation
Attached is a folded cascode amplifier with a cascode compensation capacitors Cc. How does this circuit prevent the formation of the undesired zero (in the right half of the s-plane ) ? Please let me know a logical explanation .
Hi Safiya You use folded cascode design to save power and easier to compensate.
Specs; DC gain 60dB UGB 50MHz PM >60 VCC 2.5V I am working on this design and DC gain & UGB is already fulfilled the spec,but the PM is always around 30 deg. Because the sec pole is right at 63MHz and cannot be moved right(high freq). I know the sec pole coming from the folding point, but no matter I increase the current in the cascoded br
I have attached a picture of a folded cascode amplifier with class AB push pull stage. My question is regarding the SLEW time of the amplifier. During the 'internal slewing' when the compensation capacitors CM1, CM2 are being charged up, what is the status of the M4, M4C, M8A, M9A, M2C, M6 ? Do these mosfets operate in saturation or (...)
how to add 2nd stage on single ended folded cascode? i cant figure it out,, kindly tell me, its urgent. im getting gain of 72dB and 100MHZ + ug FREQ. SO HOW TO ADD CS AMP to increase gain to 100dB???? im using NMOS input folded cascode
u can proceed folded cascode with CS as the second stage this will give you the required dc gain. and it will meet the swing requirement also. you can keep miller compensation or cascode compensation for the stability.
in folded cascode compensation capacitor and load capacitor is you must use positive fedback gain cause high unity gain frequency and nice Phase Margine. - - - Updated - - - if you want increase the campensation capacitor,unity gain will be decrease.
Hi I wanna design an opamp (2 stage folded cascode) where can I find analysis of this opamp? I need to know poles,zeros,unity gain,... for designing? plz help me I wasnt able to find any book or paper.:cry::cry: tnx
I'm going to design a two stage folded cascode OTA. first stage is folded cascode(nmos input pair) to provide gain second stage is common source to increase the output range compensation is cascode compensation My question is in my circuit, how to find poles and (...)
Hello, I have an assignment for a DDA (Differential Difference Ampplifer) where Vo= A( (Vpp-Vpn) -( Vnp - Vnn)) Hence Vo= A Then I have two input different stage that then add before it gets into the folded cascode stage (Hope I am making sense) But I have the following specs Vdd= 1.8v Total current=150uA Vpn
Dear all, I am designing a high frequency integrator. The one i designed is as It has required magnitude frequency response but weird phase response, and when i connect the load capacitance the gain of magnitude curve
With a folded cascode of the first stage and common source as the second stage. How to calculate the slew rate? The value I calculated by Itail/Cc, that is the tail current of the differential divided by compensation capacitance, is far different than the one I simulated. Should we consider the miller effect here? It seems the variance (...)
i have designed a two stage opamp (used for a buffer, fck=15M, CL=12pF), the first stage is folded cascode, the second is common source, and i use cascode compensation to ensure frequency stability, now, i get the following simulation curve, when the input signal from 0.4 to 1.6, it settles well, but when the input signal (...)
i have designed a two stage fully differential opamp with hybrid ahuja compensation (that is, two compensation capacitor used in the two cascode nodes of each branch), the first stage is folded cascode, the second is common source, and the CMFB is continuous common mode feedback which have two input pairs, (...)
You have to be careful when you write expressions without referring to a specific topology cause it can be misinterpreted (as just happened) LvW, I think jimeece13's topology is a folded cascode amp, so he doesn't have a Miller cap (his compensation is done with CL). So, yes, the unity gain freq is given by fun = gm/(2*Π*CL). diemilio
with a carefully designed 1-stage folded cascode, you can achieve about 70-75dB (not far from what you need) and you could use gain boosting to gain some margin. In this case you have the advantage that you need no compensation. If you want to design a 2-stage opamp, try to read "An improved frequency compensation (...)
for me design a folded cascode with only a dominating node only, so you can have a large gain but you may not need to do compensation. if still cannot meet your requirement, then do 2 stage
Depending on the threshold voltage of your technology, it should not be too difficult to design a folded-cascode ota at 1.2V. I would at least try it since it will save you a lot of headaches with compensation. Moreover, you can also scale the coefficients of the modulator according to the output swing (just one more degree of freedom). (...)
i want to design a two-stage opamp with cascode compensation ,and the first stage is folded cascode structure, the requirements as follows: resolution:11 bit clock speed: 20M CL=2pF,Cs=Cf=1pF,DR=70dB,Vdd=3.3V,output swing= +/-1V then how to design the two-stage opamp step by step? how to choose the size of (...)
hi why miller compensation not required in folded cascode OTA? Thanks BHanu
Hi all, I am designing a two stage folded cascode opamp. Specification of load capacitor has very high range. The minimum load cap is 470pF and maximum is 100nF. I am finding it difficult to compensate this opamp. With 470pF load capacitor, the output node becomes second pole and a miller cap will help to compensate this. But with 100nF load ca
I successfully completed the classic 2 stage OpAmp design with Miller compensation, and am looking at advanced Op Amp designs. I started with folded cascode Opamp design and am in a confusion not knowing where to start. I went through Johns Martin, and Jacob Baker's books. Both seem totally different in the way folded (...)
Hi: I have a small question about this opamp compensation as shown below. the feedback is not shown but you can see C2 is used as the compensation cap. on the other hand, there is a RC filter (R1-C1) used at the output of the 1st stage folded-cascode amplifier. This block indeed improves the compensation (...)
for the three kind of opamp:telescopic cascode, folded cascode, and two stages opamp with differential input(five transistors) & common source output & miller compensation, what's the difference of them? for example, gain, output resistance,input common mode range, output swing, noise, speed, power consumption etc. how to (...)
if only for cap-load, you can use 1-stage folded-cascode architecture, if you need large dc gain, you can add gain-boosting to it. 300nF load, 100kHz bandwidth, gm~200mS sr=5v/ms, so tail current~1.5mA need large current and large w/l for input pair.
Generally, the two stage opamp maybe need compensation, because it has two high-impedance nodes as naalald said, and the folded cascode opamp does not , may be the book written by W.Sansen will be better for you to study
I want to design a folded cascode amplifier with gain>70dB. I can design it with gain=62db.please help me for increasing gain.
Hi, Why 3 stage? It's compensation is not easy to handle. I suggest two stage with a folded cascode in the first stage for it's input CM. If you hadn't need the 1.3 V output swing you could have reached the specs (e.g. the easy 60dB gain) with only one stage.
The one-stage folded cascode OTA normally need loading cap for compensation, but if I need extra cap for compensation, can I use MOSFET or nwell cap as this compensation cap? Because it will give smaller area with the same cap value.
Yes: folded cascode have dominat pole at the output because it is a voltage to current building block. But: The intermediate stage in the folded cascode create a secondary pole, sometimes called parasitic pole. It is made by the diffusion diode caps found at the current summing node and the gate-source cap of the final (...)
I'm designing a 2 stage op amp and I use folded-cascode as my 1st stage. 1. I think output resistance is // so, I want to match up with as much as I can. However, I saw from another tutorial that I should make the ro of M4 and M7 mat
The R of the RC puts an additional zero in the compensation network. This zero should be matched to a parasitic pole coming from the folded cascode. The M21/M22 have a transconductance (gm in DCOP result file) which make with the CGS and CSB and other caps there a parasitic pole. Because this pole is bias and tech dependend most often the R (...)
Hi: The BGR circuit could be designed for supply voltage down to 1.8-V, with approximately 400uA of current consumption, however the offset compensation amplifier for PSSR suppresion, need to be a folded cascode type to relax the voltage headroom limitation. Rgds
It is a folded cascode op-amplifier. It is basically a 2 stage op-amp so to ensure the stability of the op-amp when use in the feedback system, the pole-zero compensation which is Rz, Cc is done there. Slew rate is the measurement of how fast you output signal can change for a given input signal. Basically SL= I/CL, meaning that you need to (...)
The output impedance of a folded-cascode cannot be that low. Did you get your DC biasing correct?
I'm going to design a two stage folded cascode OTA. first stage is folded cascode(pmos input pair) to provide gain second stage is common source to increase the output range compensation is cascode compensation My question is in my circuit, how to decide the input (...)
how to start design of an opamp if settling time spec is given inspite of slew rate. because as for two stage or folded cascode opamp we start designing with slew rate and compensation/load capacitance to select the tail current. since the settling time is total time of slewing and linear settling we cannot write SR=(vdd+vss)/ts (...)
When i design a folded cascode OP AMP(Follow the step by the P.E.Allen 's book),The curve of Magnitude-frequence appear a peak at the vicinity of the second pole.Firstly I thought it maybe cause by the the right half plane zero,but I couldnot solute the issue after added the compensation capacitor and i think the problem may be cause
For that application you should use a switched capacitor CMF to save power. As about the arquitecture I would prefer an input stage folded cascode with a second stage output. The cascode compensation gives higer bandwith. Bastos