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133010 I could not view the internal signal even though I am using the formal format *ghw with , , , and Anyone ?
Good Day, i am a novice programmer and am trying to compiler a code for micro controller AT89C52 using a reference code but i keep running to an error which seems to be causing other errors. this is the code void timer1_ISR (void) interrupt1 //timer1 interrupt service routine { TR1=0; //stop the timer1 time_c
Hello, As suggested in previous posts, you should refer to some verilog textbook. you need to understand how a verilog module is instantiated and its ports are connected to other modules/signals. Any basic verilog tutorial should give you clarity to understand what is formal and actual port name in module instance. i.e. in your case LUT6 is a mo
Hello, I would like to know the best book for formal Verification for a complete newbie? Any useful links are also appreciated. Best,
Lambda/10 works, sure. There is no formal IEEE definition as far as I'm aware. The "size" is usually considered to be the radius of the smallest possible sphere that encloses the entire antenna.
hello all, pls help me to find out is reason for this. should i have to run "verify" command after that because ii'm not getting any answer. Info: Net i:/WORK/usb_link_ulpi/link_dbg is undriven. Info: Net i:/WORK/usb_link_ulpi/link_dbg is undriven. Info: Net i:/WORK/usb_link_ulpi/link_dbg is undriven. Info: Net i:/WORK/us
I am getting the following two errors: Error (10346): VHDL error at comparator_TestBench.vhd(17): formal port or parameter "beginGame" must have actual or default value Error (10784): HDL error at comparator.vhd(8): see declaration for object "beginGame" and both are related to assigning a default value for beginGame in my comparato
The majority of microcontroller families of current designs offer one or more UART, SPI, I2C and other interfaces, and could most likely handle your current design tasks. While there are many considerations when choosing a particular microcontroller, three of the primary concerns are: 1. The formal specifications and required tasks of the design.
formal verification is a very complex subject that a few people fully understand, and I have to admit I am not one of them. Fishing for compliments? Anyway, thanks for the profound explanation.
Hi all! I'm running formal equivalence on RTL to Gate-level netlist. One of the errors that i encountered is the reset DFF's of revised is connected directly to ground and in the golden the reset is connected to the GSR. However, when i used the option set flatten model -seq constant, the in-equivalence was gone. How was this happen? I really
Hai all, I am planning to start a vlsi startup in bangalore and presently making a broad plan of action for the startup. Major areas of focuses are in in-house developed formal Verification method and IP core any comments and suggestion are welcome....:arrow:
Hello, In the design which I am working on, I need to pass a std_logic_vector(15 downto 0) from a register in the top module to an input port of a sub module. I have done it in the following way: -----top_module---- signal ConfigMem_Wire : std_logic_vector(15 downto 0); {Register_module} register => ConfigMem_Wire
formal tools called property checkers can mathematically prove that, given an RTL design and some assumptions about the relationships of the input signals, an assertion will always hold true. If a counter example is found, the formal tool will provide details on the sequence of events that leads to the assertion violation. If this is true, do we
Hi, I am wanting to do a design in VHDL I am been mandated to use semi formal design methods such as Yourdon which does not map well to describing hardware. Which modern methods would people suggest and how to bridge the gap between Yourdon and modern methods?
I have no formal formation in electronic, but I do have some knowledge. I know what a flip flop is, but I don't want have to use clock to add. Why 8 bits? I don't know, I just thought that would be a good challenge and it's better to have more bits to do an ALU with more functions. But that's more a long shot. Anyway, I am not concern if the logi
Hi all! Im new on using the cadence tool COnformal Ultra LVR. It says that "Conformal LVR enables formal verification of the final SPICE netlist against the golden RTL or final gate-level netlist to ensure that the design taped out is functionally equivalent with golden RTL and the final gate-level netlist." My question is that what is (...)
If you are using DC to synthesize, it is preferred to use formality and not Conformal for formal verification. But it should be possible to get it passing with Conformal as well. Maybe some additional constraints might be required. You will need to find out that...
Hi, I get the following Modelsim error when compiling my design for simulation: "# ** Error: tx_and_replica.vhd(362): Actual (function call "to_sfixed") for formal "i_x" is not a globally static expression." The relevant code snippets are: 1) Port mapping: Line 362 is the s_tx_tmr conversion to signed fixed. U_ITPL_TTL_HIGH: li
I think the formal definition of the Mealey machine will directly lead to a mapping from present states x input alphabetes to next states and output alphabet, which can be coded in a ROM.
Conformal-LEC is a program that checks logic equivalency in formal verification which means the mathematical verification of the logic of a circuit. however i found test vectors when debug. why there is vector?
This is a real case. A timing ECO iteration added an extra inverter somewhere in the design. Hundreds of inverters/buffers have been added, it's impossible to check one by one to see which inverter is the extra one. Debugging with formal tools shows lots of support points causing the mismatches, but it doesn't help too much. What would you do if it
Hi. Coz I need to some stubborn clock gating setup violation, I made some clock gating cell clone. My question is how to do formak check then. Is there extra setting needed to be set in formal tool ? thanks!
I'm looking for a formal proof. For which statement? I know that some impedances show a rotation in s-plane, but not necessarily a spiral. Others have fixed coordinates or move linearly. So obviously you have to specify a class of impedances with the claimed behaviour.
Hi People more talking about the formal verification , it has gone to advanced level. Can someone help me on that. I am curious to know difference between formal verification and functional verification.
scan_chain_reordering will not create any issue as such (during PnR). Even though there will be change in flops in scan chain - however 1st flop & last from from that chain will be intact. so it will not create any issue in formality.
Here is a more formal definition. A ripple carry adder is implemented purely with a half-adder and multiple full adders. The maximum delay is through the carry signal path from the LSB to the MSB which "ripples" through all the adders. There is pretty much only one way to implement this type of adder. A carry look-ahead adder includes additional lo
Not exactly. You can add the registers after the combinational block in the RTL, and then enable register retiming to get it to balance it for you. See the Design Compiler Register Retiming Reference Manual. It can make formal Verification a bit harder though.
Hi there, 1. Learn formal verification say Equivalence Checking starting from small HDL programs. Always prefer to work on one tool at a time. (Quality, not Quantity matters). Per se, Start over with Cadence Conformal. 2. Equivalence Checking verifies the equivalence between two views say - RTL vs Netlist , RTL1 vs RTL2 , Netlist1 vs Netlist
Dear All This has been a matter of concern to me and i am sure to many of us, When we design a microwave structure in CST or HFSS we plot current or E/H field distribution on structure. Now we often require to extract the photo to be added to research paper or report and i dont know any method to extract high resolution image, the formal bmp etc a
Quick and discouraging disclaimer: I have 0 formal education in these matters, but here is my best attempt to solve this math problem This is way more complicated then it needs to be, but here was my train of thought in solving this. Step 1: Initially, forget about the 980 samples already taken, let's figure out how to sample 12
Forgive me, I'm sure there is a simple solution to this but I am still very much a beginner with VHDL and am learning as I go along for a Digital Design course I'm currently taking. I'm running into a weird compiling error and was hoping I could get some help sorting through this. I have pasted the testbench and code I am testing underneath. I woul
Last release I was working with was 2010.1. See 'formalpro.log' in the launch directory. At the end of the file you will see '- Designs are EQUIVALENT - ' or other message. Directory 'formalpro.cache' contains 'logs' and 'reports'.
Hi All, I cannot get access to the Proceedings of the 11th International Conference on Wireless Communications (Wireless'99) held in Calgary, Alberta on 12-14 July 1999 through the formal (library\IEEE Explore, etc.) channels. I am looking for a specific paper by R. Tingley and K. Pahlavan. Can somebody please refer me to a site\company from
Hello, I tried to feed the output clocks directly into my counter code. This gave the following error: Parameter clk0/clk90 of mode in cannot be associated with a formal port of mode out. My questions are what does this error mean? It means that you have an input that you are trying to drive as an output.
I am working with an interface that I have been told is 1.8V HSTL (High Speed Transceiver Logic), however the JEDEC committee only defines a 1.5V HSTL. :-? Does anyone know if there is an official standard for 1.8V HSTL? Where did it originate from? I am looking for some formal definitions of its operation, in particularly with reference to VOHm
You have brought up the warning by specifying enum type for the formal parameter and supplying an integer literal. Although not all compilers will flag out a warning in this case, it seems reasonable, enforcing usage of enum constants rather than equivocal numbers. If you don't want it, specify a numeric type for modenum.
Hi Dynamic verification is when you actually run a testcase and you can see in the waveform of different signals that they are changing their values during the running of the testcase..(they may take a constant value in some exceptional cases). formal verification ...from what I have encountered by using IFV is that it is assertion based and used f
when i simulate the Example design after modification i usually have this error : formal has no actual or default value. :-| Any suggestion :???: That means you havent connected it in your testbench or design example. All inputs without a default value, which would look like this: p0_m
1. Near Din_in_unit type conversion doesnt match type std_logic_vector 2. Actual of formal output DOUT_reg cannot be expression What do you mean with type conversion? The actuals must be signals (and might use type conversion in addition). But there are no signals connected to the data ports in your instantiation, only types and a
Hi seniors,I am a newbie in cellular communication.I'm now studying independently (wthout any formal teacher) on GSM functional architecture.I want to ask about the correlation about 64Kbps used in GSM and LAPD protocol with BSC functionality and mapping on simple analogy and reccomended Ebook will be great :) thanks before
Hi, The problem is I need to find the surface potential where in the electric fields are elliptic (Fringing fields). I tried to find the solution when there were one dielectric by using con-formal mapping technique which i succeeded. But the problem here is there are two dielectrics permittivity of 1 >permittivity of 2. Therefore There is a
The big problem of formal verivication. Because, such tool (like Mentor FromalPro or Synopsys formality) compares input logic for each register between RTL and gate-level netlist. If you asked Synthesis to re-balance logic, the input logic for some registers will be different. For Synopsys formality, you can use side-file .svf, which is (...)
hello there i have a problem while i try to run ifv i source the ifv_setup which located at: ifv/bin folder and there what it says: ifv_setup : (c) Copyright 1995-2009 Cadence Design Systems, Inc. bash: /home/edatools/INCISIV-10.20.026/tools/ifv/bin/ifv_setup: line 11: syntax error near unexpected token ``/bin/uname`' bash: /home/edatools/I
Some formal training
Dear Friends, I have 5+ yrs of experience in Synthesis, Physical Synthesis, Low Power, DFT, Placement , Pre-CTS Optimization, formal verification, Flow / Methodology setup, ECO, Timing Closure / analysis, QoR and TCL Coding. I am looking for a change now - either in design companies or EDA product companies. I am currently based in India and
Lint is RTL syntax checks. formal verification is connectivity check against spec. formal verification can be extended to further also.
I've dabbled a bit with microprocessors and even taught an online course in microprocessor interfacing (which is concerned more with peripherals than coding). However, I do not have any formal training or on the job training (or at home hobbyist training) in microprocessors such as the PIC or HC12. I have written limited code for both in C and a
Syntax is the formal grammar rules, expressed in Backus-Naur Form (BNF), usually listed in Annex A of the language reference manual (LRM). The BNF is used by compilers to determine what each token in the source code represents (i.e. keyword, identifier, operator, string comment). Semantics is everything else after the source code is parsed - does t
Doing a simple man on the variable gives a detailed explanation for this variable does. I am not sure why you want to post this in the forum. > man simplified_verification_mode DESCRIPTION Setting this variable to true adjusts optimization inside the tool to prioritize formal verification compatibility over QoR. This enables
The Algorithmic State Machine (ASM) method is a method for designing finite state machines. It is used to represent diagrams of digital integrated circuits. The ASM diagram is like a state diagram but less formal and thus easier to understand. An ASM chart is a method of describing the sequential operations of a digital system.