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A better solution!? How about using the STANDARD template for a resetable FF. Maybe you should go find the Altera and Xilinx documents on writing synthesizable code. @lh- , Hear what they are telling you; the the right thing to do is to take advantage of templates provided by fpga manufacturers, which have either th
synthesizable VIP (or accelerated VIP as some vendors call it) are IPs that can be synthesized into emulators/fpga to support verification. advantage of using them is you can provide real time test stimulus to your synthesized design in FPAG/ASIC. You can search accelerated VIP and you can find many examples of the same. Hope this helps.
If you are interested in additional learning material on VHDL and fpga Development, I am offering a free coupon to this group only. Take advantage! Check it out and sign up for free. Lifetime Access on this material. Hope it helps!
The solution is not completely obvious, there are different options: - Implementing a common data bus for all ADCs, sequentially accessing the data advantage: less fpga pins Disadvantage: more complex logic - Individual data lines for each ADC advantage: Simple logic, fast access without sequences. Some ADC (...)
AT90USB162 is an USB enabled AVR microcontroller, not a fpga. In so far it's surely not "compatible with Impulse CoDeveloper". To understand the possible advantage of HDL code generator tools, you need to know the basics of HDL programming.
By reading the documentation of the fpga vendor? Anyways, Xilinx & Altera both offer DDS cores. So if you use Xilinx you already had your answer in post #2. If you use Altera you now have your answer in post #4. And if you use another fpga vendor then post #5 is an excellent place to mention which fpga you are using. ;-)
ADF7023 control and data communication goes through a SPI interface, it can be surely perfromed by a fpga. But seriously speaking, I don't see a particularly advantage of using a fpga instead of a microcontroller. Initialization and radio state control involves sequential procedures that can be implemented more straightforward in a (...)
hi i want to calculate gate count from slice count in xilinx fpgas like virtex 7 and kintex 7 someone tell me to calculate area / slice of nand 2*1 if its right please tell me how can i measur slice of nand gate please help me how can i calculate them tnx
Hello, i am implementing a project with USB1T11A and Cyclone IV fpga. The tranceiver got two operating modes. Differential and single ended. Someone can point me out the advantage of each mode? With the singled ended i would have one less line in the schematic, but whats the tradeoff? Best regards, LR
People around me always use the async in most cases can it be called a bad design? not exactly, as Tricky said - synchronize the reset and use it as async. input to registers; the advantage of such approach is that the async. reset is an independent input to fpga cell so doesn't consume data in
Thanks a lot for the response. but the link you provided is about fpga. I want to understand this in ASIC flow. Thanks Jay
The first question should be, which function is required for the controller of sensor network, are there any advantages of a fpga implementation compared to a processor? Even if there is no advantage for the product design, a fpga may offer specific feature during development and test of a system. But that's something you (...)
Hi Doesn't Mentor anymore support fpga advantage? There is no name of fpga advantage in the related page. ASIC and fpga HDL Design Creation and Synthesis Solutions - Mentor Graphics Has Mentor released a new integrated program instead of fpga advantage?
I have installed fpga advantage 8.1. This error is shown and the program is terminated. 60841 I use win7. I also tried run as win xp compatibility but dosn't work.
Oversampling process is not working at 80 MHz with this baudrate. I think, it can work well, but some intelligency is needed in modifying the design. fpga designs have the advantage, that you're not restricted to standard oversampling ratios of e.g. 16. Alternatively, you can use a fractional frequency divider, which is utilized
Hi..I just saw this thread...I came to know that fpga advantage is not compatible with win 7. I heard it can run only on win xp. The error comes because of this reason.
Helo ihadser to resolve this problem open the command window (cmd.exe). verify that the promt get you dto drive C type the following with the quot. marks: md "c:\users\Ihab\Application Data\HDL Designer Series\hds_user" verify that the directory was created by typing: cd "c:\users\Ihab\Application Data\HDL Designer Series\hds_user" if the prom
Just a couple of semi-random thoughts... Optimize design to best fit the resources of your target fpga. When designing for spartan-3 (LUT4) you might do things a bit different than for spartan-6 (LUT6). Use best practices that avoid code that makes your HDL synthesize to something that is larger/slower than necessary. Case in point the [url=h
Hi, Just a opinion survey thrown to the floor. fpga has the advantage of parallelism and datastreaming under a lower clock speed(less power usage) while GPU have higher clockspeed and utilise float point calculation(better accuracy) though suffer from low throughput with memory access requirement and high power usage. With the introductio
You may need a program like fpga advantage or something like that. Check out this page: ASIC and fpga HDL Design Creation and Synthesis Solutions - Mentor Graphics
can you specify few points , why fpgas advantage and disadvantages are compared with DSP ? Is fpga compatible enough????
I think surely. Even in fpga or CPLD design process we use Mealy or Moore models to design the circuit. One advantage is that, nowadays, most of the complex part of solving Mealy or Moore models are done by a computer software.
what's your goal? student trial? commercial trial? in case student trial, I believe the quartus/xilinx tool are efficient to generate the fpga image. in commercial case, it's better to by the license, if you require such of tool.
as we know that microprocessors are now a days with a lot of clock speed... where as we see that fpga's are restricted to MHzs then why we say that fpga's are more effective??? Every calculation will cost one cycle of MCU at least. But fpga can do parallel calculation. So for some complex data stream processing, such
what is the advantage of implementing FFT function on fpga instead of CPLD
the same functionality which we get in fpga we can get in microcontrollers also..rite..? and like fpga in vlsi fiels,what hardware kit is used in embedded systems for verification purposes?
I used this tool 5 years back through fpga advantage. What I recall is after you synthesize it generates a gate list that can be viewed graphically as well. No certain settings. -- Amr Ali
Hi, Many fpgas have flip-flops built into the input and output buffers to optimize the timing in and out of the chip. Along with these special I/O buffers will be an optimization to enable or disable the packing of these registers into the I/O. Figure 16.8 illustrates the concept of packing registers into the I/O buffers. [url=image
There is none advantage. Usually one gets an USB circuit and attaches it to fpga. A problem remains to implement in fpga some FIFO buffer and FSM to build some protocol implementation.
Hello there. I have created and simulated a project (a simple counter) with Mentor fpga advantage with Precision synt. Now I have to generate a .jed file (programming file) for a xilinx CPLD (XPLA3). Please (I'm new in fpga adv, but I must use it, I know quite well Xilinx ISE) could you indicate me the steps to follow to generate programming (...)
In order to do some useful work in real world using fpga you will have to download your bit stream to it. It will be connected to various resources. If you don't assign pins on your own, synthesis tool will assign it for you and you will have to connect other devices as suggested by hardware (PCB) would be designed accordingly. However,
hi all i am making an FIR filter for practicing VHDL what i need is : work with fixed point like addition and mul i use fpga advantage 7.2 and i have xilinx 10.1 also any suggestions??
In fpga,The global set/rest signal GSR,three-state signal GTS are high active, why? What advantage is it?
hi all i made an arrat 16 row and size of each row 8 bit. it will be a rom not a ram so i have no read signal in that block so i intialize them i tried 2 different codes subtype elements is std_logic_vector(7 downto 0); type arr is array (0 to 15) of elements; signal Arr_data : arr :=(x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
hi all i have fpga advantage 7.2 i want to simulate systemC module how can i simulate it on modelsim here is the code i want to simulate // // Created: // by - Ahmed.UNKNOWN (AHMED) // at - 02:39:23 26/12/2008 // // using Mentor Graphics HDL Designer(TM) 2005.3 (Build 75) // #include SC_MODULE(new
I've Design my project in Mentor Graphics/fpga advantage's a really good S.W. but now I need to implement These modules in my design using Mega functions and IPs......: 1.One or Two Soft CAM/RAM Memroy 3.Ethernet Interface How can I port my project from fpga advantage to Quartus or ISE? or How can I (...)
I need to implementing a CAM(Content Address Memory) in an fpga Based Design. I've Found it in Quartus but my project is in the fpga advantage now I need your help what can I do? is it possible to find similar IP for fpga advantages? is it possible to temporarily move my project to Quartus and then back...
Hi all, We are located to the west of Toronto and are seeking somebody with experience using DxDesigner and PADS-PCB. Knowledge of ORCAD would be an advantage. IPC accreditation would be an advantage. Successful applicant will be able to work directly with senior engineering staff on layouts for low frequency high power systems, fpga and (...)
fpga advantage (fomer renior) is a software packge. it has modelsim, leonardo and precision rtl. you can use these software alone, but with fpga advantage you can manage your (large) design better.
Ah, Ok. That's different. I guess it's something like fpga advantage :D I haven't used HDL design before but if I find anything useful I'll send it right away good luck :)
if you have fpga advantage then it's implemented already there
all the examples you said are digital so why don't you use VHDL with fpga advantage also from mentor which is great in digital
A traffic light controller sounds like the job for a simple low-cost microcontroller, unless your goal is to learn fpga design. An fpga can give extremely high performance if you design a parallel processing algorithm that takes advantage of the fpga's architecture. If you simply drop a microprocessor core into the (...)
Microblaze is a 32-bit soft processor core, which means that it isn't a hardware part of the fpga it's cost efficient, highly configurable and supported by EDK
a simple tool is provided in Samir Palnitkars' CD..When u buy that book, he gives u a demo tool..Else u can try out fpga advantage tool ..U can get it free fom any cracked site
Hi, The two main PLD families are : CPLDs & fpgas. --CPLD (Complex PLD) : is a good solution if we have a small design, generally used as glue logic, or to load an fpga at power up, it has the advantage to keep it's configuration even when power is down. --fpga(Field Programable Gate Array) : is widly used in many (...)
Dear all.. I want to get into the fpga world.. I selected the fpga Kit (XILINX Spartan-3E Kit) and now i wanna start to burn my design to it... What i wonder about is, i have a VHDL code, written on fpga advantage, i wanna burn it on my fpga, can i use fpga advantage (...)
Could any one help me in the designing of digital controlled delay unit circuit for my Delay Locked loop Circuit As i am not able to implement uisng a Verilog Simulation tool ,fpga advantage PRO. Send me any ALL DIGITAL DELAY LOCKED LOOP CIRCUIT ,as i am not able to find any complete circuit in the internet or books . Also how to i
Hi I'm abeginner with verilog and i use fpga advantage and modelSim when i want to simulate the following code output counte give me unknown Is there is setting in ModelSim i have to set in order to simulate correctly? module firstseq (clk, reset, enable, count); input clk, reset, enable; output count; reg count; alw
Hai, I am doing a DLL design ,can anyone send me some fully/all digital DLL circuits or papers,and websites which show the entire simulation and layout flow for DLL circuits. I am going to use the VERILOG HDL simulation tool (fpga advantage PRO)..