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354 Threads found on edaboard.com: Fpga Advantage

I need an FPGA Advantage 5.5 licence file if you can help me

Hi Haytham26, I really need it, I formatted my PC last weekend and now fpgadv 5.3 doesn't work :cry:. ( I am using the files I got in this post ) What I need is a valid 'license.dat' file which includes a license for VSIM in Modelsim, that is the only pr
   ASIC Design Methodologies and Tools (Digital) :: 02.12.2002 09:41 :: maestor :: Replies: 3 :: Views: 2427

Mentor's Fpga advantage EVA

You can download the evalution and request the 45-day temp. license to see the function
   Software Links :: 10.03.2003 02:20 :: calvinhorng :: Replies: 0 :: Views: 585

help: about using the Mentor Graphic's FPGA Advantage 5.4

Hi friend, I had gotten some training on fpga advantage.but I have no the s/w at hand now, so I can't repeat the error you run in. But I think whether you could run/simulate your design in a Modelsim enviorment separately not invoke it in the HDL Designer.
   PLD, SPLD, GAL, CPLD, FPGA Design :: 17.04.2003 14:10 :: arena_yang :: Replies: 1 :: Views: 1937

link to download FPGA advantage 5.3b demo version

hello everybody, I search a link (ftp, irc, web) to download fpga advantage 5.3 demo version. Please Thank you
   PLD, SPLD, GAL, CPLD, FPGA Design :: 26.10.2003 17:04 :: nega :: Replies: 0 :: Views: 773

Problems compiling designs using FPGA Advantage FOR FRAMES.

Having trouble compiling a small RAM for my Masters project, iam using the FOR FRAME to create an 8x8 RAM cell. Heres the problem the design compiles at UNI using fpga advantage 5.3, however at home using version 6.2 the generated output is slightly different and the errors are listed below. ** Error: F:/VHDL/MVSD3_ILP/crane/hdl1/ram
   ASIC Design Methodologies and Tools (Digital) :: 18.01.2004 02:28 :: gezzas525 :: Replies: 2 :: Views: 750

FPGA Advantage and VHDL COnfiguration file

Hi, I?m a newbie on VHDL (and on advantage also ) I?m using fpga advantage 6.2 and I?m trying to use VHDL configuration file to select the desired architecture for synthesis. My configuration file is: configuration top_entity_config of top_entity is for struct for all : reg use entity pci_acp.reg(v1_0); (...)
   PLD, SPLD, GAL, CPLD, FPGA Design :: 30.04.2004 13:03 :: AMCC :: Replies: 0 :: Views: 1128

FPGA Advantage with Node locked Licence without network conn

I have been running fpga advantage 6 on both windows and linux however ive just got a laptop and there seems to be noway of running it unless its connected to a network i.e. the wired gigabit or the Intel wireless. It isnt a prolem under windows as i got away with using virtual NIC adapters via VMWARE GSX server and then mapping the licence to tha
   Linux Software :: 25.06.2004 15:31 :: gezzas525 :: Replies: 2 :: Views: 745

What about Mentor FPGA Advantage ?

Is anyone using Mentor fpga advantage ? Its design capture tools look so powerful, is it as good as seems? I'd like to know your comments...
   PLD, SPLD, GAL, CPLD, FPGA Design :: 01.07.2004 08:10 :: Regnum :: Replies: 8 :: Views: 1344

FPGA Advantage with Xilinx tools

I chose Mnetor graphics because this is the first tools in my university and so my experience has born with them. However I found the response for my question: iI have to integrate the coregen lib in fpga advantage as proposed in appsnotes/fpgaadvantage/UsingCoreGen.pdf Hope this helps someone[
   PLD, SPLD, GAL, CPLD, FPGA Design :: 20.07.2005 16:58 :: dainis :: Replies: 6 :: Views: 1549

Jedec file with FPGA advantage

Hello, I have a quesiton about the jedec file, I am using fpga advantage "Mentor Graphics" and I want to produce an output file with jedec extension to program my PAL cypress PALCE20V8. anybody know this? Thanks
   PLD, SPLD, GAL, CPLD, FPGA Design :: 18.10.2006 15:53 :: lightofspace :: Replies: 1 :: Views: 547

What is the FPGA Advantage ?

fpga advantage (fomer renior) is a software packge. it has modelsim, leonardo and precision rtl. you can use these software alone, but with fpga advantage you can manage your (large) design better.
   ASIC Design Methodologies and Tools (Digital) :: 28.03.2008 16:58 :: amir81 :: Replies: 13 :: Views: 1218

FPGA advantage 7.2, modelsim with systemC

hi all i have fpga advantage 7.2 i want to simulate systemC module how can i simulate it on modelsim here is the code i want to simulate // // Created: // by - Ahmed.UNKNOWN (AHMED) // at - 02:39:23 26/12/2008 // // using Mentor Graphics HDL Designer(TM) 2005.3 (Build 75) // #include SC_MODULE(new
   PLD, SPLD, GAL, CPLD, FPGA Design :: 26.12.2008 02:13 :: mr_byte31 :: Replies: 0 :: Views: 626

fpga advantage 7.2 - violation due to integer use in VHDl

hi all i made an arrat 16 row and size of each row 8 bit. it will be a rom not a ram so i have no read signal in that block so i intialize them i tried 2 different codes subtype elements is std_logic_vector(7 downto 0); type arr is array (0 to 15) of elements; signal Arr_data : arr :=(x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
   PLD, SPLD, GAL, CPLD, FPGA Design :: 28.12.2008 17:25 :: mr_byte31 :: Replies: 5 :: Views: 660

FPGA ADVANTAGE + XILINX ISE

Hello there. I have created and simulated a project (a simple counter) with Mentor fpga advantage with Precision synt. Now I have to generate a .jed file (programming file) for a xilinx CPLD (XPLA3). Please (I'm new in fpga adv, but I must use it, I know quite well Xilinx ISE) could you indicate me the steps to follow to generate programming (...)
   PLD, SPLD, GAL, CPLD, FPGA Design :: 04.08.2009 15:32 :: mauriziomontesi :: Replies: 1 :: Views: 1378

FPGA Advantage v7.2..

what's your goal? student trial? commercial trial? in case student trial, I believe the quartus/xilinx tool are efficient to generate the fpga image. in commercial case, it's better to by the license, if you require such of tool.
   PLD, SPLD, GAL, CPLD, FPGA Design :: 20.08.2010 17:22 :: rca :: Replies: 5 :: Views: 806

FPGA advantage 7.2 on win7?

Helo ihadser to resolve this problem open the command window (cmd.exe). verify that the promt get you dto drive C type the following with the quot. marks: md "c:\users\Ihab\Application Data\HDL Designer Series\hds_user" verify that the directory was created by typing: cd "c:\users\Ihab\Application Data\HDL Designer Series\hds_user" if the prom
   ASIC Design Methodologies and Tools (Digital) :: 26.04.2011 22:50 :: Gandalf :: Replies: 3 :: Views: 818

fpga advantage 8.1 installation error

i have tried installing fpgadv 8.1 in windows 7 and i am not able to do it .the error it says is that the software is unable to migrate user preferences.if any body knows it please tell me what do they mean and thank you:D
   Software Problems, Hints and Reviews :: 24.03.2011 14:39 :: gigo_gigo88 :: Replies: 4 :: Views: 1048

FPGA Advantage running error

I have installed fpga advantage 8.1. This error is shown and the program is terminated. 60841 I use win7. I also tried run as win xp compatibility but dosn't work.
   Software Problems, Hints and Reviews :: 29.08.2011 17:11 :: spman :: Replies: 0 :: Views: 260

Last version of FPGA Advantage

Hi Doesn't Mentor anymore support fpga advantage? There is no name of fpga advantage in the related page. ASIC and fpga HDL Design Creation and Synthesis Solutions - Mentor Graphics Has Mentor released a new integrated program instead of fpga advantage?
   PLD, SPLD, GAL, CPLD, FPGA Design :: 31.08.2011 12:17 :: spman :: Replies: 0 :: Views: 227

What software is typically used for Xilinx FPGA development?

There are 3 contendors in this field; 1- synopsys fpga express, 2- synplicity and 3- mentor fpga advantage. I looked into this a while back and picked fpga express over the other two simply because synopsys was smart enough to build a mini version of primetime into this tool so in case you designed a 100 mhz (...)
   PLD, SPLD, GAL, CPLD, FPGA Design :: 16.02.2003 05:52 :: rakko :: Replies: 39 :: Views: 6236

What is a good starting point for FPGA design?

What is the good starting point for the fpga design ? which tool , which book , which hardware etc. thanks
   PLD, SPLD, GAL, CPLD, FPGA Design :: 07.02.2003 08:25 :: mystery :: Replies: 33 :: Views: 9013

HOw to split bus in FPGA Adv using "Block Diagram' ent

Hi all, I could not manage to split the bus using fpga advantage in the "Block Diagram" entry. Below is an example ---------------------------------------------------------- module aaa0(a0,.......); input a0; ......... endmodule ---------------------------------------------------------- module aaa1(a1,......) input a1;
   PLD, SPLD, GAL, CPLD, FPGA Design :: 03.10.2003 17:19 :: always@smart :: Replies: 3 :: Views: 1180

Latest FPGA Advantage for Linux?

as I know mentor have release fpgaDV 6.1 and 6.2 for linux but u must request the new releases and they provide u the download link/password. also i think they provide update for their customers. PS: there is no linux version for versions before 6.1. BEST!
   Linux Software :: 20.12.2003 20:56 :: goodboy_pl :: Replies: 2 :: Views: 1536

Need Advice on starting the FPGA

If you need to learn in a short time, I suggest altera's fpga. Quartus II V4.1 and Modelsim V6.0 should be the best combination for synthesis and simulation within the development process. Cyclone or Stratix would be the best platform to test your fpga design. Xilinx's fpga may need more time to learn in depth but provides more flexibility. (...)
   PLD, SPLD, GAL, CPLD, FPGA Design :: 20.10.2004 09:17 :: cawan :: Replies: 6 :: Views: 723

Getting started in the FPGA world!! [A Question]

fpga advantage can compile (synthesize) your HDL, but you still need Xilinx ISE to do the place-and-route and to download into the device. See diagram at bottom of page: ISE can do everything by itself. I recommend starting with ISE before adding fpga advantage into your work fl
   PLD, SPLD, GAL, CPLD, FPGA Design :: 28.12.2006 10:15 :: echo47 :: Replies: 5 :: Views: 1804

HOW TO DESIGN UART IN FPGA

i know nothing , how can i design UART in fpga, using HDL.thanks
   PLD, SPLD, GAL, CPLD, FPGA Design :: 01.07.2007 14:31 :: fan2005 :: Replies: 5 :: Views: 2282

Which FPGA Vendor/Software for my Design

You have to start looking first to the hardware (fpga devices) and after you can start thinking in the SW. If you are a not familiar with fpgas I'll recommend you to use the SW tools from the HW manufacturer (Xilinx or Altera). I don't remember for Altera Quartus but for Xilinx (when using MicroBlaze or the PPC) you also need the EDK, an environ
   PLD, SPLD, GAL, CPLD, FPGA Design :: 07.08.2008 12:00 :: zape :: Replies: 4 :: Views: 648

CAM/RAM MadulWare(or MegaFunction) for FPGA Advantages

I need to implementing a CAM(Content Address Memory) in an fpga Based Design. I've Found it in Quartus but my project is in the fpga advantage now I need your help what can I do? is it possible to find similar IP for fpga advantages? is it possible to temporarily move my project to Quartus and then back...
   PLD, SPLD, GAL, CPLD, FPGA Design :: 10.08.2008 18:31 :: sadid :: Replies: 3 :: Views: 531

PLI - designing a test bench in C

Yes, I know. Did you try fpga advantage? I just want to compose the tester in C. And I will connect the tester and the UUT(Unit under Test). The whole entity should be called TEST BENCH, right? Therefore, I think your method is right. Thank you!!
   Professional Hardware and Electronics Design :: 13.06.2001 15:11 :: Joyee :: Replies: 3 :: Views: 2540

How to work with FPGA cores?

Why IP cores? I think, good IP cores can significantly reduce your time to market. This is true for both SOC and fpga design.
   ASIC Design Methodologies and Tools (Digital) :: 15.01.2003 11:33 :: Ohh :: Replies: 14 :: Views: 1359

How to simulate Post-P&R?

check the xilinx web site it has very good docummentation (App Note and tutorials) for fpga advantage flow and interation with xilinx tools Al Farouk
   ASIC Design Methodologies and Tools (Digital) :: 14.01.2003 07:37 :: Al Farouk :: Replies: 4 :: Views: 1195

Where can I get UMS design kit for ADS?

Latest ***** software ftp download cad/cam/cae/eda/optical ***** ftp download software Part of Software ---------------------------------------------------------------------- Do not put any replies here. WE will not check any replies here on the forum. If you are interested in or want to get more software list ,please go cax2
   Software Problems, Hints and Reviews :: 07.05.2011 03:33 :: ghji90 :: Replies: 3 :: Views: 3282

Is it better to use DSP or FPGA ?

What is recommended between using a DSP or fpga configured as DSP? Would the discussion be application specific or general? Kindly give reasons for your opinions. Thank you. bimbla.
   PLD, SPLD, GAL, CPLD, FPGA Design :: 09.03.2003 11:25 :: bimbla :: Replies: 18 :: Views: 2347

model\sim Vs Active\H\DL

My opinion is fpga advantage is the counterpart to active hdl, which includes design entry, simulation and synthesis together by bundling hdl designer, model sim and leonardo, and also more powerful than active hdl. rguo
   ASIC Design Methodologies and Tools (Digital) :: 29.04.2003 03:11 :: rguo :: Replies: 13 :: Views: 2076

Using 802.11a MAC in a FPGA?

Hi, Has anybody tried a 802.11a MAC in a fpga? Can somebody tell me the expected gate complexity for such a core, which Xilinx VirtexII chip may be suffecent??
   PLD, SPLD, GAL, CPLD, FPGA Design :: 03.04.2003 07:46 :: it_boy :: Replies: 7 :: Views: 1620

how much this EDA Tools Cost

hi all, can any one tell me the price of a perpetual license of these eda tools for windows or linux Synopsys VCS Synopsys Desgin Compiler Synopsys Prime time Synopsys Hspice Cadenec LDV Cadence AMbit Buildgtes cadence silicon ensemble Modelsim modelsim+ Hdl designer series leonardo spectrum fpga advantage Aldec Active HDL
   ASIC Design Methodologies and Tools (Digital) :: 10.04.2003 09:47 :: eda_wiz :: Replies: 13 :: Views: 4514

What should a beginner do?

I recommend Men*or's fpga advantage. Also you can try Synplicity's synplify.
   PLD, SPLD, GAL, CPLD, FPGA Design :: 26.06.2003 10:27 :: my_garden :: Replies: 7 :: Views: 1544

Mentor's FPGA advantage config datasheet of new release FA61

if you want to get it , you can read this cofiguration. good luck.
   PLD, SPLD, GAL, CPLD, FPGA Design :: 03.07.2003 06:04 :: ljkong :: Replies: 0 :: Views: 590

Need Fpga advantage 6.1 for linux

Where can we get this?
   Linux Software :: 18.07.2003 15:45 :: Dick Hou :: Replies: 0 :: Views: 990

Difference b/w FPGA & CPLD

It is basic,go to
   PLD, SPLD, GAL, CPLD, FPGA Design :: 04.06.2004 17:23 :: alphi :: Replies: 22 :: Views: 17333

FPGA Advantage 5.4 libraries dont work in 5.2 help!

I can open vhd and state machine however It crashes when I attemp to open blockdiagrams. I think Iam gona need version 5.4 urgently but I cant find it anywhere, ive tried version 6.2 however the license I have doesnt include the modelsim so iam stuck. KLEOS
   Linux Software :: 11.01.2004 21:53 :: gezzas525 :: Replies: 0 :: Views: 655

Linux Install of FPGA Advantage 6.1/6.2

Is there an install guide for this? What env variables will be needed. I will be using the windows license, do I have to modify this. Any help will be appreciated. KLEOS
   Linux Software :: 12.01.2004 00:26 :: gezzas525 :: Replies: 5 :: Views: 1221

schematic convert into fpga?

In the first place questions are: 1) Which kind of schematic 2) Which kind of fpga ? It is best to use manufacturer library to create a fpga from schematic. Why? First of all you can simulate your design and see if it is working as you expected, in short it will save you a lot of time. Guessing work is rarely a good thing.. Secondly
   PLD, SPLD, GAL, CPLD, FPGA Design :: 20.01.2004 17:59 :: henrik2000 :: Replies: 4 :: Views: 901

Altera release MAX II CPLD (or FPGA?)

yes it's an fpga but with a flash prom into this chip ... to make the same advantage that a CPLD. but you don't forget, fpga need time to program himself by a flash
   PLD, SPLD, GAL, CPLD, FPGA Design :: 11.03.2004 11:26 :: :: Replies: 12 :: Views: 1667

Mentor Graphics ModelSim5.7d Fatal Error

I get a # 0 0x0057ac02: ' + 0xd2b52' # 1 0x0057adc2: ' + 0xd2d12' # Corrupt Call Stack ** Fatal: (SIGSEGV) Bad pointer access. Closing vsim. ** Fatal: vsim is exiting with code 211. error when i'm invoking ModelSim from fpga-advantage. It works on its own so there is no licence iss
   Software Problems, Hints and Reviews :: 23.03.2004 13:32 :: ucassbo :: Replies: 4 :: Views: 1573

Where can I download Renoir software?

the newest version of hds is hds6.2 include:hds,modelsim,spectrum,and rtl pricision it's fpga-advantage 6.2
   Software Links :: 26.05.2004 17:15 :: CatKing :: Replies: 5 :: Views: 1473

Beginners questions about FPGA and microcontroller core

hi all I'm very much new to fpgas. there r few querries which i think u can help me with that. firstly like i have the 8051 microcontroller core n i would like to to programe that fpga after incorporating that core to fpga. how that would work? seondly what is the advantage of using fpga n what is (...)
   PLD, SPLD, GAL, CPLD, FPGA Design :: 02.04.2004 08:13 :: ashishjindal76 :: Replies: 4 :: Views: 991

could vhdl + verilog codes are syntsisable ???????

i have a piece of VHDL code which I synsithsis and everything worked properly.. now I am writing verilog code for asynchrous Tr-Rx.. I want to include my VHDL code with verilog? does it possible..?? can i add boths, netlist and download it on fpga.. is there any EDA tool for this? TIA, tom
   PLD, SPLD, GAL, CPLD, FPGA Design :: 13.05.2004 18:54 :: tom_hanks :: Replies: 7 :: Views: 1116

what is the advantage of Fpga?

Hi.i am a beginer in fpga design.i have worked with microcontrollers and i have found them very usefull.i can not find a topic that fpga's can individually do them. You can also use fpga's to emulate your preferred Microcontoller. For example you can implement an AVR MCU as an IP-core in a small part of the fpga and still
   PLD, SPLD, GAL, CPLD, FPGA Design :: 10.07.2004 22:56 :: ME :: Replies: 15 :: Views: 5747

More Linux EDA AMD64 Software released, the flow has started

As I was predicting from the beggining of 2004 we would see major EDA titles appearing: Mentor Calibre Mentor Modelsim and I hear fpga advantage is on the way, the big one will be Cadence IC 5 suite. KLEO
   Linux Software :: 12.07.2004 20:48 :: gezzas525 :: Replies: 0 :: Views: 647