148 Threads found on edaboard.com: Fpga Advantage
I really need it, I formatted my PC last weekend and now fpgadv 5.3 doesn't work :cry:.
I am using the files I got in this post
What I need is a valid 'license.dat' file which includes a license for VSIM in Modelsim, that is the only pr
ASIC Design Methodologies and Tools (Digital) :: 02.12.2002 03:41 :: maestor :: Replies: 3 :: Views: 2655
You can download the evalution and request the 45-day
temp. license to see the function
Software Links :: 09.03.2003 20:20 :: calvinhorng :: Replies: 0 :: Views: 589
I had gotten some training on fpga advantage.but I have no the s/w at hand now, so I can't repeat the error you run in.
But I think whether you could run/simulate your design in a Modelsim enviorment separately not invoke it in the HDL Designer.
PLD, SPLD, GAL, CPLD, FPGA Design :: 17.04.2003 08:10 :: arena_yang :: Replies: 1 :: Views: 2068
I search a link (ftp, irc, web) to download fpga advantage 5.3 demo version. Please
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.10.2003 11:04 :: nega :: Replies: 0 :: Views: 919
Having trouble compiling a small RAM for my Masters project, iam using the FOR FRAME to create an 8x8 RAM cell.
Heres the problem the design compiles at UNI using fpga advantage 5.3, however at home using version 6.2 the generated output is slightly different and the errors are listed below.
** Error: F:/VHDL/MVSD3_ILP/crane/hdl1/ram
ASIC Design Methodologies and Tools (Digital) :: 17.01.2004 20:28 :: gezzas525 :: Replies: 2 :: Views: 942
I?m a newbie on VHDL (and on advantage also )
I?m using fpga advantage 6.2 and I?m trying to use VHDL configuration file to select the desired architecture for synthesis.
My configuration file is:
configuration top_entity_config of top_entity is
for all : reg
use entity pci_acp.reg(v1_0); (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 30.04.2004 07:03 :: AMCC :: Replies: 0 :: Views: 1329
I have been running fpga advantage 6 on both windows and linux however ive just got a laptop and there seems to be noway of running it unless its connected to a network i.e. the wired gigabit or the Intel wireless. It isnt a prolem under windows as i got away with using virtual NIC adapters via VMWARE GSX server and then mapping the licence to tha
Linux Software :: 25.06.2004 09:31 :: gezzas525 :: Replies: 2 :: Views: 864
I'm trying to use the fpga advantage tools from Mentor Graphics in order to develop Xilinx fpga based systems.
However at present time I'm not able to use the libraries of ISE Xilinx in advantage.
IS there someone that can provide me some link to a document that explain how to integrate the libraries of (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 19.07.2005 10:15 :: Giox :: Replies: 6 :: Views: 1812
fpga advantage is a synthesis tool ,its output will be .edif file.
U need to use cypress tool in order to generate final programming file(.jed).
PLD, SPLD, GAL, CPLD, FPGA Design :: 24.10.2006 01:35 :: alt007 :: Replies: 1 :: Views: 678
can anyone tell me what is fpga advantage? and
how to work on fpga advantage?
do anyone have manual ?
ASIC Design Methodologies and Tools (Digital) :: 13.03.2008 08:17 :: sachinmaheshwari :: Replies: 13 :: Views: 1562
i have fpga advantage 7.2
i want to simulate systemC module
how can i simulate it on modelsim
here is the code i want to simulate
// by - Ahmed.UNKNOWN (AHMED)
// at - 02:39:23 26/12/2008
// using Mentor Graphics HDL Designer(TM) 2005.3 (Build 75)
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.12.2008 20:13 :: mr_byte31 :: Replies: 0 :: Views: 735
i made an arrat 16 row and size of each row 8 bit.
it will be a rom not a ram so i have no read signal in that block so i intialize them
i tried 2 different codes
subtype elements is std_logic_vector(7 downto 0);
type arr is array (0 to 15) of elements;
signal Arr_data : arr :=(x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.12.2008 11:25 :: mr_byte31 :: Replies: 5 :: Views: 733
Hello there. I have created and simulated a project (a simple counter) with Mentor fpga advantage with Precision synt. Now I have to generate a .jed file (programming file) for a xilinx CPLD (XPLA3). Please (I'm new in fpga adv, but I must use it, I know quite well Xilinx ISE) could you indicate me the steps to follow to generate programming (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 04.08.2009 09:32 :: mauriziomontesi :: Replies: 1 :: Views: 1515
what's your goal?
student trial? commercial trial?
in case student trial, I believe the quartus/xilinx tool are efficient to generate the fpga image.
in commercial case, it's better to by the license, if you require such of tool.
PLD, SPLD, GAL, CPLD, FPGA Design :: 20.08.2010 11:22 :: rca :: Replies: 5 :: Views: 963
to resolve this problem open the command window (cmd.exe).
verify that the promt get you dto drive C
type the following with the quot. marks:
md "c:\users\Ihab\Application Data\HDL Designer Series\hds_user"
verify that the directory was created by typing:
cd "c:\users\Ihab\Application Data\HDL Designer Series\hds_user"
if the prom
ASIC Design Methodologies and Tools (Digital) :: 26.04.2011 16:50 :: Gandalf :: Replies: 3 :: Views: 1223
Hi..I just saw this thread...I came to know that fpga advantage is not compatible with win 7. I heard it can run only on win xp. The error comes because of this reason.
Software Problems, Hints and Reviews :: 07.07.2011 03:35 :: srinpraveen :: Replies: 4 :: Views: 1371
I have installed fpga advantage 8.1.
This error is shown and the program is terminated.
I use win7. I also tried run as win xp compatibility but dosn't work.
Software Problems, Hints and Reviews :: 29.08.2011 11:11 :: spman :: Replies: 0 :: Views: 342
Doesn't Mentor anymore support fpga advantage? There is no name of fpga advantage in the related page.
ASIC and fpga HDL Design Creation and Synthesis Solutions - Mentor Graphics
Has Mentor released a new integrated program instead of fpga advantage?
PLD, SPLD, GAL, CPLD, FPGA Design :: 31.08.2011 06:17 :: spman :: Replies: 0 :: Views: 343
There are 3 contendors in this field; 1- synopsys fpga express, 2- synplicity and 3- mentor fpga advantage. I looked into this a while back and picked fpga express over the other two simply because synopsys was smart enough to build a mini version of primetime into this tool so in case you designed a 100 mhz (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 15.02.2003 23:52 :: rakko :: Replies: 39 :: Views: 6509
I could not manage to split the bus using fpga advantage in the "Block Diagram" entry. Below is an example
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.10.2003 11:19 :: always@smart :: Replies: 3 :: Views: 1349
as I know mentor have release fpgaDV 6.1 and 6.2 for linux but u must request the new releases and they provide u the download link/password.
also i think they provide update for their customers.
PS: there is no linux version for versions before 6.1.
Linux Software :: 20.12.2003 14:56 :: goodboy_pl :: Replies: 2 :: Views: 1734
fpga advantage can compile (synthesize) your HDL, but you still need Xilinx ISE to do the place-and-route and to download into the device. See diagram at bottom of page:
ISE can do everything by itself. I recommend starting with ISE before adding fpga advantage into your work fl
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.12.2006 04:15 :: echo47 :: Replies: 5 :: Views: 2221
if you have fpga advantage
then it's implemented already there
PLD, SPLD, GAL, CPLD, FPGA Design :: 02.07.2007 13:37 :: salma ali bakr :: Replies: 5 :: Views: 2807
I've these softwares:
and this is my design features:
Designing a Router (MPLS one) so:
1.need two soft core processor (32bit)
2.has enough IP and MegaCore
3.easy to use Block Diagramming approach
4.I've a HighVolum High Performance fpga
5.Ethernet IP Mega Coer
6.has enough and verity (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 02.08.2008 08:58 :: sadid :: Replies: 4 :: Views: 761
I need to implementing a CAM(Content Address Memory) in an fpga Based Design.
I've Found it in Quartus but my project is in the fpga advantage
now I need your help what can I do?
is it possible to find similar IP for fpga advantages?
is it possible to temporarily move my project to Quartus and then back...
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.08.2008 12:31 :: sadid :: Replies: 3 :: Views: 628
Yes, I know. Did you try fpga advantage? I just want to compose the tester in C. And I will connect the tester and the UUT(Unit under Test). The whole entity should be called TEST BENCH, right? Therefore, I think your method is right.
Professional Hardware and Electronics Design :: 13.06.2001 09:11 :: Joyee :: Replies: 3 :: Views: 2709
check the xilinx web site it has very good docummentation (App Note and tutorials) for fpga advantage flow and interation with xilinx tools
ASIC Design Methodologies and Tools (Digital) :: 14.01.2003 01:37 :: Al Farouk :: Replies: 4 :: Views: 1286
My opinion is fpga advantage is the counterpart to active hdl, which includes design entry, simulation and synthesis together by bundling hdl designer, model sim and leonardo, and also more powerful than active hdl.
ASIC Design Methodologies and Tools (Digital) :: 28.04.2003 21:11 :: rguo :: Replies: 13 :: Views: 2308
Has anybody tried a 802.11a MAC in a fpga?
Can somebody tell me the expected gate complexity for such a core, which Xilinx VirtexII chip may be suffecent??
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.04.2003 00:46 :: it_boy :: Replies: 7 :: Views: 1907
can any one tell me the price of a perpetual license of these eda tools for windows or linux
Synopsys Desgin Compiler
Synopsys Prime time
Cadence AMbit Buildgtes
cadence silicon ensemble
modelsim+ Hdl designer series
Aldec Active HDL
ASIC Design Methodologies and Tools (Digital) :: 10.04.2003 03:47 :: eda_wiz :: Replies: 13 :: Views: 5782
I recommend Men*or's fpga advantage. Also you can try Synplicity's synplify.
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.06.2003 04:27 :: my_garden :: Replies: 7 :: Views: 1679
if you want to get it , you can read this cofiguration.
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.07.2003 00:04 :: ljkong :: Replies: 0 :: Views: 705
Where can we get this?
Linux Software :: 18.07.2003 09:45 :: Dick Hou :: Replies: 0 :: Views: 1087
I can open vhd and state machine however It crashes when I attemp to open blockdiagrams. I think Iam gona need version 5.4 urgently but I cant find it anywhere, ive tried version 6.2 however the license I have doesnt include the modelsim so iam stuck.
Linux Software :: 11.01.2004 15:53 :: gezzas525 :: Replies: 0 :: Views: 769
Is there an install guide for this?
What env variables will be needed. I will be using the windows license, do I have to modify this.
Any help will be appreciated.
Linux Software :: 11.01.2004 18:26 :: gezzas525 :: Replies: 5 :: Views: 1403
In the first place questions are:
1) Which kind of schematic
2) Which kind of fpga ?
It is best to use manufacturer library to create a fpga from schematic.
First of all you can simulate your design and see if it is working as you
expected, in short it will save you a lot of time. Guessing work is rarely a good thing..
PLD, SPLD, GAL, CPLD, FPGA Design :: 20.01.2004 11:59 :: henrik2000 :: Replies: 4 :: Views: 1188
it's an fpga but with a flash prom into this chip ... to make the same advantage that a CPLD.
but you don't forget, fpga need time to program himself by a flash
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.03.2004 05:26 :: :: Replies: 12 :: Views: 1850
I get a
# 0 0x0057ac02: ' + 0xd2b52'
# 1 0x0057adc2: ' + 0xd2d12'
# Corrupt Call Stack
** Fatal: (SIGSEGV) Bad pointer access. Closing vsim.
** Fatal: vsim is exiting with code 211.
error when i'm invoking ModelSim from fpga-advantage.
It works on its own so there is no licence iss
Software Problems, Hints and Reviews :: 23.03.2004 07:32 :: ucassbo :: Replies: 4 :: Views: 1812
the newest version of hds is hds6.2
include:hds,modelsim,spectrum,and rtl pricision
it's fpga-advantage 6.2
Software Links :: 26.05.2004 11:15 :: CatKing :: Replies: 5 :: Views: 1473
I'm very much new to fpgas. there r few querries which i think u can help me with that. firstly like i have the 8051 microcontroller core n i would like to to programe that fpga after incorporating that core to fpga. how that would work? seondly what is the advantage of using fpga n what is (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 02.04.2004 01:13 :: ashishjindal76 :: Replies: 4 :: Views: 1154
fpga tools able to perform mixed HDL synthesis, and in order to perform simulation, you need a simulator that having this Mixed HDL feature.. Modelsim having this feature, but you need to purchase a license from Modeltech. Altera quartus able to perform the simulation with mixed hdl, but i believe it is very very slow...
PLD, SPLD, GAL, CPLD, FPGA Design :: 16.05.2004 14:07 :: skynet :: Replies: 7 :: Views: 1273
Is anyone using Mentor fpga advantage ?
Its design capture tools look so powerful, is it as good as seems?
I'd like to know your comments...
PLD, SPLD, GAL, CPLD, FPGA Design :: 01.07.2004 02:10 :: Regnum :: Replies: 8 :: Views: 1586
Hi.i am a beginer in fpga design.i have worked with microcontrollers and i have found them very usefull.i can not find a topic that fpga's can individually do them.
You can also use fpga's to emulate your preferred Microcontoller.
For example you can implement an AVR MCU as an IP-core in a small part of the fpga and still
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.07.2004 16:56 :: ME :: Replies: 15 :: Views: 6955
As I was predicting from the beggining of 2004 we would see major EDA titles appearing:
and I hear fpga advantage is on the way, the big one will be Cadence IC 5 suite.
Linux Software :: 12.07.2004 14:48 :: gezzas525 :: Replies: 0 :: Views: 758
Hi, iam using UMC 0.18u standard cell library in leonardo spectrum via fpga advantage. Iam not clear on the process of the flow. After synthesising a design I want to then obtain a real model to simulate in modelsim i.e. with delays etc.. some how using the .sdf format. Ive tryed various things but I cant seem to obtain the timing information, e
ASIC Design Methodologies and Tools (Digital) :: 09.08.2004 07:10 :: gezzas525 :: Replies: 0 :: Views: 690
Evreryone have their own pros and cons...
for matehmatical operation appliation/ signal processing... u can choose DSP and for high freq operation obviously fpga is better... and one more advantage of fpga is its cheaper....and interfacing with ADC , DAC is also easier
PLD, SPLD, GAL, CPLD, FPGA Design :: 07.09.2004 00:07 :: jay_ec_engg :: Replies: 3 :: Views: 1415
People here mentioned features, timing required for implementation, and characterized them especially cawan gave a very good insight.
What I would like to mention is "the price , the cost". If you system X ravibg, assuming speed issues etc... are resolved, can be built just using microcontrollers (see cawan explanation) it will be cheaper build
Electronic Elementary Questions :: 08.11.2004 20:05 :: djalli :: Replies: 16 :: Views: 33024
fpga 40 MHz? Modern fpgas are more like 500 MHz, if you design carefully.
The big advantage of fpga is you can reconfigure the entire device in milliseconds.
Electronic Elementary Questions :: 17.02.2005 05:52 :: echo47 :: Replies: 5 :: Views: 1718
i have used ment0r's fpga advantage b4, it is very good graphic entry tool..
ASIC Design Methodologies and Tools (Digital) :: 24.03.2005 05:58 :: always@smart :: Replies: 5 :: Views: 997
There is no essential difference at RTL simulation. For functional verfication, asic and fpga will give you the same simulation result, but huge distinguish at gate level.
ASIC Design Methodologies and Tools (Digital) :: 11.04.2005 07:58 :: soccer :: Replies: 5 :: Views: 835