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148 Threads found on edaboard.com: Fpga Advantage
Hi Haytham26, I really need it, I formatted my PC last weekend and now fpgadv 5.3 doesn't work :cry:. ( I am using the files I got in this post ) What I need is a valid 'license.dat' file which includes a license for VSIM in Modelsim, that is the only pr
You can download the evalution and request the 45-day temp. license to see the function
Hi friend, I had gotten some training on fpga advantage.but I have no the s/w at hand now, so I can't repeat the error you run in. But I think whether you could run/simulate your design in a Modelsim enviorment separately not invoke it in the HDL Designer.
hello everybody, I search a link (ftp, irc, web) to download fpga advantage 5.3 demo version. Please Thank you
Having trouble compiling a small RAM for my Masters project, iam using the FOR FRAME to create an 8x8 RAM cell. Heres the problem the design compiles at UNI using fpga advantage 5.3, however at home using version 6.2 the generated output is slightly different and the errors are listed below. ** Error: F:/VHDL/MVSD3_ILP/crane/hdl1/ram
Hi, I?m a newbie on VHDL (and on advantage also ) I?m using fpga advantage 6.2 and I?m trying to use VHDL configuration file to select the desired architecture for synthesis. My configuration file is: configuration top_entity_config of top_entity is for struct for all : reg use entity pci_acp.reg(v1_0); (...)
I have been running fpga advantage 6 on both windows and linux however ive just got a laptop and there seems to be noway of running it unless its connected to a network i.e. the wired gigabit or the Intel wireless. It isnt a prolem under windows as i got away with using virtual NIC adapters via VMWARE GSX server and then mapping the licence to tha
I chose Mnetor graphics because this is the first tools in my university and so my experience has born with them. However I found the response for my question: iI have to integrate the coregen lib in fpga advantage as proposed in appsnotes/fpgaadvantage/UsingCoreGen.pdf Hope this helps someone[
hi , fpga advantage is a synthesis tool ,its output will be .edif file. U need to use cypress tool in order to generate final programming file(.jed). regards alt007
can anyone tell me what is fpga advantage? and how to work on fpga advantage? do anyone have manual ?
hi all i have fpga advantage 7.2 i want to simulate systemC module how can i simulate it on modelsim here is the code i want to simulate // // Created: // by - Ahmed.UNKNOWN (AHMED) // at - 02:39:23 26/12/2008 // // using Mentor Graphics HDL Designer(TM) 2005.3 (Build 75) // #include SC_MODULE(new
hi all i made an arrat 16 row and size of each row 8 bit. it will be a rom not a ram so i have no read signal in that block so i intialize them i tried 2 different codes subtype elements is std_logic_vector(7 downto 0); type arr is array (0 to 15) of elements; signal Arr_data : arr :=(x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
Hello there. I have created and simulated a project (a simple counter) with Mentor fpga advantage with Precision synt. Now I have to generate a .jed file (programming file) for a xilinx CPLD (XPLA3). Please (I'm new in fpga adv, but I must use it, I know quite well Xilinx ISE) could you indicate me the steps to follow to generate programming (...)
what's your goal? student trial? commercial trial? in case student trial, I believe the quartus/xilinx tool are efficient to generate the fpga image. in commercial case, it's better to by the license, if you require such of tool.
Helo ihadser to resolve this problem open the command window (cmd.exe). verify that the promt get you dto drive C type the following with the quot. marks: md "c:\users\Ihab\Application Data\HDL Designer Series\hds_user" verify that the directory was created by typing: cd "c:\users\Ihab\Application Data\HDL Designer Series\hds_user" if the prom
Hi..I just saw this thread...I came to know that fpga advantage is not compatible with win 7. I heard it can run only on win xp. The error comes because of this reason.
I have installed fpga advantage 8.1. This error is shown and the program is terminated. 60841 I use win7. I also tried run as win xp compatibility but dosn't work.
Hi Doesn't Mentor anymore support fpga advantage? There is no name of fpga advantage in the related page. ASIC and fpga HDL Design Creation and Synthesis Solutions - Mentor Graphics Has Mentor released a new integrated program instead of fpga advantage?
There are 3 contendors in this field; 1- synopsys fpga express, 2- synplicity and 3- mentor fpga advantage. I looked into this a while back and picked fpga express over the other two simply because synopsys was smart enough to build a mini version of primetime into this tool so in case you designed a 100 mhz (...)
Hi all, I could not manage to split the bus using fpga advantage in the "Block Diagram" entry. Below is an example ---------------------------------------------------------- module aaa0(a0,.......); input a0; ......... endmodule ---------------------------------------------------------- module aaa1(a1,......) input a1;
as I know mentor have release fpgaDV 6.1 and 6.2 for linux but u must request the new releases and they provide u the download link/password. also i think they provide update for their customers. PS: there is no linux version for versions before 6.1. BEST!
Dear all.. I want to get into the fpga world.. I selected the fpga Kit (XILINX Spartan-3E Kit) and now i wanna start to burn my design to it... What i wonder about is, i have a VHDL code, written on fpga advantage, i wanna burn it on my fpga, can i use fpga advantage (...)
i know nothing , how can i design UART in fpga, using HDL.thanks
I've these softwares: 1.ISE 9.4 2.Quartus 7.2ps 3.fpga advantage and this is my design features: Designing a Router (MPLS one) so: 1.need two soft core processor (32bit) 2.has enough IP and MegaCore 3.easy to use Block Diagramming approach 4.I've a HighVolum High Performance fpga 5.Ethernet IP Mega Coer 6.has enough and verity (...)
I need to implementing a CAM(Content Address Memory) in an fpga Based Design. I've Found it in Quartus but my project is in the fpga advantage now I need your help what can I do? is it possible to find similar IP for fpga advantages? is it possible to temporarily move my project to Quartus and then back...
Yes, I know. Did you try fpga advantage? I just want to compose the tester in C. And I will connect the tester and the UUT(Unit under Test). The whole entity should be called TEST BENCH, right? Therefore, I think your method is right. Thank you!!
check the xilinx web site it has very good docummentation (App Note and tutorials) for fpga advantage flow and interation with xilinx tools Al Farouk
My opinion is fpga advantage is the counterpart to active hdl, which includes design entry, simulation and synthesis together by bundling hdl designer, model sim and leonardo, and also more powerful than active hdl. rguo
Hi, Has anybody tried a 802.11a MAC in a fpga? Can somebody tell me the expected gate complexity for such a core, which Xilinx VirtexII chip may be suffecent??
hi all, can any one tell me the price of a perpetual license of these eda tools for windows or linux Synopsys VCS Synopsys Desgin Compiler Synopsys Prime time Synopsys Hspice Cadenec LDV Cadence AMbit Buildgtes cadence silicon ensemble Modelsim modelsim+ Hdl designer series leonardo spectrum fpga advantage Aldec Active HDL
I recommend Men*or's fpga advantage. Also you can try Synplicity's synplify.
if you want to get it , you can read this cofiguration. good luck.
Where can we get this?
I can open vhd and state machine however It crashes when I attemp to open blockdiagrams. I think Iam gona need version 5.4 urgently but I cant find it anywhere, ive tried version 6.2 however the license I have doesnt include the modelsim so iam stuck. KLEOS
Is there an install guide for this? What env variables will be needed. I will be using the windows license, do I have to modify this. Any help will be appreciated. KLEOS
In the first place questions are: 1) Which kind of schematic 2) Which kind of fpga ? It is best to use manufacturer library to create a fpga from schematic. Why? First of all you can simulate your design and see if it is working as you expected, in short it will save you a lot of time. Guessing work is rarely a good thing.. Secondly
yes it's an fpga but with a flash prom into this chip ... to make the same advantage that a CPLD. but you don't forget, fpga need time to program himself by a flash
I get a # 0 0x0057ac02: ' + 0xd2b52' # 1 0x0057adc2: ' + 0xd2d12' # Corrupt Call Stack ** Fatal: (SIGSEGV) Bad pointer access. Closing vsim. ** Fatal: vsim is exiting with code 211. error when i'm invoking ModelSim from fpga-advantage. It works on its own so there is no licence iss
the newest version of hds is hds6.2 include:hds,modelsim,spectrum,and rtl pricision it's fpga-advantage 6.2
hi all I'm very much new to fpgas. there r few querries which i think u can help me with that. firstly like i have the 8051 microcontroller core n i would like to to programe that fpga after incorporating that core to fpga. how that would work? seondly what is the advantage of using fpga n what is (...)
Hi. fpga tools able to perform mixed HDL synthesis, and in order to perform simulation, you need a simulator that having this Mixed HDL feature.. Modelsim having this feature, but you need to purchase a license from Modeltech. Altera quartus able to perform the simulation with mixed hdl, but i believe it is very very slow...
Is anyone using Mentor fpga advantage ? Its design capture tools look so powerful, is it as good as seems? I'd like to know your comments...
Hi.i am a beginer in fpga design.i have worked with microcontrollers and i have found them very usefull.i can not find a topic that fpga's can individually do them. You can also use fpga's to emulate your preferred Microcontoller. For example you can implement an AVR MCU as an IP-core in a small part of the fpga and still
As I was predicting from the beggining of 2004 we would see major EDA titles appearing: Mentor Calibre Mentor Modelsim and I hear fpga advantage is on the way, the big one will be Cadence IC 5 suite. KLEO
Hi, iam using UMC 0.18u standard cell library in leonardo spectrum via fpga advantage. Iam not clear on the process of the flow. After synthesising a design I want to then obtain a real model to simulate in modelsim i.e. with delays etc.. some how using the .sdf format. Ive tryed various things but I cant seem to obtain the timing information, e
Evreryone have their own pros and cons... for matehmatical operation appliation/ signal processing... u can choose DSP and for high freq operation obviously fpga is better... and one more advantage of fpga is its cheaper....and interfacing with ADC , DAC is also easier
People here mentioned features, timing required for implementation, and characterized them especially cawan gave a very good insight. What I would like to mention is "the price , the cost". If you system X ravibg, assuming speed issues etc... are resolved, can be built just using microcontrollers (see cawan explanation) it will be cheaper build
fpga 40 MHz? Modern fpgas are more like 500 MHz, if you design carefully. The big advantage of fpga is you can reconfigure the entire device in milliseconds.
hi akrlot, i have used ment0r's fpga advantage b4, it is very good graphic entry tool.. regards, smart
There is no essential difference at RTL simulation. For functional verfication, asic and fpga will give you the same simulation result, but huge distinguish at gate level.