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3 Threads found on edaboard.com: Full Adder Using Decoder
the image below showing how to implement a full adder using a the image F1 is Sum and
F2 is Carry
If the input is 011 that means A is 0, B is 1 and C = 1
If we add 0 0 1 in binary it will give 1 as carry and 0 as sum
Elementary Electronic Questions :: 09-19-2011 11:47 :: Jakes9x :: Replies: 0 :: Views: 980
Hello every one
i need your help in VHDL .
actually i need a code to design a full adder using a decoder ..
and thank you for such great forum ...
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-05-2010 16:01 :: Student89 :: Replies: 1 :: Views: 1407
sorry for misleading u... i am using the HDL code n do on CPLD/FPGA...
the hardware generated(synthesis output) is just basic gates.... only OR, AND, XOR gates are use(like in my code).... no decoder required
for ur the output of decoder there are alwasy single '1' and others are '0'...
input (s1,s2) output (q3,q2,q1,q0
Elementary Electronic Questions :: 09-27-2005 10:33 :: sp :: Replies: 14 :: Views: 30977