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147 Threads found on Functional Verification
Hi all, I am trying to do function verification using System Verilog. I have DUT developed in Verilog. The DUT is very complex. I would like to run multiple test on this DUT, from batch mode. The compilation and elaboration of the DUT takes long time in the whole simulation process. So I am wondering is there a way I can compile, elaborate
you should do a functional simulation to test your code. elsif set ='1' and (rising_edge(clk)) then ... and a timing analysis. Are you sure your code can be implemented in an CPLD (see above)? Consider debouncing your buttons. why are you setting your temporary signals assynchronously wit
Hello I have users with unsupported OS who have asked for the cadence package. They want to run it on a virtual machine. I want to manage their expectation. Has anyone experienced running simulations/test on virtual environment? What was your experience? My concern is whether cadence software will run as they expect (like that on a desktop/se
I am not sure what you actually want. I tried to write testbench but the design i am testing is very big and not fully known to me. So i was told to test few new functionality. Here, as I have understood you want to do functional verification of a design. For this you need to manually write a good test-bench using a HDL. In the 2nd
Corner cases here refers to functional verification. Whenever you start FV, you know which are the direct cases. But there are cases which you do not anticipate. You may need a lot of expertise on the functionality of the core in order to think of this case. These cases are called as corner cases.
Since we are moving towards ever complex designs year after year, does this not mean that since SystemVerilog with its advanced capabilities for verification is fully capable of functional coverage, we should now only emphasize SystemVerilog which can be used for synthesis as well as verification and do away with VHDL? Also, since SystemC (...)
The main topic is functional verification of ICs The web site is Here presented are: 1) Anouncement 2) Registration form 3) Program Orgcommittee.
This is not a tool. It is a bus functional is useful in verification..U can use it..
VLSIGuru Training Insitute is starting a new batch of VLSI Training in SV & UVM based functional verification. Below are details. Website: Course duration: 17 Weeks Start date: 13/Dec/2014 Fee: 25K Feedback on course: We have put up all our students phone numbers on our website. Please talk to them and get the feedback. htt
Thank you for your help. I was wondering if you can provide more information on how you created and used the bus functional model. I am trying to make sure that I am in right path... I googled it, I found a document from Xilinx that suggests using "Create/Import User Peripheral" (in XPS) to develop BFM simulation, which helps to create a new EDK I
Hi People more talking about the formal verification , it has gone to advanced level. Can someone help me on that. I am curious to know difference between formal verification and functional verification.
BFM : Bus functional Model
Tarang EDA has launched Cloud based VHDL functional verification tool to quickly with many new features which are not possible in Desktop/Offline Tools. No Bulky Installations Fastest Simulation Work as Teams Work from anywhere Platform Independent You can try it on
If the purpose of your FPGA design is only functional verification - why do you insist on running at such a high frequency? Just synthesize your final design on the FPGA and make sure it functions properly. Than do a thorough timing analysis on your ASIC synthesis tool. With your RTL code being the same, everything should work properly.
But it is. SystemVerilog for RTL is approaching 50% of non-FPGA designs. Pure Verilog usage has begun to decline and VHDL has remained relatively flat. See this study from 2012. The main barriers for Syste
I'm going to assume that you are asking why behavioral models versus transistor-level models for analog circuits for functional verification... Transistor-level models (SPICE models) provide high fidelity results but SPICE simulations are very compute intensive and therefore take quite sometime to run. And, when SPICE models are mixed with digital
Hello all, Please list the all critical points and challenges of design Flow and verification(Front end). Regards cam
hello sir i am using VCS tool,so now i want to do coverage (functional verification) so specify me the procedure to be carried out to do coverage driven functional verification. specify the respective commands and if possible scripts.
how does Intel or ARM for example verify their architectures before designing them .. I mean testing them as blocks with actual programs without having to start the design .. to verify that these architectures are functional in the way they are expected or to find out the expected DMIPS or something like that ..
What makes you think that it is even possible to change functionality by changing drive strength ????
Hi all, while doing formality between PRE layout and POST layout netlist in functional mode i.e scan enable is tied to ''0'',the formal verification is passing in flatten mode.But in hierarchical mode there are many failing modules.the modules are failing because reordering of logic by BACK_END Team is it necessary in Hierarchical mode of
For digital ASIC: RTL, Gate-level simulation and functional verification - IES (Waveform viewer - simvision), formal verification - IEF Logic Synthesis - RC Compiler Layout Synthesis - SOC Encounter For analog ASIC: Schematic + Layout : Virtuoso Simulation : MMSIM
front-end: rtl design, functional verification, lint analysis back-end: logic synthesis (basic, dft, bsd), ATPG, formal verification, STA, physical synthesis (floorplan, CTS, P&R, parasite extraction), physical verification
Hi, Here is book, I would like suggest, Writing testbenches: functional verification of HDL models By Janick Bergeron verification is an art. Thinking process for verification is way different than design. This book has helped me lot for switching between Design to verification. You atleast make sure you (...)
Hi, I use ConceptHDL how Schematic Entry for PCB Design under linux O.S.. I am developing am Hardware Design Flow and I would like to know if I can use Verilog (mixed-signal simulation version) to develop a first functional verification of my board becouse in linux there are same problems to use AMS Simulator (PSPICE). Can you help me? Do you kn
Dear Group, I am developer of TCL for EDA project, presenting TCL usage in Synthesis, STA, DFT and functional verification. 63805 Please find the project under "Freeware" menu at SPARKEDA : Design verification Solutions Best Regards, -Alexander
just some add up. 1) Simulation is one way of verification and there are other ways to verify a design, such as LVS, formal verification, etc. 2) Corner case can have many meanings. In functional verification, corner case can be the test cases which is not covered by general test cases. In Synthesis, corner has a special (...)
How does one functionally verify a netlist synthesized using the RTL Compiler? Please give steps and associated commands. Thanks.
Hi All, In a directed testcase environment with no support for functional coverage embedded in the verification environment.what are the criteria that needs to be considered for sign off of functional verification of a chip. The functional coverage is done manual in my case.having said that how to make (...)
Weekend SystemVerilog Course (VSV) CVC is launching its highly successful 2 days certificate course on functional verification using SystemVerilog with a project in one of the following domains. ? Networking ? Communication ? Image Processing While the basic 2-days class is ideal for working professionals looking to upgrade their (...)
I have posted this in Elementary forum, but thought that it's more relevant to here -- I would like to do verification on a mixed-signal design, but have a problem when netlisting functional views. Look forward to kind help and replies. Thanks in advance. I have written functional views for analog blocks and tried Verilog XL. In (...)
Dear All, I would like to do verification on a mixed-signal design, but have a problem when netlisting functional views. Look forward to your kind help and replies. Thanks in advance. I have written functional views for analog blocks and tried Verilog XL. In Verilog Netlisting Options, I have put "behavioral (...)
Have anyone used the oregano mc8051 core? Recently I have a project related to microcontroller, and I find mc8051 meets my requirements. The functional verification with modelsim is good, but when I synthesis it with altera cynclone 2 device, all seems fine but the CPL bit, say CPL P3.1, P3.1 just holds it value the first time it's set! Would it be
Weekend SystemVerilog Course (VSV) CVC is launching its highly successful 2 days certificate course on functional verification using SystemVerilog with a project in one of the following domains. ? Networking ? Communication ? Image Processing While the basic 2-days class is ideal for working professionals looking to upgrade their (...)
Formal verification (FV) techniques ensure 100% functional correctness and they are more reliable and cost effective, less time consuming. The main concept of FV is not to simulate some vectors, instead prove the functional correctness of a design. In Formal verification process Design Under Test (DUT) is compared with (...)
please elaborate ur question.. WHy u want to do RTL Vs RTL equivalence checking?. Do u want verify functional equivalence of 2 RTL's.. ?.. Is formal verification tools like conformal, formality doesnt statisfy ur problem?. Aravind
Hi Hsim is fastspice tool. its for full chip transistor level functional verification.
Depends on how you define "run code coverage." Performs multi-language coverage-driven functional verification, analysis, and debug from system level to gate level. Automates testbench generation.
GLS is similar to RTL simulations...what is extra in it is just the gates delays...You gotta learn functional verification for both :D
I work in ASIC functional verification. I have seen VLSI Mtech Syllabus of some collages. None of them meet Todays industry requirements in functional verification. It takes minimum 6 months to learn complete functional verification. May be this is the reason , (...)
Hi All, Can someone please provide me with an ebook for functional verification basics, basically covering things like assertions , BFMs, drivers monitors If you know any website link that will also help Thanks
Dear, I have often extracted Verilog-Gate-Level-Netlist(VGLN) from hierarchical Netlist for functional verification. But I must review schematic to set/replace gates in VGLN with right strength/strong of signals. Is there any methodology to set strength/strong of signals/gates in VGLN automatically? Thanks, Best Regard
I guess you would need: Custom IC Design Kits (Virtuoso): IC610, MMSIM72, CADENCEHELP, Lic+Config_Utils functional verification Kits (NC-verilog, Simvision): IUS82, (I don't know the alias of Simvision) Digital Implementation Kits (Encounter): SOC81 You should be able to find a pdf or a text file explaining what each archive/directory contain
Hi All, Can anyone please share me the book "Step-by-Step functional verification with SystemVerilog and OVM "
ESL is a catch all for different tools and languages. you need to be more specific with your question. regards ajay Hi thank you for your reply my question is if 1.ESL to RTL(using some tool) is possible 2.formal verification between esl and rtl is also possible.. then
These days High Level Synthesis tools (Mentor's Catapult,Synfora's Pico for C/C++ to RTL) getting into industry. Will there be any effect of these tools on functional verification using VMM/OVM? (atleast in near future..) Please correct me if my question itself is wrong...
Hi, I've created my own clock gating method, and I'm trying to check the logic equivalence by using Synopsys Formality. However, verification always fails even though I've checked the functional equivalence by RTL simulation. Also, I've set the set_clock_gate_hold_mode to 'any'. My clock gating method is as follows: 1. Create an enable signal
Hi Vikram, With respect to Digital Design. Front End: RTL coding,functional Simulation/verification. Backend means Implementation which includes, Synthesis,Place and Route,Static Timing Analysis,Physical verification. Synthsis can be done by either Front end or Backend Engineer. Regards
I believe that the chip design industry should have a better understanding of what functional verification is all about. R&D executives should have more knowledge in verification than they do today. Its' not that I expect CTO's to sta
Certificate course on functional verification ........basics to ASIC verification using SystemVerilog CVC is announcing a new session of its popular 5-day certificate course on functional verification covering SystemVerilog in depth. Broadly it covers the following topics:  SystemVerilog (...)