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154 Threads found on edaboard.com: Generate Timing
Hi All, I have to generate RGB signals from an application processor, having equivalent timing parameters for NTSC and PAL (Later this signal will be converted into an analog signal). By looking at the analog video signal (NTSC or PAL) how can we calculate the digital timing parameters ? I specifically need hback-porch, hfront-porch, (...)
Its much easier just to generate a single constraints file and include it with the design. The .sdc file is just a tcl file that allows you to run tcl commands (for altera at least), like applying sdc constraints only to the fitter if you really have to (for example overconstraining the design during the fit to try and make it meet timing during ti
You can generate variable pwm using one timer and one pot also. 1.make port pin ON. start timer with ON time period 2.when it expires load OFF time period to timing registers. And make port pin off Whenever ADC value gets changed calculate new ON, OFF values for timer registers
Hi All I am trying to speed up the ams simulator by using behavior model. However, the behavior model does not generate correct results. It seems to due to the timing problem. It used to have some .libs for ams simulator, but right now I only have fixed rising, falling time and delay in the behavior model. Can anyone comments on how to solve t
I am trying to build a Standard Cell Library and it's associated .LIB file. I have made finished making all the individual cells. Next step involves making a .LIB file with timing and power information. I am trying to find simulation setups to generate data for the required matrices to be included in the .LIB file.
Hello, I need help with NCO ip tool,vhdl code generated from quartus IP tool,and im trying to add this code in my project. could you please say,what should i put on phi_inc_i? U_cord_gen : entity work.cord_gen port map ( clk => clk, reset_n => not tx_reset, clken => clken, phi_inc_i => phi_inc_i, fs
Using clock as data and generate clocks as in your example is likely to cause timing problems. It would be helpful if you specify the problem completely, e.g. with a timing diagram.
I have extracted the def file of my processor in innovus/encounter/EDI and ported it to calibrewb in order to remove some dummy lines. Since calibre cannot generate def output, I saved the final design in oasis (.oas) format. Now I would like to import the oasis into cadence platform in order to extract spef files and do timing analysis. Anybody kn
This is a very complex question. The simple answer is that is it better to rely on static timing analysis tools to determine your critical paths - they are far more accurate. In dynamic simulation, you need assurance that all the models can accurately generate X's when there is a timing failure, and that the same models are written to (...)
What's the waveform you want to generate and where is it used for? People avoid generated clocks in FPGA design and use clock enable signals wherever possible.
try to generate the bram with core generator instead....
You run one of those tools, which run spice using the netlist for the standard cells, and then they generate the .lib for you.
In general I would expect DRC and Monte Carlo methods will determine critical timing and path length issues. Critical path (shortest latency) results should come out of a manual or auto generated set of test vectors in combinational and sequential table and generate the results which could be sorted. But I offer no step by step solution on each.
Hi, I have a design which uses MIG ip.I added some user modules & i could get it to implement successfully.But in that design,i had differential system clock & reference clock.(4 diff sys clk + 1 diff ref clock.) Earlier all these diff. clock inputs were inputs to my top module,now i wanted to generate those clocks internally by using cloc
I would try it out in this way... Using a counter and the 10MHz clk, generate a signal that is HIGH for 100ms and LOW for the next 100ms, that gives us 200ms. Use this signal as clk input to the stop_flag register.
Hi Electro ns, since SSI is a synchronous type of serial transfer and you generate the master clock it can be generated in software if you meet the timing of the device connected. The general SSI description can be found here: . There are some differences from MFG to MFG and you need to h
For a start I would never have known from your code that Timer 4 was working as a 16-bit timer but that Timer4/5 was not working as a 32-bit timer. This is why you need to explain what it working and what is not. The problem is that for 32-bit timers, the interrupts are generated from the 'odd' numbered timer (last bullet point in the "Timers" FRM
You don't tell in which form you want to the "timing information". But it shouldn't be difficult to generate an array with time of all square wave edges.
In contrast to modern microcontrollers, AT89S52 has no hardware timer outputs. So the timing signals have to be generated in software, e.g. in a timer interrupt. A detailed specification can show if it's feasible with sufficient accuracy.
I used the clock divider to set the clock of the ADC (according to dataheet 4.8kHz) 4.8 kHz is the maximum sampling rate, not the clock frequency. The ADC clock frequency is generated by a crystal on the module. You'll generate a SPI interface timing according to the datasheet specification. Maximum SCLK frequency is 5 MHz, 1 or 2
if you don't care of the timing you just need a text editor. Same for the LEF. i usually used scripts to generate the LEF with the expected waveform, and place pins in one border. For the liberty I used script in PT with quicklib model
Hello All, I want to generate VGA signal with microcontroller. But I have hard time finding solution online how to generate them in software. For e.g. Usually all online VGA signal generation just explains timing requirement for HSYNC and VSYNC along with back and front porch timing with for some fixed values like (...)
ISE is a synthesis tool and ignores any simulation timing statements. To generate timing in hardware, you need an input clock and sequential statements referring to it.
I don't know if the FPGA tool vendor have some power consumption estimation. But normaly, to know the power of a design: 1- simulate a netlist with backannotated timing in your power-functional case, export a VCD or SAIF 2- with tool like primetimePX, based on the VCD/SAIF, report the power, and also generate a fsdb, you read it with zWave (or
Bharath, Here is sample VHDL code for Buzzer interface with FPGA. In the above code it will generate ON/OFF pulse every 1 sec. 50MHz produce 20ns timing. To convert 20ns to 1sec, 50000000 counter is generated. for your
Hi, I am using a SoC which goes into sleep mode for 5 minutes. Now after 5 minutes I need to wake it up using some external trigger. What are the different ways I can implement interrupt generator in hardware? I can not use timers of SoC, as SoC is in sleep and Timers are not operational in sleep mode. I thought of RTC, counters or RC networ
PERL platform is good for any EDA tool. EDA tool project cant be developed in 6-8 months. What you can do is , write a wrapper around any tool to get the automated results to help designers/verif engineers. For ex , If you consider, DC as your EDA tool. DC will generate the timing reports. Assume you have 250 clocks in the design. DC will write
Hi Experts When we generate RC factors from ostrich it gives us the clock and data RC factors separately. Since preroute clock is considered ideal, why does tool give us the preroute RC clock factor? Where does it use the clock RC (timing/optimization??)? - - - Updated - - - ..............ok got my answer
You should never get into the habit of using logic generated clocks in FPGAs. You should generate clock enables isntead.
Primetime requires .db (compile .lib file) to work. Virtuoso could not generate .lib file, you need a characterisation tool for that.
Hi All, Is there a way or skill to generate a report in altium designer with attributes netname,from(source),to(destination),length(mils),timing(picoseconds). any help will be appreciated.Refer image. SHABU
In primetime, you have some command to fix that "easily": fix_eco_drc, and could generate a script which indicate what modification was made by the command.
CCS provide the waveform of the current transform, then this is very much complicate to interprete or generate.
Well, when I faced to a scan simulation issue: 1- I run the simulation without timing annotation, which confirm that the patterns is "functional" versus the netlist, and will confirm that the model used to generate the patterns is the same as used for the simulation. In our design, I have a analog component, and normaly all outputs of this module n
Hi there I am using a SPARTAN6 speed grade 3 and there is a high speed SDR SRAM In my board. I've used PLL to generate clock and out to SRAM. I set timing constraint but the max frequency I achieved is 125 MHz. If I increase the output clock of PLL to 150 MHz I have timing constraint error: "Slack in some nets is -3.447ns." How can I (...)
Hi I am using Nanotime to generate critical path timing report to use in Tetramax and I am getting the following error. ERROR:NetComp:0x30204008:cannot find subcircuit definition or function model AND2_X2 for instance XNAND2_1. Error: Compiling netlist failed. (NLNK-002) I would be glad if someone can help me out with this. Thanks
I'm not familar with STM8 either but I have coded several master and slave 1-Wire applications. You have to write your own timing routines to generate the reset pulse and clock pulses. Their timing is fairly critical. Remember there is only one master device on a 1-Wire bus so the slaves don't need to generate a clock as
Can anyone give me any idea that how can I generate two pulses with 90° phase shift with pic micro-controller? The frequency is 50Hz, and I've to show 4 different data in LCD too with this operation. As I did a rough where I can't get the exact timing. It creates a delay for LCD and ADCRead. how can I generate these continuous pulses without (...)
Hi All, After P&R phase, P&R engineers generate many SDF files - each one for a different PVT corner. Which one should be used for the future Logic Optimization? Thank you!
Dear all... I am new in RTL designing ..I am facing one problem in my design is having an input clock of 100MHz and generate some of the frequencies in my design like 160,50Mhz ans some wat my problem is..i have one signal(Register) which is clocked by 160 MHz and i am passing the signal from the previous to a register with c
The generation of enable to the clock gating. The register which generates the clock enable is also expanded in clock tree synthesis then timing closure of clock gating enable on root clock would be very tough. So bottom line is we should not expand the clock tree on registers which generate clock enable
I would rather try to generate the WE waveform by a PLL directly than or-ing phase shifted clocks. Phase shift of WE against address/data may be still necessary to compensate for timing variations. Minimum pulse width has specification to be considered, 2 ns should work with Cyclone II. At worst case, an in-system calibration of WE phase with te
Is this clock generated out from the CLKGEN ckt?. From your description, there is control logic to generate the clock to your ckt. Follow these steps to find the root cause ?. I assume tool used for signoff is synopsys. Ask your timing engineer to trace the fanin of the clock. (report_transisitve_fanin -to
TETRAMAX generate test pattern and use ncverilog to sim,take no timing info, but it report error, what is the question , thanks,
To interface the peripherals to the 8255 ports you will have to use one port(e.g. 8 bit) to generate the chip select for the different peripherals and the control signals needed. Each peripheral requires a specific read/write cycle you need to generate in software and meet their timing diagram. Could be a lot of effort and slow. If you can (...)
These things are nearly always a problem with the UART settings or timing. (Sorry if you already know all of this, but I don't know how much experience you have)... What crystal are you using for the ATMega, and do your settings generate an accurate baud-rate clock for the UART? Have you tried (with the same settings) connecting the ATMeg
You need to generate the .lib file to have the timing, power, area, functionality informations and a lef file for the physical description, and a CDs for the Celtic view. You do not need to change the standard lib cell, just add on more lb file read by the backend tool.
Hello all, I used Design Compiler to generate .sdf file for my design; I used wire-load standard models. As I see through my generated sdf file, there is not any timing(delay) report on my interconnects (all are set to 0)!! LIKE: (INTERCONNECT U26245/Y U26248/A (0.000:0.000:0.000)) (INTERCONNECT U4068/Y U26247/A0 (...)
actually the problem arises when we use timer of microcontroller to have a delay of 12.5 ?s (half of 25 ?s {time period equivalent to 40 kHz}) , it becomes comparable to time spent by the ?C in executing instructions ( 0.5 ?s for 1 Machine Cycled instructions) and hence the instructions to produce the delay contribute significantly to the delay..
You can use different outputs from the CD4060 in order to generate separate timings for the LEDs and the buzzer…