43 Threads found on edaboard.com: Gtech Synopsys
hello members
after a long and patient search i have got synopys dc wint nt 2000.11
from a board member . yu guys must be knowing that a good board member uploaded it in 39 zip 4mb zip files in his ftp server which is now closed.
i have installed it successfully . however when i try to b
build the gtech files from hdl sources then i get the
ASIC Design Methodologies and Tools (Digital) :: 13.06.2002 12:10 :: dk :: Replies: 1 :: Views: 1545
After so long i have found a solution at least for the structural description of the circuit. If anyone can provide something for the behavioral plz tell me.
Here is the listing
library IEEE;
use IEEE.std_logic_1164.all;
library gtech;
use gtech.gtech_components.all;
entity adder is
port (a,b,cin :in std_logic; (...)
ASIC Design Methodologies and Tools (Digital) :: 02.08.2004 19:28 :: etherios :: Replies: 9 :: Views: 1473
Hi all,
I have several question regarding synopsys DC :
(a) What are design references? It was mentioned in the documentation that Link Libraries are needed for design references..
(b) What are Link Libraries. I know target libraries is the one used to bulid a circuit from a translated RTL design. But what are link libraries
ASIC Design Methodologies and Tools (Digital) :: 06.12.2004 04:11 :: haosg :: Replies: 16 :: Views: 6748
Hi all,
When synthesizing RTL to netllists, synopsys Design Compiler will read gtech lib to generate a technology-independent netlist before reading lib from foundary such as TSMC. My question is what's the format of the file mapped from gtech lib? Could the file mapped from gtech lib be written out? How to do that? (...)
ASIC Design Methodologies and Tools (Digital) :: 20.04.2006 13:22 :: eda_wiz :: Replies: 4 :: Views: 1087
synopsys gtech is in synopsys .db format.
------------------------------------------------------------------
You can find it unfer the tool install directory,
$install_dir > find . -name "gtech.db"
ASIC Design Methodologies and Tools (Digital) :: 24.04.2006 17:03 :: joe2moon :: Replies: 3 :: Views: 2507
gtech is a virtual library. this is what your circuit first gets translated into, before it gets synthesised to technology-defined gates. It does not mean that your real target library will have these gates. It is useful in the sense you can see broadly what kind of circuit, your VHDL ends up with.
Designware library is a real implentation for
ASIC Design Methodologies and Tools (Digital) :: 22.08.2006 11:32 :: bulx :: Replies: 3 :: Views: 1981
hi all,
I have doubts about ".synopsys_dc.setup" file. hope someone can help...!
1) when search path is given a path fpr example "
search_path = {} + search_path, what the + search_path mean ?
I mean why I need to include search_path = {"original path"} + search_path
2) About technology files :- I have ".db and .lib" bu
ASIC Design Methodologies and Tools (Digital) :: 15.12.2006 11:10 :: Mirzaaur :: Replies: 1 :: Views: 644
Hello,
Pay attention to the paths you are writing in the variables:
link_library = { vlsicad/micsoft/IBM_CMOS8/A
should be:
link_library = { vlsicad/micsoft/IBM_CMOS8/A
Maybe that "/" caused the problem.....
I hope this helps!
hi all I am stuck with a strange problem. here is my .synopsys_dcset up file :
ASIC Design Methodologies and Tools (Digital) :: 20.12.2006 15:26 :: Atre :: Replies: 5 :: Views: 698
Hi all
i need to convert the db file gtech.db to gtech.v format
is it possible?
pls let me know
thanks in advance
srinivas
ASIC Design Methodologies and Tools (Digital) :: 27.01.2007 08:24 :: rsrinivas :: Replies: 6 :: Views: 1538
Hi bcdeepak,
What do you mean by "using its library (default)".
Is it a generic library or gtech?
I hope it is not a generic library. Cause you can't use this lib to synthesize and layout your design.
You need a real tech lib, ex. tsmc or ami or others and you must use the same tech lib for synthesis and layout.
Hope it helps.
ASIC Design Methodologies and Tools (Digital) :: 21.05.2008 10:23 :: no_mad :: Replies: 1 :: Views: 773
Hi Bhargav,
In synopsys you have .synopsys_dc_setup file. In this file you have to specify your link and target library in order to map your logic to actual library. If you don't specify any library as target and link lib. it will map the logic is its standard gtech library(generic tech library).
Hope this will solve your problem.......
ASIC Design Methodologies and Tools (Digital) :: 09.10.2008 04:52 :: viju :: Replies: 1 :: Views: 1247
i tried these in command window and got following errors:
set target_library "C:\synopsys\libraries\syn\gtech.db"
Error: Undefined operator on or near line 1 at or near 'set'. (EQN-2)
design_analyzer> set target_library "C:/synopsys/libraries/syn/gtech.db"
Error: Undefined operator on or near line 2 at or near 'set'. (...)
ASIC Design Methodologies and Tools (Digital) :: 19.12.2011 15:00 :: aria62 :: Replies: 8 :: Views: 693
I try it in the pass time.
It's the must-be way to do in FPGA synthesis by DC.
Therefore I found most of the information reguard in insert_pad all
from Xilinx ftp/web. U can find it in their web.
BTW, I found many limit in doing auto insert pad .
U should follow this guid-line.
1. Name ur pad module interface signals in this rule
si
ASIC Design Methodologies and Tools (Digital) :: 15.05.2002 16:18 :: Nobody :: Replies: 7 :: Views: 2746
How to convert synopsys gtech.db to Debussy's symbol library?
ASIC Design Methodologies and Tools (Digital) :: 16.05.2002 13:35 :: DeepIC :: Replies: 0 :: Views: 1566
Well, we are trying to run Design Analyzer of Synopsis. There is a relativly good tutorial on Verilog design.
However, the code we have is written in VHDL. Thus, we either have to "force" Design Analyzer deal with it or make a toplevel verilog code and somehow instatiate VHDL entities in it. :roll:
The problem with VHDL is th
Microcontrollers :: 13.02.2003 03:46 :: always@smart :: Replies: 6 :: Views: 1047
It seems none of the business of library_compiler, because it even cannot read the gtech library.
The following is the messege:
Loading db file '/local/eda/synopsys/libraries/syn/dw_foundation.sldb'
Error: Can't read unprotected library 'dw_foundation.sldb'. (DDB-44)
Loading db file (...)
ASIC Design Methodologies and Tools (Digital) :: 06.08.2004 17:35 :: wizard :: Replies: 9 :: Views: 3085
how can i begin with design compile if i have no foundry library?
Without a foundry libary you cannot compile the code to get a netlist...
If you want looking for a genric netlist.. you can use DC to genrate a gtech Cell based netlist which has no timing information..
eg..
analyze file.v
elaborate Module_name
write
ASIC Design Methodologies and Tools (Digital) :: 13.11.2004 10:49 :: eda_wiz :: Replies: 47 :: Views: 8270
when i finish elaborate step using dc, i get gtech netlist. i set dont_touch in this module, and then synthesize this module or synthesize the upper module, i want to know that whether i can get the gatelist that have mapped to target library?
If the module to which you applied constraint dont_touch is a library specifi
ASIC Design Methodologies and Tools (Digital) :: 17.11.2004 05:21 :: eda_wiz :: Replies: 13 :: Views: 8048
coreConsultant can also generate what is called a gtech representation of the core. This can be used for simulation with any simulation tool. You will have to have the synopsys gtech libraries to do so. gtech is in a netlist format fyi.
To generate readable rtl, you need the core's source license.
ASIC Design Methodologies and Tools (Digital) :: 05.10.2005 02:19 :: kittykat77 :: Replies: 5 :: Views: 827
Hi All,
My customer use synopsys gtech gate level netlist verilog format
as hand-off format. (set target_library = gtech.db in DC)
But we use Cadence RTL compiler as synthesis tool.
How to compile synopsys gtech gate netlist in RTL compiler to otimize
and map to technology library cells?
ASIC Design Methodologies and Tools (Digital) :: 01.03.2006 15:12 :: jiang :: Replies: 4 :: Views: 1626
I am using Design Compiler, width tsmc 0.13 Asic library.
The tsmc library provides full adder cell but Design Compiler is not using it.
I instantiated a full adder using the component instantiation as descripted in Designware User Guide.
library IEEE, gtech;
use IEEE.std_logic_1164.all;
use gtech.gtech_components.all;
entity (...)
ASIC Design Methodologies and Tools (Digital) :: 11.06.2006 17:10 :: nkef :: Replies: 3 :: Views: 629
This article is from solvnet copying it from you, i find interesting that simple questions can be searched easily in solvnet with one keyword :idea:
next time you have any questions search it once you will surely find answers :D
The target_library variable specifies the library that Design Compiler
uses to select cells for optimization and
ASIC Design Methodologies and Tools (Digital) :: 23.08.2006 10:14 :: dr.farnsworth :: Replies: 8 :: Views: 5860
you must use dont_touch on library cell, not math logic.
synopsys will translate math logic to gtech library, then map to target library. If you want delay chain.
Just use target cell directly. then set_dont_touch on them.
ASIC Design Methodologies and Tools (Digital) :: 29.08.2006 15:55 :: wkong_zhu :: Replies: 7 :: Views: 969
Hi,
synopsys has a tool design compiler. Following is a method to create gate level equivalent for There gtech library.
--------------------------------------------------------------------------------------------
To create a netlist with gates that are technology independent, you should use
a generic library, such as the generic technology
PLD, SPLD, GAL, CPLD, FPGA Design :: 29.01.2007 05:50 :: ram :: Replies: 6 :: Views: 1793
Hello Friends,
Even if we read the svf file there are chances of getting inconclusive results. I faced the same situation and got inconclusive results at some multipliers of the design.
Here my suggestion is, if u r having the DW components like Multipliers, check what king of multiplier(csa, csd, wallace etc.) ur synthesis tool has inferred
ASIC Design Methodologies and Tools (Digital) :: 02.01.2009 08:45 :: sunilbudumuru :: Replies: 5 :: Views: 1951
This warning is generated when the verilog write detect that there are references of SELECT_OP or gtech components in this module. When finish compile, this warning maybe need not be cared.
ASIC Design Methodologies and Tools (Digital) :: 16.01.2009 02:26 :: horzonbluz :: Replies: 14 :: Views: 3733
I don't know if there are any tools you can use to transfer the synthesized netlist directly to a generic verilog independent to the technology.
but i guess there are two ways to make it true:
1. other than the netlist, define a mapping file to map the gates instantiated in the netlist into gates of the other technology lib ---hell lot of work
ASIC Design Methodologies and Tools (Digital) :: 24.02.2009 09:08 :: fpga_asic_designer :: Replies: 15 :: Views: 7031
Yes, the flow I'm following is as follows:
After elaboration (gtech) I insert clock gating and compile once. No saif annotation here.
Then after i get the first clock gated netlist, I simulate it and get a saif file out of the simulator. Then I go back to the synthesis flow, enable power driven clock gating and read in the saif annotation. Th
ASIC Design Methodologies and Tools (Digital) :: 07.05.2009 14:55 :: Zorbas-E- :: Replies: 9 :: Views: 1654
I want to run fm_shell using multi cpus in one servel (not multi sevel) but it seems not work.
Hostname: RHEL37 (amd64)
Current time: Thu Sep 17 11:32:11 2009
Loading db file '/tool/synopsys/fm_2007.06_SP3/libraries/syn/gtech.db'
fm_shell (setup)> add_distributed_processors rhel37*4
Status: Forking successful
ASIC Design Methodologies and Tools (Digital) :: 17.09.2009 05:44 :: aaronhe :: Replies: 0 :: Views: 507
I think doing either set_case_analysis or set_dont_touch_network have some possible issues
1. If with set_case_analysis, there may be some unwanted optimization in the fanout of the "master control signal". If it's really static, why not change it to a constant
2. If with set_dont_touch_network, the logic in the fanout may not get mapped to
ASIC Design Methodologies and Tools (Digital) :: 08.02.2010 16:31 :: kujigaya :: Replies: 6 :: Views: 1273
Hi auroral,
Pls make that sure you have added all reference libraries using in your design. Could you provide your running logs for analysing ?
Regards,
Eric.Pan
When I open and get into the milkyway dir and try to import my verilog design, this is what happens.
icc_shell> open_mw_lib example/
{example}
icc_s
ASIC Design Methodologies and Tools (Digital) :: 24.05.2010 21:59 :: auroral :: Replies: 6 :: Views: 3437
Hi,
I am trying to estimate the gate count of my design. I do not have a target technology library at hand.
Hence I decided to synthesize the design using synopsys Design Compiler and get the netlist in gtech.
I assume that gtech_NAND2 is equal to 1 cell. Then i plan to estimate the cell count of the design (in terms of NAND2 cells) (...)
ASIC Design Methodologies and Tools (Digital) :: 17.06.2010 00:02 :: onkars :: Replies: 3 :: Views: 876
Hi everyone,
I met an error when I run ICC with the instruction "import_design", shown as following:
icc_shell> import_designs -format verilog -top ChipTop -cel ChipTop_floorplan {./results/compile.v}
Loading db file '/iggroup/home/phuang/synopsys_Curriculu/low_power_methodology/lpmm_labs/lpmm_lab3/models/saed90nm_typ_ht_pg.db'
Warni
ASIC Design Methodologies and Tools (Digital) :: 16.12.2010 03:03 :: phuang :: Replies: 3 :: Views: 1211
if DC cant find any scan cell in .lib file, it will keep it with the gtech models in the verilog.
ASIC Design Methodologies and Tools (Digital) :: 13.07.2011 16:59 :: shakemyhead :: Replies: 2 :: Views: 235
Hi, guys, I need ur help,thx!
I have problems while elaborating the FFT_256 project from opencores.org(Pipelined FFT/IFFT 256 points processor :: Overview :: OpenCores ) in the synopsys design compiler. I dont know why this happen because I synthesized the same design in Virtex4 FPGA using synpl
ASIC Design Methodologies and Tools (Digital) :: 02.09.2011 10:27 :: rockybc :: Replies: 0 :: Views: 444
Hi,guys,would you help me sth. about report_area command ,thx.
I synthesized the can bus RTL in Design Compiler,and set the target_library "gtech.db".I didn't involve any constraint while compiling and after finishing the compile, the information read:
****************************************
Report : area
Design : can_top
Version: C-2009.0
ASIC Design Methodologies and Tools (Digital) :: 07.09.2011 10:23 :: rockybc :: Replies: 5 :: Views: 777
Hey
Thanks for your reply
I realized that registers are not design ware. What do you mean by should specify standard.sldb as target library??? isnt target library suppose to be technology lib like faraday fsc0h.??
also i realized that synthesis of design is inferring everything(and, or, nand) from gtech lib but not standard.sldb?
if u
ASIC Design Methodologies and Tools (Digital) :: 23.09.2011 11:02 :: jkbagada :: Replies: 2 :: Views: 244
what is the importance of gtech libraries in synthesis?? i mean in the process of synthesis, why we have to first transform to gtech cells, and what happened, if we directly mapped with technology dependent cell in target libraries...
ASIC Design Methodologies and Tools (Digital) :: 02.10.2011 18:15 :: sharif.shiek :: Replies: 4 :: Views: 268
Frontend
1.technology libraries
a.Target library(.db)
b.linklibrary(.db format)
2.symbol library
3.technology independent library
a.gtech library(genric technology)
b.synthetic library
c.Designware library
ASIC Design Methodologies and Tools (Digital) :: 01.12.2011 20:08 :: ravipandu46338@gmail.com :: Replies: 7 :: Views: 1059
For DesignCompiler
set target_library ".../synopsys/.../libraries/syn/gtech.db"
set link_library "* $target_library"
analyze -format verilog ${RTL_SOURCE_FILES}
elaborate ${TOP_NAME}
ungroup -all
compile -no_map -exact_map -ungroup_all
write -f verilog -hier -out ${TOP_NAME}.assign.v
It will produce the boolean equation (by using a
ASIC Design Methodologies and Tools (Digital) :: 10.04.2012 15:24 :: oratie :: Replies: 11 :: Views: 462
I have changed systemverilog file as you written. But the warrning still exit. info as below.
dc_shell> read_file -format sverilog ./clockgating/counter11.sv
Loading db file '/home/esdcad/designkits/st/st12/v92/CORE9GPLL_SNPS_AVT_4.1/SNPS/bc_1.32V_0C_wc_1.08V_105C/PHS/CORE9GPLL_Worst.db'
Loading db file '/home/esdcad/designkits/st/st12/v92/CO
ASIC Design Methodologies and Tools (Digital) :: 14.04.2012 01:05 :: windy7286 :: Replies: 6 :: Views: 622
can you try this...
in DC
dc_shell-t> list_libs
and in Primetime
pt_shell> list_libraries
it will tell you the libraries and in both the cases. See if there paths are same.
DC tells me:
Logical Libraries:
-------------------------------------------------------------------------
Library F
ASIC Design Methodologies and Tools (Digital) :: 30.05.2012 14:30 :: hbeck :: Replies: 6 :: Views: 440
I'm beginner of using Design compiler (synopsys)
but I want to know the library file ,such as lsi_10k .db , class.db, gtech.db.
which company serves this library or which nanometer they are served.
though I looked for this data in solvnet, and also throw a question via e-mails,
but They didn't give a clear answer.
How can I get this inform
Electronic Elementary Questions :: 20.05.2013 09:56 :: kjkj35 :: Replies: 0 :: Views: 64
Previous
1
Next
Last searching phrases:
gsm sim programming | dspic33fj256gp710 | hfss pml fss | interfacing and 128x64 | intrinsic region | mems tools | memristor | notebook acer | uln led display | training egypt
gsm sim programming | dspic33fj256gp710 | hfss pml fss | interfacing and 128x64 | intrinsic region | mems tools | memristor | notebook acer | uln led display | training egypt