66 Threads found on edaboard.com: Hex Verilog
We have to use $readmemb() to read files in binary form. $readmemh() to read hex files. I used it many-a-time, let you check out once. I hope no need of PLI or whatever mentioned....,...,
I can use this PLI for using hex data or bin data from ordinary file,
but whenever reading obj code fil
ASIC Design Methodologies and Tools (Digital) :: 29.07.2004 22:44 :: roger :: Replies: 13 :: Views: 3319
1. Any assembler or hex code generator for AMD?
2. Any sample design of for example 8-bit cpus, 16-bits cpus, etc with AMD?
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.10.2004 08:58 :: jimjim2k :: Replies: 7 :: Views: 2620
What u are looking for is hardware -software co -simulation ... how is it done in simple terms ... compile ur program .. get the binaries .. convert it into hex format ... load it into a memory model in verilog or vhdl then run it (normal h/w verification way ) . But what u want to do is port your OS to a processor .. doing this on simulation will
ASIC Design Methodologies and Tools (Digital) :: 21.03.2005 01:51 :: semiconductorman :: Replies: 2 :: Views: 825
Interview question I guess :) .........
It is rather simple here the '-' sign does not denote any value .Remember that in verilog the valid values are only 1,0,X,Z . So when you assign "-" . this is treated as a string and then the ascii value of this "-" is taken which is 2D is hex. The '0' bit value of "-" is ascii is then assigned to the varia
Electronic Elementary Questions :: 26.05.2005 04:15 :: semiconductorman :: Replies: 2 :: Views: 1174
$fopen will only open the file. To do any file operation in verilog this has to be done first. for reading from file try $memreadb (for binary files) or $memreadh (for hex files).
U also have $fscanf, $fgetc, $fread to read files. Not sure
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.03.2006 05:21 :: vivek :: Replies: 6 :: Views: 30189
yah.. what dcreddy said..
never leave unknowns in any default/reset condition as they will affect the simulation/synthesis.. If you don't care about them then don't put them in then case statement..
the main problem is your using "?".. personally i never would use a x or ? in my code.. if you don't care about their state changing, then either
ASIC Design Methodologies and Tools (Digital) :: 30.08.2006 23:57 :: jelydonut :: Replies: 21 :: Views: 2367
When writing state machine, we prefer to use hexadecimal than binary !!!
What is the advantage of using hexadecimal instead of binary?!
Is it increase performance??!!
Point Will be Given if can supply me with professional answer!!!
PLD, SPLD, GAL, CPLD, FPGA Design :: 19.10.2006 17:16 :: choonlle :: Replies: 5 :: Views: 2229
Ineed aprogram that covert hex file generated from kiel to a form that include full content of program memory ,so that it's easy to implement in my 8051 ROM module.
Thanks in advance
PLD, SPLD, GAL, CPLD, FPGA Design :: 07.02.2007 09:57 :: Elnegm :: Replies: 2 :: Views: 956
I knew before that hex file contain contents in program memory but lately i need to unsert hex file in verilog imlemented ROM but i discovered that hex file is not exactly the ROM it contain additional data Is anybody has an idea how can i extract program memory byte from hex file
Thanks in advance
Embedded Systems and Real-Time OS :: 08.02.2007 15:55 :: Elnegm :: Replies: 3 :: Views: 704
if any of you nice guys can help me out .
i need some model code written in verilog
1) hex keypad
2) 14 digit lcd
plspls pls pls help me out guys
my id is
PLD, SPLD, GAL, CPLD, FPGA Design :: 29.04.2007 08:36 :: Shahgul :: Replies: 3 :: Views: 2348
For simulation, by using verilog how can I code the programme to obtain pixel data from file hex form. Plesea show me the books, syntax, etc...
Thank you very much!
PLD, SPLD, GAL, CPLD, FPGA Design :: 24.08.2007 05:33 :: win3y :: Replies: 5 :: Views: 848
Recently i was reading verilog LRM for this, and i came to know about
Usign it I can read one line at a time, that too in my convinient format(i.e. hex)....
Anyway, thanks a lot for your replies...
ASIC Design Methodologies and Tools (Digital) :: 17.09.2007 02:00 :: bharat_in :: Replies: 3 :: Views: 2770
may someone know how to translate hex into binary by vhdl! if you know, pls tell me! thanks!
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.11.2007 02:37 :: shenql :: Replies: 13 :: Views: 13417
Previously I had trouble with the variations of "readmem". A testbench from last year contained the following comment.
// Old commands for using ASCII hex input files
// Pull the VLIW into the temporary memory array
// $readmemh("sample.hex", tmpMem, 0);
That testbench needed binary input data. I solved the problems and got it to work as
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.01.2008 08:04 :: banjo :: Replies: 3 :: Views: 5935
I think you mean a BCD-to-7-segment decoder.
Here is the 'case' statement from a digital clock project that I wrote some time ago. Maybe it will help you.
'nibble' is the 4-bit input code (similar to your BCD value), and 'segment' is an 8-bit register connected to the 7-segment display (and its unused decimal point). It displays hex digits 0
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.05.2008 11:00 :: echo47 :: Replies: 1 :: Views: 6288
As I got a notification to send the final solution from admins
here you are
1- use readmemb, readmemh for read binary and hex data. This option is supported in most of tools
2- use PLI (standard file IO functions) like is more powerful and gives more flexibility but not supported in trial version, student version tools
ASIC Design Methodologies and Tools (Digital) :: 08.04.2009 13:02 :: haytham :: Replies: 3 :: Views: 1143
x <= '0' Bit
x <= O"57" Octal
x <= X"2F" hexadecimal
x <= "00000" Binary
x <= B"00000" Binary
x <= 1200 Decimal
Note that, for instance with hexadecimal, the destination must be a vector which fits exactly (4/8/12/16/20/.... bit vectors).
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.06.2009 10:38 :: Marcel Majoor :: Replies: 1 :: Views: 830
Hi, I'm trying to write a simple module in verilog that I can use on an APEX APEX20K200EFC484 starter (Excalibur) board to write characters to the display.
I have seen some examples here for other displays and FPGAs but finding it very difficult to get the correct information on how the display decoder works.
This looks promising: www
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.12.2009 03:20 :: alias__neo :: Replies: 0 :: Views: 1223
I've bunch of 14-bit data points which I would like to convert in hex to use with $readmemh in verilog.
Any clue how to do that? It seems there is no direct function to do that in MATLAB and Excel can not handle more than 10-bit data!!
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.02.2010 02:11 :: Jack// ani :: Replies: 0 :: Views: 572
I need help displaying the duty cycle of an incoming 1 MHz signal. The output number will be displayed as a hex value/ascii number. Please help!!
For back information, I'm using a Spartan 601 starter kit board. With the use of the provided base reference design interface there is a second tab that has a user defined section. The user is allo
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.03.2010 14:26 :: ntropy :: Replies: 3 :: Views: 791
To read array from test bench use:
In above case you read hex data from data.txt file to read memory data. You can use for loop to traverse through all the location.
To write data to text file use: $dumpfile("data.txt");
Hope this helps
Network :: 21.04.2010 02:35 :: Jack// ani :: Replies: 1 :: Views: 2267
Im trying to read an image on verilog. Im supposed to carry out a DWT on an image matrix. Since i couldnt figure out how to convert an image into matrix (hex) on verilog i used MATLAB imread for it. Now that i have the matrix for it how can i save it on verilog? Should i access it on verilog using it (...)
Digital Signal Processing :: 05.05.2010 08:59 :: UFK :: Replies: 3 :: Views: 1624
Yes it is possible and it's not hard to do.
You can get the simulation time using this:
And then save it in a file using this:
integer file_ptr; // file pointer
file_ptr <= $fopen("C:\\...whatever...\\your_file.txt", "wb");
PLD, SPLD, GAL, CPLD, FPGA Design :: 24.05.2010 13:30 :: fcfusion :: Replies: 1 :: Views: 549
can someone please help me write a verilog code for converting a given value in decimal to hexadecimal. My code computes a value 'T' after some math calc. This value T must further be used in the code in hex format. How can i do that?
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.05.2010 13:47 :: UFK :: Replies: 2 :: Views: 3273
I want to write a single byte(8 or 16 bits) into an hex file, but the system always replenishes it to a 32bits data with extra zeros.
Part of the verilog file and my analysis are expressed below.
// verilog file
// Open File
fp = $fopen("AF.hex", "wb");//must be binary read mode (...)
ASIC Design Methodologies and Tools (Digital) :: 30.06.2010 02:47 :: xang :: Replies: 0 :: Views: 2793
In my code im using $readmemh to read hex values from a text file in which alot of the values are negative. verilog is treating them as positive and returning erroneous results. Can someone please help me deal with this problem? I really need to figure out a way to recognize these negative hex values.
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.07.2010 14:14 :: UFK :: Replies: 2 :: Views: 1088
Can anyone please help me read decimal values from a text file using readmem.
I tried using $readmemh for hex values but it cannot read negative values. Can someone please help me read values (both positive and negative) in either hex or decimal format from text file?
Thanks in advance
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.07.2010 14:16 :: UFK :: Replies: 1 :: Views: 2715
$readmemh() is very usful for such tasks.
Need to define an array, the file should hold hex values (in text, not a binary file), readmemh loads the values into the array.
google readmemh and you'll find a few examples.
PC Programming and Interfacing :: 08.11.2010 07:05 :: yoramgr :: Replies: 1 :: Views: 784
I don't know if 320 is a decimal or hex, but in either way, you don't need a divider block if dividing 8 bit data by 320 is what you are looking for, because the quotient is always 0, isn't it ?
Or are you expecting 8 bit output to be lesser than 1 ?
ASIC Design Methodologies and Tools (Digital) :: 22.11.2010 02:16 :: lostinxlation :: Replies: 3 :: Views: 722
Take a look on
VHDL, verilog, design, verification, scripts, ...
"CPU 8051 assembly code in verilog like readmemh style..."
Microcontrollers :: 27.01.2011 12:47 :: pini_1 :: Replies: 18 :: Views: 1855
HI How to model a memory as 2d Memory array in verilog ?...We have to load an hex file as the programFile for a Microcontroller in the Program ROM......
PLD, SPLD, GAL, CPLD, FPGA Design :: 02.02.2011 23:47 :: blooz :: Replies: 2 :: Views: 1332
What is the best way to read a textfile that contains decimal number (eg. 2.987) into verilog?
At the moment, I convert the values to hex using matlab (using num2hex). But when I use readmemh, it assumes that the 32bit variable is a 'regular' number and not a floating number?
Any suggestion will be greatly appreciated.
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.07.2011 18:22 :: chikaofili :: Replies: 0 :: Views: 1048
Hey I'm working on a project to get PS2 Input to the LCD, right now when I hit a key its flooding the entire LCD with that character, and I can't seem to get it to "increment",
This is the code I am using
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.03.2012 15:22 :: Rello :: Replies: 0 :: Views: 428
i have a 32bit IP address in hex..say 703020F8..i have to extract first 4bits(in binary) ,do some operation with it, then extract next 4bits and so on..how do i do it? i m a beginner so this question might sound silly.. plz help!
PLD, SPLD, GAL, CPLD, FPGA Design :: 29.03.2012 22:11 :: cutesue :: Replies: 0 :: Views: 184
Write the data into a file,such as .hex, .mic.
altsyncram_component.init_file = "fir_zero.rif"
altsyncram_component.init_file = "fir_zero.hex"
PLD, SPLD, GAL, CPLD, FPGA Design :: 12.04.2012 23:50 :: guguwuwu :: Replies: 3 :: Views: 996
A flexible method, that's also used by Altera IP is to write the data in hex format and specify it as init file for an altsyncram block. Alternatively, $readmemb and $readmemh is supported for synthesis of verilog code with inferred RAM/ROM blocks.
PLD, SPLD, GAL, CPLD, FPGA Design :: 17.04.2012 05:19 :: FvM :: Replies: 7 :: Views: 1098
I am trying to load an srec file into to a byte-addressable memory in verilog
The memory has to be one megabyte and has to have a 32-bit address input
- I am running into the following issues
-according to the srec format I have to load data into specific addresses. how to map hex addresses to a verilog memory like this one
reg [ (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 15.05.2012 23:40 :: Hassan Munir :: Replies: 1 :: Views: 474
This code was implemented on a CPLD but it is not working. Please help!
// This code should show the position of the push-button pressed by glowing appropriate leds.
output reg row,led;
PLD, SPLD, GAL, CPLD, FPGA Design :: 20.06.2012 04:48 :: pranavm1502 :: Replies: 2 :: Views: 1049
Use readmemh/readmemb system functions to read from the .raw file. To confirm what is read is correct or simply see the hex contents of the raw file, use a hex editor where you can simply open the raw file and see the hex numbers.
ASIC Design Methodologies and Tools (Digital) :: 09.10.2012 03:51 :: vijay82 :: Replies: 8 :: Views: 1124
so what is wrong with that..
What is the size of your file. What is the size of data.
In the following case I assume that size of file is 256 and the size of each data is 8bits
follow this code
module test(clk , dataout);
output reg dataout;
reg memory //memory
integer i =0;
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.10.2012 02:59 :: syedshan :: Replies: 8 :: Views: 792
As I don't have a model for ROM so I am creating it by declaring an array of specific depth. Now my problem is to store the content of hex file (generated by processor compatible compiler) to the array in such a way that the fixed size value written on each line in the hex file shall be stored on each address of array. So that I can use it as ROM.
ASIC Design Methodologies and Tools (Digital) :: 12.10.2012 05:30 :: er.akhilkumar :: Replies: 0 :: Views: 259
So my professor gave me this problem and no background what so ever on this subject. He just talked about it for 5 minutes in class and gave us this huge problem to solve. The one thing he said to do is a state machine. So far this is what i have come up with. So basically I have to use a state machine to turn this C code into verilog. I have to fi
PC Programming and Interfacing :: 10.12.2012 15:16 :: Franci25 :: Replies: 0 :: Views: 308
what should provide the 72 bits? a PC another microprocessor, through a memory?
my input file is a hex file generated by matlab, now I need to input this file in verilog testbench
ASIC Design Methodologies and Tools (Digital) :: 25.04.2013 00:41 :: jiyaa :: Replies: 5 :: Views: 566
I have one problem.
I am trying to simulate and synthetise the PIC16F84 into Spartan2 FPGA. The implementation of the PIC (I got it from Opencores) use BlockRAM as a program memory.
I would like to know, how I can convert the PIC program (written in MPLAB) from hex format into verilog source which I can use for BlockRAM initialisatio
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.10.2003 16:27 :: CADDevil :: Replies: 2 :: Views: 1819
The ModelSim tool does not support the memory initialization file (.mif) format and requires you to generate a .hex file as specified in 1430.html. Once you have the initial memory contents specified in the .hex format, please note the following:
If you are simulating in a VHDL environment, the ModelSim tool will automatically referenc
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.05.2004 07:23 :: zhuoyue :: Replies: 6 :: Views: 8230
When use @ltera LPM_ROM and @ltera ROM INITIAL FILE to generate LPM_ROM verilog Ccde(With inital value file .hex) then call synplify to produce .edf file to let altera compile to produce .sof file
Error: Can't compile EDIF Input File due to syntax error parse error, expecting `'(''
trace the error find edf syntax as follow c
PLD, SPLD, GAL, CPLD, FPGA Design :: 24.01.2005 07:58 :: mediatek :: Replies: 0 :: Views: 654
armulator with vcs for h/w s/w co - verificaioton ... hmm ..what I genrally do is use armcc and armasm compilers to generate the object files ... link it ... forms a elf file . Use fromelf utlilty to transfer this to intel hex format ... write more scripts to translate this to any format that you need .. preload these memory images into the memory
ASIC Design Methodologies and Tools (Digital) :: 27.05.2005 04:01 :: semiconductorman :: Replies: 2 :: Views: 666
You need first to design a 7-bit binary to 7-segment decoder.
Say u want to output 39 (decimal), u should write a code to encode the 3 & to encode the 9 into the required format to derive the 7-segment dispay. In the sent code there is an example of hex to segment coding, replace it by ur encoding
Then design a controller if
PLD, SPLD, GAL, CPLD, FPGA Design :: 30.08.2005 07:42 :: amraldo :: Replies: 6 :: Views: 24040
I'm currently using coolrunner ii Xc2c256cxl as my system board and DI04 as my I/O board. Using verilog, i am having problem turning on the 7-sement display. any link or verilog code that help me understand how to implement this is well appreciated. attached is my verilog code. the problem is the 4 common anode lines, how to turn it on (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 12.03.2007 22:00 :: bbgil :: Replies: 0 :: Views: 439
hey um zahra final yr student of NED uet ay khi pakistan
is thr nebody who use modelsim as simulation of verilog codes?
and can any one guide me how can i call a data or more precisely image data in modelsim i have converted ma image in hex form via a hexeditor but problem is that i cant initialize ma ram with my data
i was familiar with (...)
ASIC Design Methodologies and Tools (Digital) :: 17.05.2007 12:42 :: zahra.nedian :: Replies: 0 :: Views: 579