1000 Threads found on edaboard.com: Hex Verilog
if any of you nice guys can help me out .
i need some model code written in verilog
1) hex keypad
2) 14 digit lcd
plspls pls pls help me out guys
my id is
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-29-2007 08:36 :: Shahgul :: Replies: 3 :: Views: 2635
I want to write a single byte(8 or 16 bits) into an hex file, but the system always replenishes it to a 32bits data with extra zeros.
Part of the verilog file and my analysis are expressed below.
// verilog file
// Open File
fp = $fopen("AF.hex", "wb");//must be binary read mode (...)
ASIC Design Methodologies and Tools (Digital) :: 06-30-2010 02:47 :: xang :: Replies: 0 :: Views: 3566
In my code im using $readmemh to read hex values from a text file in which alot of the values are negative. verilog is treating them as positive and returning erroneous results. Can someone please help me deal with this problem? I really need to figure out a way to recognize these negative hex values.
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-08-2010 14:14 :: UFK :: Replies: 2 :: Views: 1271
This code was implemented on a CPLD but it is not working. Please help!
// This code should show the position of the push-button pressed by glowing appropriate leds.
output reg row,led;
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-20-2012 04:48 :: pranavm1502 :: Replies: 2 :: Views: 1856
1. Any assembler or hex code generator for AMD?
2. Any sample design of for example 8-bit cpus, 16-bits cpus, etc with AMD?
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-05-2004 08:58 :: jimjim2k :: Replies: 7 :: Views: 2880
What u are looking for is hardware -software co -simulation ... how is it done in simple terms ... compile ur program .. get the binaries .. convert it into hex format ... load it into a memory model in verilog or vhdl then run it (normal h/w verification way ) . But what u want to do is port your OS to a processor .. doing this on simulation will
ASIC Design Methodologies and Tools (Digital) :: 03-21-2005 01:51 :: semiconductorman :: Replies: 2 :: Views: 943
Interview question I guess :) .........
It is rather simple here the '-' sign does not denote any value .Remember that in verilog the valid values are only 1,0,X,Z . So when you assign "-" . this is treated as a string and then the ascii value of this "-" is taken which is 2D is hex. The '0' bit value of "-" is ascii is then assigned to the varia
Electronic Elementary Questions :: 05-26-2005 04:15 :: semiconductorman :: Replies: 2 :: Views: 1489
$fopen will only open the file. To do any file operation in verilog this has to be done first. for reading from file try $memreadb (for binary files) or $memreadh (for hex files).
U also have $fscanf, $fgetc, $fread to read files. Not sure
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-10-2006 05:21 :: vivek :: Replies: 6 :: Views: 34471
I can't think of any technical advantage. When writing code, hexadecimal notation is simply more compact and usually easier to read than binary notation.
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-19-2006 19:33 :: echo47 :: Replies: 5 :: Views: 2543
Ineed aprogram that covert hex file generated from kiel to a form that include full content of program memory ,so that it's easy to implement in my 8051 ROM module.
Thanks in advance
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-07-2007 09:57 :: Elnegm :: Replies: 2 :: Views: 1149
To extract data from Intel hex file use hex2BIN converter ..
It can be downloaded from here:
Embedded Systems and Real-Time OS :: 02-09-2007 02:27 :: IanP :: Replies: 3 :: Views: 829
For simulation, by using verilog how can I code the programme to obtain pixel data from file hex form. Plesea show me the books, syntax, etc...
Thank you very much
Look for $readmemh in google. For custom file read you can also use $fscanf
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-24-2007 10:00 :: aji_vlsi :: Replies: 5 :: Views: 965
Recently i was reading verilog LRM for this, and i came to know about
Usign it I can read one line at a time, that too in my convinient format(i.e. hex)....
Anyway, thanks a lot for your replies...
ASIC Design Methodologies and Tools (Digital) :: 09-17-2007 02:00 :: bharat_in :: Replies: 3 :: Views: 3657
may someone know how to translate hex into binary by vhdl! if you know, pls tell me! thanks!
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-27-2007 02:37 :: shenql :: Replies: 13 :: Views: 14448
As I got a notification to send the final solution from admins
here you are
1- use readmemb, readmemh for read binary and hex data. This option is supported in most of tools
2- use PLI (standard file IO functions) like is more powerful and gives more flexibility but not supported in trial version, student version tools
ASIC Design Methodologies and Tools (Digital) :: 04-08-2009 13:02 :: haytham :: Replies: 3 :: Views: 1336
x <= '0' Bit
x <= O"57" Octal
x <= X"2F" hexadecimal
x <= "00000" Binary
x <= B"00000" Binary
x <= 1200 Decimal
Note that, for instance with hexadecimal, the destination must be a vector which fits exactly (4/8/12/16/20/.... bit vectors).
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-03-2009 10:38 :: Marcel Majoor :: Replies: 1 :: Views: 977
Hi, I'm trying to write a simple module in verilog that I can use on an APEX APEX20K200EFC484 starter (Excalibur) board to write characters to the display.
I have seen some examples here for other displays and FPGAs but finding it very difficult to get the correct information on how the display decoder works.
This looks promising: www
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-08-2009 03:20 :: alias__neo :: Replies: 0 :: Views: 1422
I've bunch of 14-bit data points which I would like to convert in hex to use with $readmemh in verilog.
Any clue how to do that? It seems there is no direct function to do that in MATLAB and Excel can not handle more than 10-bit data!!
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-28-2010 02:11 :: Jack// ani :: Replies: 0 :: Views: 712
To read array from test bench use:
In above case you read hex data from data.txt file to read memory data. You can use for loop to traverse through all the location.
To write data to text file use: $dumpfile("data.txt");
Hope this helps
Network :: 04-21-2010 02:35 :: Jack// ani :: Replies: 1 :: Views: 2702
Im trying to read an image on verilog. Im supposed to carry out a DWT on an image matrix. Since i couldnt figure out how to convert an image into matrix (hex) on verilog i used MATLAB imread for it. Now that i have the matrix for it how can i save it on verilog? Should i access it on verilog using it (...)
Digital Signal Processing :: 05-05-2010 08:59 :: UFK :: Replies: 3 :: Views: 1902
Yes it is possible and it's not hard to do.
You can get the simulation time using this:
And then save it in a file using this:
integer file_ptr; // file pointer
file_ptr <= $fopen("C:\\...whatever...\\your_file.txt", "wb");
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-24-2010 13:30 :: fcfusion :: Replies: 1 :: Views: 654
how many bits of decimal number u are getting? and from which kind of interface...? If you are getting decimal from software its better to convert it in software and take it on FPGA in hex form only....
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-31-2010 07:00 :: bapodradhairyab :: Replies: 2 :: Views: 3931
$readmemh() is very usful for such tasks.
Need to define an array, the file should hold hex values (in text, not a binary file), readmemh loads the values into the array.
google readmemh and you'll find a few examples.
PC Programming and Interfacing :: 11-08-2010 07:05 :: yoramgr :: Replies: 1 :: Views: 917
i have 8051 chip which is already programmed . i dont know the program. is it possible to get the hex code from the 8051 chip and then convert it into .asm
plz tel d procedure.
Microcontrollers :: 01-26-2011 02:17 :: rasikab30 :: Replies: 18 :: Views: 2308
HI How to model a memory as 2d Memory array in verilog ?...We have to load an hex file as the programFile for a Microcontroller in the Program ROM......
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-02-2011 23:47 :: blooz :: Replies: 2 :: Views: 1549
What is the best way to read a textfile that contains decimal number (eg. 2.987) into verilog?
At the moment, I convert the values to hex using matlab (using num2hex). But when I use readmemh, it assumes that the 32bit variable is a 'regular' number and not a floating number?
Any suggestion will be greatly appreciated.
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-11-2011 18:22 :: chikaofili :: Replies: 0 :: Views: 1452
A flexible method, that's also used by Altera IP is to write the data in hex format and specify it as init file for an altsyncram block. Alternatively, $readmemb and $readmemh is supported for synthesis of verilog code with inferred RAM/ROM blocks.
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-17-2012 05:19 :: FvM :: Replies: 7 :: Views: 1722
I am trying to load an srec file into to a byte-addressable memory in verilog
The memory has to be one megabyte and has to have a 32-bit address input
- I am running into the following issues
-according to the srec format I have to load data into specific addresses. how to map hex addresses to a verilog memory like this one
reg [ (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-15-2012 23:40 :: Hassan Munir :: Replies: 1 :: Views: 680
Use readmemh/readmemb system functions to read from the .raw file. To confirm what is read is correct or simply see the hex contents of the raw file, use a hex editor where you can simply open the raw file and see the hex numbers.
ASIC Design Methodologies and Tools (Digital) :: 10-09-2012 03:51 :: vijay82 :: Replies: 8 :: Views: 1647
As I don't have a model for ROM so I am creating it by declaring an array of specific depth. Now my problem is to store the content of hex file (generated by processor compatible compiler) to the array in such a way that the fixed size value written on each line in the hex file shall be stored on each address of array. So that I can use it as ROM.
ASIC Design Methodologies and Tools (Digital) :: 10-12-2012 05:30 :: er.akhilkumar :: Replies: 0 :: Views: 393
So my professor gave me this problem and no background what so ever on this subject. He just talked about it for 5 minutes in class and gave us this huge problem to solve. The one thing he said to do is a state machine. So far this is what i have come up with. So basically I have to use a state machine to turn this C code into verilog. I have to fi
PC Programming and Interfacing :: 12-10-2012 15:16 :: Franci25 :: Replies: 0 :: Views: 452
what should provide the 72 bits? a PC another microprocessor, through a memory?
my input file is a hex file generated by matlab, now I need to input this file in verilog testbench
ASIC Design Methodologies and Tools (Digital) :: 04-25-2013 00:41 :: jiyaa :: Replies: 5 :: Views: 926
Internal number representation isn't hex or decimal, just binary. You should figure out what you mean with "concatenate". I guess you mean the operation c = a + 100*b
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-21-2014 05:39 :: FvM :: Replies: 6 :: Views: 380
If data is equal to 68 or lesser than 68, it returns "True".
8'h44 means 8bits data expressed as hexa decimal, 44.
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-01-2014 05:16 :: pancho_hideboo :: Replies: 6 :: Views: 292
If you want an audio interactive tutor to learn verilog or VHDL.. I did upload it for someone who did ask me... ES PERAN verilog & VHDL.
If you are interested let me know
Professional Hardware and Electronics Design :: 08-06-2001 13:01 :: henrik2000 :: Replies: 5 :: Views: 10010
i do not find site -- picall Firmware .hex
Professional Hardware and Electronics Design :: 01-09-2002 02:37 :: z543g :: Replies: 0 :: Views: 1446
Uploaded file: verilog_synthesis.rar
ASIC Design Methodologies and Tools (Digital) :: 02-17-2002 06:25 :: roli :: Replies: 9 :: Views: 3338
open verilog international programming reference manual
A 350 pps pdf ebook.
Uploaded file: open-verilog-International.programming-reference-manual.pdf
Microcontrollers :: 02-21-2002 02:58 :: jimjim2k :: Replies: 2 :: Views: 1578
open verilog Language Reference Manual
A 391 pps pdf ebook.
Uploaded file: verilog Language Reference Manual.pdf
Microcontrollers :: 02-21-2002 03:08 :: jimjim2k :: Replies: 2 :: Views: 2647
Classware Handbook on verilog HDL
A 32 pps ebook.
Uploaded file: verilog-manual.pdf
Microcontrollers :: 02-21-2002 06:11 :: jimjim2k :: Replies: 1 :: Views: 2522
Some useful verilog ebook
Prof. Don Thomas, carnegie Mellon University.
The verilog Hardware Description Language
Dr. Daniel C. Hyde's Handbook on verilog HDL.
A short but in-depth introduction to verilog HDL.
Gerard M Blair's On
Microcontrollers :: 02-21-2002 20:45 :: mimosa :: Replies: 9 :: Views: 8254
There are three free verilog simulators available with limited capabilities:
SILOS III from Simucad.
SILOS III's high performance logic and fault simulation environment supports the verilog Hardware Description Language for simulation at multiple levels of abstraction. The Environment's state-of-the-art architecture incorporates an exclusive
Microcontrollers :: 02-21-2002 20:47 :: mimosa :: Replies: 10 :: Views: 7633
There are two free verilog waveform viewers:
WaveViewer by SynaptiCAD is a free verilog VCD waveform viewer. WaveViewer also imports waveforms from HP logic analyzers, TDML documents, and many gate level simulators. The viewer allows the placement of markers, delays, setups and holds. Download the free viewer from
Microcontrollers :: 02-21-2002 20:50 :: mimosa :: Replies: 2 :: Views: 4001
For reduing the debug effort,how to write best RTL code?
ASIC Design Methodologies and Tools (Digital) :: 02-21-2002 23:19 :: prisnow :: Replies: 10 :: Views: 3604
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-22-2002 00:44 :: coolsniper :: Replies: 5 :: Views: 1670
ASIC Design Methodologies and Tools (Digital) :: 02-23-2002 08:11 :: roli :: Replies: 11 :: Views: 3894
verilog-XL Reference Manual
A 264 pps ebook.
Uploaded file: verilog-xl.pdf
Microcontrollers :: 02-24-2002 03:50 :: jimjim2k :: Replies: 0 :: Views: 3775
I am attaching a very good tutorial on writing verilog Testbenches.
Its available on this link. You have to register to download this Reading
Microcontrollers :: 05-15-2002 01:59 :: DrBELL :: Replies: 0 :: Views: 11719
this is the latest verilog standard reference.
Uploaded file: 1364_2001.pdf
Microcontrollers :: 02-28-2002 17:06 :: KARLZ :: Replies: 4 :: Views: 3754
Does any one know how to translate verilog (GATE Level) to Spice(with Standard Cell)?
ASIC Design Methodologies and Tools (Digital) :: 03-04-2002 20:17 :: joe_chuang :: Replies: 12 :: Views: 6723