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High Swing Cascode

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26 Threads found on High Swing Cascode
One possibility: For the first stage, consider using a folded cascode topology (with PMOS inputs) to get high gain with good voltage headroom. For the second stage, use a topology for low output impedance and good swing - eg a common-source stage with active load. You may want to consult a good analog IC design book (such as Razavi's) (...)
Any high swing cascode CM will works
Hi BartiebyScrivener I think: Vb2 = Vtn + Vdsat7 + Vdsat9 Vb1 = VDD - (Vdsat4 + Vdsat5 + Vtp) Choose Vdsat 7 + vdsat9 and (vdsat5 + vdsat9) small if want high output swing
Hi Dominik, Thanks for the help. My design requirement dictates that my output voltage swing should go upto 3.5V and as low as 0.5. Therefore, i need to use higher supply voltage. Even if i use a thick gate oxide transistor, i will have to use two of them in cascode. This is because thicker gate oxide transistor has breakdown voltage of (...)
Hi Majero, The main mirror M3 and M2 need to be sized according to the matching you need between your input and output current. With that size you can look at the Vdsat you get, if that is not enough you can increase the size more. Once you have sized that sufficienctly, you can size M1 and M4 as large devices so that
good day everybody.. i'm doing simulation right now about high swing cascode current source. this is about the self bias high swing cascode current source. please refer below for the figure. (i found this circuit in CMOS Analaog Design by Allen, 2nd edition page 133.) In this (...)
To design a unity gain cmos buffer amplifier(for 45nm technology): Band Gap Reference (BGR) Input: 1.2+_50 mV (+_ means plus or minus) Output: BGR+_10V Cload=3.5pF or higher Iload(current load) 50uA Vdd=3.3V+_300mV Idc<100uA PSRR>60dB FREQ:1MHz Temp:-45 to 125 degree C
Hello, I'm desiging a FCDA for a 60dB gain, high output swing. but, my load capacitor is variable from 20fF to 100fF max. I have a phase margin <45° can someone help me please? look at the attached file.
i advice u first stage folded cascode (PMOS as input) and second stage is CS (sure NMOS the input), this circuit gives u low in settling time and high gain with phase margin regards
An another point of view. Small bottom MOST only is used in high frequency application. If consider low offset, noise applications and bandwidth trade-offs mirroring MOSTs must operate at strong inversion level with small value of Gm. Usually this gives small W/L ratio (high ro1). Influence of cascode MOSTs on offset and noise really (...)
the vds if M6 is set by the vgs of M5 which in turn is set by the size of M5.This is a high swing cascode. mostly used as a load in cascode opamps(folded,telescopic etc) amarnath
try this book
Advantage : higher gain Disadvantage : Limited output swing
what process will you use. your current is quite high.
There is another question about device sizing of the other high-swing bias circuit. What does the objective "VDS1=R*Vd1,sat" mean ? And why Vd6,sat equates Vd1,sat in advance!
i have an op-amp which is used for LDO. the Vref is about 1.16V. At that point, my op-amp's offset is ~6mV will this a problem for my LDO? How to lower the op-amp offset? my op-amp is only one stage op-amp which using high swing cascode current mirror as load current. thanks in advance :)
2) And then this is really confusing. Since I'm designing a cascode, I should be able to get a high gain from this stage. But, 0.016V at the output, and 0.25v swing at the input, it seems to me that this stage is decreasing the gain. how could that be? Hi airboss, I think a little explanation could clarify u and meet
I am designing a opam with 70-80db gain, and more than 20MHz bandwidth, and real-to-real output. Can some one give me some suggestions about the structures? THANKS GDHP
Because source followers suffer bad performance due to body-effect + they need high voltage ( swing will be within Vgs of transistor .. can be large for low suppliues ) whereas common source provides higher swing, no body effect
you could use a folded cascode with gain boosting. Have a high swing folded cascode design.
send me a design example of high swing cascode with both PMOS and NMOS devices. Thanks in advance
A full differential amplifier with 0.13um process,the threshold voltage is about 0.3v.I want a GWB of 800MHZ(1pf capacitor),Gain of 80dB,and the output swing is -0.3~0.3.
I think you may need self biasing using resistors but if u need high swing try the folded cascode try to check anaolg design book like razavior meyer
Hi there, i've failed to bias wide-swing cascode current mirror properly using 1.8V supply. The circuit i used is Fig 6.11 from Ken Martin book. Is it impossible to bias 4 transistors in cascode because of 4xVdsat? I need high current so that i can reach high slew rate. Can anyone help me or give me (...)
Here is your standard fully diff. folded cascode op amp. Im using 0.18um technology, 1.8V supply. Im not getting the correct open loop output. My open loop gain is way tooo low. Cant even get a gain of 1. I know that all transistors should be operating in the saturation region. How do i go about setting all transistors to be in saturation? Do i set
Hi.. any one know any technique which can be used to design a current mirror capable of providing 10mA with low voltage headroom (less than 0.3V for the transistor to operate, the signal swing takes about 2.7V with 3V power supply) and high output impedance (more than 5k)? Is it possible cascode current mirror can achieve such a low voltage (...)