Search Engine www.edaboard.com

High Swing Cascode

Add Question

68 Threads found on edaboard.com: High Swing Cascode
good day everybody.. i'm doing simulation right now about high swing cascode current source. this is about the self bias high swing cascode current source. please refer below for the figure. (i found this circuit in CMOS Analaog Design by Allen, 2nd edition page 133.) In this (...)
idea to make well matched current mrrors is simple: ids=B(Vgs-Vth)^2(1+λVds) make Vgs (it is normallly done when you connect gates and sourcea) and use matched mosfets(important matching is for mosfets near gnd) with same Vds (by proper circuit configuration and biasing). For matching L has to be high enough ...say 4-10xLmin... For high outp
Hi.. any one know any technique which can be used to design a current mirror capable of providing 10mA with low voltage headroom (less than 0.3V for the transistor to operate, the signal swing takes about 2.7V with 3V power supply) and high output impedance (more than 5k)? Is it possible cascode current mirror can achieve such a low voltage (...)
Hi there, i've failed to bias wide-swing cascode current mirror properly using 1.8V supply. The circuit i used is Fig 6.11 from Ken Martin book. Is it impossible to bias 4 transistors in cascode because of 4xVdsat? I need high current so that i can reach high slew rate. Can anyone help me or give me (...)
While it will increase CMRR,which is mandatory, the cascoding of the tail current source has nothing to do with the Av part of it. If you look into the differential half circuit, you will notice that the tail current source will never come into that part. Moreover,in your case, the OPamp might need a very high PSRR- as well. Hence they will hav
There is another question about device sizing of the other high-swing bias circuit. What does the objective "VDS1=R*Vd1,sat" mean ? And why Vd6,sat equates Vd1,sat in advance!
try this book
I am designing a typical cascode high swing NMOS current mirror. Trying to determine on the transistor size here. In my opinion, the bottom transistor can be minimum length because its Vds doesn't change much due to the buffer of cascode transistor above, while the cascode transistor should use longer length (...)
how do i generate Vbn Vbp Vcascn Vcascp Vbcm??? if opamp is fully differential.... look up bias generators and high-swing cascode mirror bias this link is a good start, then you need a second branch of mirrors to bias the other
Here is your standard fully diff. folded cascode op amp. Im using 0.18um technology, 1.8V supply. Im not getting the correct open loop output. My open loop gain is way tooo low. Cant even get a gain of 1. I know that all transistors should be operating in the saturation region. How do i go about setting all transistors to be in saturation? Do i set
the reason is most probably due to different Vds.use a configuration that has high rout may be cascode or folded cascode
i am trying to design a triple cascode (telescopy) OTA, but I don't know how to generate the BIASing structure of this high swing OTA. thx
Did u try folded cascode with source degeneration. Use high swing cascode at the ouptut.This will solve ur problem for sure. 20 MHz is easily acheiveable.
send me a design example of high swing cascode with both PMOS and NMOS devices. Thanks in advance
i have an op-amp which is used for LDO. the Vref is about 1.16V. At that point, my op-amp's offset is ~6mV will this a problem for my LDO? How to lower the op-amp offset? my op-amp is only one stage op-amp which using high swing cascode current mirror as load current. thanks in advance :)
I suggest it serves for bias purpose. For example, bias of high-swing cascode current mirror. First nmos in sat. region gives Vth1+Vov1, and others in triode region gives +Vov2. Together Vth1+Vov1+Vov2 properly bias cascode nmoss in cascode current mirror. I think so.
that's design. first choose the currents (approximately) in each branch then choose the W/L to give the saturation voltage you desire. Try 0.150v Vdsat for the mirrors, size M7/M8 to give the output current you need, and choose M2/M9 to set the class AB current in M7/M8 not too high. PS - you don't bias using voltage, you bias using current
The general goal is to bias the transistors which signal travels in the saturation region to work with large gain and good linearity.Better to save more swing at the same time. I just wonder the structure of the bias circuit for a OP amplifier. How to bias each transistor in a stacked configuration??[/quote
wide swing cascode mirror is good it helps in keeping same vds for both the transistors and setting higher vgs helps especially vth{threshold} mismatch in the mirror .Probably montecarlo will still be worse if transistor dimensions are not good .
the vds if M6 is set by the vgs of M5 which in turn is set by the size of M5.This is a high swing cascode. mostly used as a load in cascode opamps(folded,telescopic etc) amarnath
i suggest u use folded cascode with CS out put stage it has high swing output, high settling time, use Nmos transistors as differential input
to mirror current exactly,the ratio of W/L of the mirrored and mirroring transistor should be exact,too;i want to ask ,for W/L=50/0.5 with finger number=10 (mirroring transistor)and W/L=10/0.5 with finger number=2 (mirrored transistor),how is the layout?if i use the technique of sharing source and drain,the parasitic cap may be d
I designed a Phase-Frequency-Detector and an Charge-Pump, as blocks of a PLL. And what parameters I should measure of this two blocks? The mismatch of Iup and Idn and the stability of the CP? And anymore? About the current mismatch, what method I should use? The method I used is to connect a dc voltage source with the CP ou
Hi Majero, The main mirror M3 and M2 need to be sized according to the matching you need between your input and output current. With that size you can look at the Vdsat you get, if that is not enough you can increase the size more. Once you have sized that sufficienctly, you can size M1 and M4 as large devices so that
I have tried with the self biased high swing cascode current source taken from the book "CMOS Analog Circuit Design" by Phillip E. Allen, Douglas R. Holberg.
PSRR is linked to output conductance of transistors as well as matching among them. Try to increase channel length of your current mirrors and increase the area of transistors in general to improve matching. Also, actually it depends on the Vth of your transistors, 3V is high enough to accomodate cascodes. Miller compensation could also help.
I need a Opamp with DC gain>80dB and Unity Gain frequency >100MHz. At first I try to design it with the class-A two-stage structure. but it is difficult to satifiy both the DC gain and phase margin. Who can give me some advice about how to design. such as, if class-A structure can meet the request, or which kind of structure is more suitable. and
Rail to rail: differential amplifier with NMOS, current source to the gnd in parallel with differential amplifier with PMOS, current source from Vdd *NMOS diff does not work with small voltages, but PMOS diff can. *PMOS diff does not work with high voltages, but NMOS diff can. *In the middle both PMOS and NMOS amplifiers can work, but the g
If u have twin tub process u could isolate the cascode transistors. Anyway for PMOS u can do that. The body effect would increase the Vt of the cascoded device. I would only use isolation if it critical and i have low supply voltage. Also if you are designing high swing cascodes then the back bias observed (...)
A full differential amplifier with 0.13um process,the threshold voltage is about 0.3v.I want a GWB of 800MHZ(1pf capacitor),Gain of 80dB,and the output swing is -0.3~0.3.
you can refer this paper -----"DESIGN AND OPTIMIZATION OF A high PSRR CMOS BANDGAP VOLTAGE REFERENCE". Try.
you could use a folded cascode with gain boosting. Have a high swing folded cascode design.
I am designing a opam with 70-80db gain, and more than 20MHz bandwidth, and real-to-real output. Can some one give me some suggestions about the structures? THANKS GDHP
when you design a high BW opamp, the parasitic capacitor need be considered, such as cgs of M3. and the Cgs and gmbs of M9 when the compensation cap connected the source of M9 with the second stage output, because there is a zero at right plane, which affects your phase magin.
In general the active regulated cascode is the right choice for solving the trade between DC gain and output voltage swing. BUT THIS ARCHITECTURE IS BAD! WHY? Because the voltage across source/drain of m1 is vth-vdsat(ma1). That is higher than vdsat(m1). So you need a different amplifier. You can use instead of ma1 a NMOS source (...)
what are the advantages and disadvantages of folded cascode amplifier?? Can be designed rail to rail input voltage.... low output swing... high output impedance.....what else??
"Pseudo-differential " means that there is no common tail current source like in real differential pair. Added after 2 minutes: BTW would u plz upload the thesis. thnx Added after 2 minutes: a guess about the bottom MOSTs M1,M4 are the
Hello , The available best solution for designing high Slew Rate /Ultra low power bias current Amp is using Class-AB output stage .The available Class-AB output Topologies are Floating Current Source biased Output Stage & Source Follower type Output stage .each have its own adavantages....Floating Current source biased Output Stage type Amp is
hello i read that cascode structure has advantages on high reverse isolation and reducing the effect of Cgd plz explain them, how are they possible?? can anyone give me some material on this? thank you deepak
ur OPAMP has very small load, any way u have to know what is he poles and zeros of ur system for folded cascode with NMOS differential input u can refer to razafi book. any way the way of getting high phase margin and settling time it can be by increase the current of the cascode, to get haigh gain increase the current of the differenial (...)
Hello, I'm desiging a FCDA for a 60dB gain, high output swing. but, my load capacitor is variable from 20fF to 100fF max. I have a phase margin <45° can someone help me please? look at the attached file.
Class AB by definitition is used for high so you have the correct idea. However your question is open-ended. google this etc. and if you have any issues, come back with detailed question on a specific issue.
isn't clear how requirements for 50dB SFDR deal with 1.6MOhm out impedance. Typical load of high speed current DAC - 50Ohm resistors. SFDR can be reduced by VARIATION of (output || load) impedance depending on amplitude/code. I think that is necessary to recalculate you spec requirements in this aspect.
Hi Dominik, Thanks for the help. My design requirement dictates that my output voltage swing should go upto 3.5V and as low as 0.5. Therefore, i need to use higher supply voltage. Even if i use a thick gate oxide transistor, i will have to use two of them in cascode. This is because thicker gate oxide transistor has breakdown voltage of (...)
1) The channel length is dropping due to digital guys...The maximum voltage which can ever be applied across the D and S of the FET is also dropping, to prevent electric breakdown of the material due to high electric fields....E =V/L as L decreasing => E increasing...thus to maintain E low enuf the V is also decreasing => VDD is decreasing thus the
I think the first can get the higher gain since the cascode output, the second is not easy to increase the gain since the gain mainly acquire from the output stage. But the first output swing is small, but i think it meet our application in bandgap error opamp. The second reason is the bandgap Vbe is low, so it need a Pmos input.
You have to optimize for high Gm and high A. Therfore Gm= 2* Ids/(Voverdrive). For A ~ Gm*rds. For high rds in cascode it's better to have less current flowing through branch b. That's the deal.
Basically, you need to break the loop of the CMFB. You can break the loop at any point around the loop but the result (Phase Margin) will be the same. The best loop breaking is between the CM dc extraction resistor and opamp that you used for comparing the reference voltage. Then you run AC analysis and proble the gain and phase from the output ove
Because source followers suffer bad performance due to body-effect + they need high voltage ( swing will be within Vgs of transistor .. can be large for low suppliues ) whereas common source provides higher swing, no body effect
I think that the closed loop gain would be equal 2. This doesn't mean that Opamp's gain is 2. Also, a 1G Gain Bandwidth product is weigh too high. Most probably it will be impossible ( but can't be 100% sure of that ). I think for the given speed and input range, the telescopic is not a very good candidate ( very limited i/p range ). Perhaps