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20 Threads found on edaboard.com: **Hold Equation**

Hello All,
**equation** for
setup : t(ck-q) + t(combo) < Clock period + clock skew - setup
**hold** : t(ck-q) + t(combo) > clock skew +**hold**
I want to know that how skew will calculated in following situation for setup and **hold** violation on the basis of above **equation**. (...)

ASIC Design Methodologies and Tools (Digital) :: 07-08-2014 10:21 :: maulin sheth :: Replies: **3** :: Views: **1312**

To Check Setup : The setup multiplier Can be N. The launch will happen at 0th clock cycle and setup capture will happen at Nth clock cycle.
To check zero cycle **hold** check :
set_multicycle_path -**hold** 1
The rule is: **hold** cycle = (setup argument) -1 - (**hold** argument)
Based on this (...)

ASIC Design Methodologies and Tools (Digital) :: 05-10-2013 11:15 :: sam536 :: Replies: **2** :: Views: **1904**

Can anyone help me prove why there will not be any **hold** violations if launch ff is pos-edge and capture ff is neg-edge ?
Also, can you help me understand setup scenario also ?

ASIC Design Methodologies and Tools (Digital) :: 03-12-2013 04:28 :: nandithaa_m :: Replies: **18** :: Views: **2662**

Hi Venkat,
Can you elobrate this question little more?
As in digital logic timing formulas, Skew time, Cylce time, Setup time, **hold** time play major role. I'm not sure about Tlaunch and Tlaunchclk. maight be similar terms with different name.
BR
Shashi

ASIC Design Methodologies and Tools (Digital) :: 01-18-2012 07:09 :: mishrashashi :: Replies: **3** :: Views: **661**

Setup is check at each step from synthesis to sta.
**hold** time after the clock tree.

ASIC Design Methodologies and Tools (Digital) :: 01-06-2012 17:24 :: rca :: Replies: **4** :: Views: **907**

Setup time **equation**:
Tcq + Tcomb> Tskew + T**hold**
**hold** time **equation**:
Tcq + Tcombhold violation depends on the clock path delay. Before CTS clock path is taken as ideal. We don't have skew and transition numbers of the clock path. (...)

ASIC Design Methodologies and Tools (Digital) :: 11-07-2011 05:57 :: yadavvlsi :: Replies: **10** :: Views: **1164**

hi Bhargav,
Just wanted to know few things before answering your question..
**hold** Slack= Data arrival time - data required time
and
setup slack = data required time - data arrival time...
keeping these 2 **equation** please let me know what exactly you want to ask ???

ASIC Design Methodologies and Tools (Digital) :: 06-13-2011 04:41 :: birdy123 :: Replies: **2** :: Views: **1232**

hello everyone
i am working on simulink.
i have a system where i sample my signal using sample and **hold** block from simulink library. Then i have to use a "Matlab Embedded" block from the "User defined" sublibrary.
The "Matlab Embedded" block should have the **equation** of charging a capacitor which charges during thr **hold** time of the (...)

Analog Circuit Design :: 02-13-2011 11:06 :: pankaj jha :: Replies: **0** :: Views: **1187**

hello everyone,
i am trying to write the **equation** for charging of a capacitor.
Vo = Vin(nT)*(1-exp(-t/30)); for nT< t<(n+1)T.
where, the T=**hold** time for a sample and **hold** circuit.
I have to write this **equation** in matlab. Can anyone suggest me the code....

Analog Circuit Design :: 02-13-2011 10:56 :: pankaj jha :: Replies: **0** :: Views: **1171**

Dear EDA Form Members,
I was wondering if anyone knew where I could buy/find solutions to Balanis Antenna Theory (Third Editon).
I now **hold** a job with an RF company and many of the things people are asking me questions about I have not used in a long time.
therefore I am trying to teach myself out of Balanis Antenna Theory book and I am

RF, Microwave, Antennas and Optics :: 09-08-2008 21:42 :: b4bb4ge :: Replies: **2** :: Views: **2310**

Hi All,
Can any body tell me
What are the possible questions on SET-UP and **hold** time for interview.

ASIC Design Methodologies and Tools (Digital) :: 01-12-2009 13:22 :: spartanthewarrior :: Replies: **2** :: Views: **12026**

hi every body
again and again the SFDR, i am designing sample and **hold** my target to get high SFDR, but in fact How much SFDR needed for sample and **hold** circuit 10bit 50 MS/s?
i am loking to **equation** explain the relation between the sampling frequency, No of bits and the SFDR.
regards

Analog Circuit Design :: 01-15-2008 20:02 :: wael_wael :: Replies: **4** :: Views: **873**

Can anyone explain me these **equation**s with the help of a diagram
bcz slight confusion is there
late launch clock delay+late data path delay <=Tclk +early capture cck delay-Tsetup
In this **equation** we are indirectly satisfying the **hold** not setup......bcz if we make the data late then we will get setup violation no

ASIC Design Methodologies and Tools (Digital) :: 12-18-2007 05:59 :: cooldude040 :: Replies: **3** :: Views: **1488**

Elementary Electronic Questions :: 06-21-2007 08:34 :: eeeraghu :: Replies: **4** :: Views: **2272**

Since most standard cell flops have **hold** time very close to 0 (much smaller than CK->Q time) so unless there is a fair amount of clock skew it is next to impossible to not meet **hold** time.

ASIC Design Methodologies and Tools (Digital) :: 05-25-2007 03:10 :: eternal_nan :: Replies: **5** :: Views: **1809**

There are two type of propagation delay:
1) propagation delay min (sometime we call it contamination delay)
2) propagation delay max
In setup time calculation, we apply max propagation delay on other hand we use contamination delay in **hold**time expression.
Hence the **equation** should be:
Tc-q_max + Tsetup + Tcskew + Tcomb_max <= T (se

ASIC Design Methodologies and Tools (Digital) :: 01-23-2007 11:35 :: barkha :: Replies: **3** :: Views: **5668**

The maximum time is governed by the setup time **equation** and the minimum time is defined by the **hold** time **equation**. If you don't know the way to analyse for setup time and **hold** time analysis let me know. I'll write up that stuff and attach it. Make sure you put it as personal message least I miss this post.

ASIC Design Methodologies and Tools (Digital) :: 10-15-2006 20:40 :: semiconductorman :: Replies: **7** :: Views: **1233**

the **equation**s u need:
(1) time constant of load (τ) =Rload*Cload=50*5=250 ps
(2) for any N-bit resolution converter, the following **equation** must be **hold**.
2^N*LSB*exp(-t/τ) < LSB/2
==> t > τ*(N+1)*ln(2)
==> 1/f > τ*(N+1)*ln(2)
(3) in ur case, f=1GHz, τ=250ps, ln(2)~=0.7, ==> N < 4.8
So, in theorem, u will (...)

Analog Circuit Design :: 02-27-2006 03:51 :: Btrend :: Replies: **7** :: Views: **1283**

tpd - propagatinal delay
tco - combinational delay
to satisfy setup conditions,
Tclk >= Tsu + Tco,max + Tcq
to satisfy **hold** conditions,
Th > Tcq + Tco,min

ASIC Design Methodologies and Tools (Digital) :: 01-10-2006 12:40 :: anjali :: Replies: **2** :: Views: **6608**

1) x^2 + y^2 - 64(x^2)*(y^2) = x^4 + y^4 - 62(x^2)*(y^2)
x^2 + y^2 = x^4 + y^4 + 2(x^2)*(y^2)
x^2 + y^2 = (x^2 + y^2)^2
now let a:= x^2 + y^2 then:
a = a^2
a^2 - a = 0
a(a-1) = 0 => a=0 or a=1
=> x^2 + y^2=0 or x^2 + y^2=1
which means the **equation** doesnt **hold** for any x,y.
2) √(

Mathematics and Physics :: 07-04-2005 14:28 :: mayyan :: Replies: **7** :: Views: **1538**

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