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# Hold Multicycle Path

12 Threads found on edaboard.com: Hold Multicycle Path

## Multicycle path constraint apply scenario?

if you have a path where two registers use the same clock enable that is a periodic clock enable, then you know that the setup and hold time can be much longer for these registers as they really only get updated once every N clocks.

## Set_multicycle path regarding

I think it's unable to meet both setup and hold for such, if you using usual library cells. And it's also un-reasonable for the real DFF to have setup and hold both equal to 0.

## Multicycle path: Can setup value can be less than hold value.

Hello All, In the case of Mullticycle path, the setup value is more than the hold value, however if we consider multi clock domains in the multi cycle path, can setup value be less than hold value? Please provide your views.

## Doubt regarding multicycle path

Coz since by default hold will be just one cycle befoire the setup. So in this scenario the hold will be calculated at 2nd clock pulse. But we don't require this as to meet this the tool will unnecessarily put many buffers. So we make the hold the first clock pulse by giving the second constarint which u have mentioned. Ho[pe it helped Regards

## setup and hold (multi clocks)

Not sure I understand the question. What do you mean by "setup and hold between two F.F"? If you don't know the phase relationship between the two clocks, even if they are synchronous, then you can still get into trouble. If this is in an FPGA then the tools will take care of meeting timing between ffs. If you're talking about two discrete ffs,

## Multicycle Hold analysis

Can anyone tell me about multicycle hold analysis? Does it affect the frequency of the chip?

## Setup and Hold check in multicycle design!

In a multicycle path of two cycle set setup is checked at the second cycle and hold is check at first cycle. Why?

## Hold violation on multicycle path...........................

Agree with lostinxlation! Another point is : not all the multicycle path contain many conbination logic on data path. Someone may specify the multicycle path for some special requirement. For example, multi-frequency design, Source Syncronous Bus design. In that case, you should be careful about the (...)

## Doubt regarding multicycle path setup and hold anlysis

Hi, In our design we r generating 1MHZ clock from 8mhz clock. There are some logic in design where we are sending data from 8Mhz to 1 MHZ. Do we need to set multicyle paths for setup and hold check? Thanks

## Why Hold time is not considered while calculating Max. Clk Freq.?

In the sequencial circuit, output of flip flops going through cominatinal logic then, again, to flip flops inputs. Thus delay would be combinational delay+setup time of flipflop. hold time would be satisfied inherently.

## Other End Arrival Time

Depending on whether you have a single cycle path, or multicycle path, whether you are checking for setup or for hold, your endpoint clock arrival time is adjusted by the clock period. But yes, unless you have clock arrival at endpoint, how are you going to capture data ? Its applicable for all synchronous (...)

## What does .sdc file contain?

can anyone explain me abt the detail info abt sdc file...... wat i know/:----sdc constraints has, setup & hold time information, clk to every net, timing info for std cells, blocks, io delays & port pins,...............other than this anythin more?? wat abt false path, multi clk path it also conatins or not?? plz do correct me