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22 Threads found on edaboard.com: Hold Time Slow
Yes, both setup & hold violations are possible in the same path. Setup analysis will be done in the slow corner, where as hold is done in the fast corner. Now, look at this way, the combo path consists of only HVT cells ( which usually gives more delay in slow corner, less delay in fast corner ). This is due to delay (...)
Because hold time check is on the same clock edge. Clock slow or fast won't affect the result.
Hi All, As for the SetUp and hold checks, should I run the PT tool twice each time for either SetUp Or hold check? If the tool is able to read slow and fast SDF and libs together, why not running it only once for all kind of the checks? Thanks!
Jeevan , can you discuss why exactly you need hold anaylsis before CTS...hold fixing is not in true sense an optimization process, its a degradation or relaxation step... since we have realistic clock skew, latency, and delay values POST CTS, thats why we do hold fixing after analyzing the final need and hold violations. (...)
We use slow libraries for setup time and fast libraries for hold time voilation check. Why it os so? SETUP: flop_launch_clk_edge->combo_logic_delay->flop_capture_clk_edge. Setup is defined as the amount of time required for the signal to be valid before the capture clock edge. This is effected by delay (...)
Sometimes we may have timing violations at typical corner, especially for hold time.
setup time ( Maxtime) violations occurs when things get slower hold time (Mintime) violations occurs when things get faster. So How do things get slower ? - slower PMOS - slower NMOS - Lower Voltage - Higher Temperature or Lower (...)
I'm trying to use a stepper motor for my first time. I have managed to get it spinning using a 16f84a. But it is getting quite hot, is that normal? And what is the correct way to apply hold torque?
he's right. slow/slow for setup. fast/fast for hold.
Hi ASIC_intl, When the clock signal transation time is too slow and the data signal transation time is too quick, the setup time will be negative. And the setup time + hold time >= 0. The total of setup time and hold can be view as the (...)
in the slow.lib(for example) u can find these two parameters: constrained_pin_transition and related_pin_transition what i want to know is how does tool get these two transition time?thank u remark : constrained_pin is D of a DFF related_pin is CK of a DFF
I think this should take your margin into account,maybe different margins for setup/hold,then the risk is different.
shahal, leeguoxian, Frequency of operation is not as important during scan shifting. Therefore, we can always slow down the freq and/or modify the duty cycle to remove a hold time problem with data lockup latches. If your skew is big, then you will need a lot of buffers or delay cells, which is undesirable for power/area etc.
For setup time you need clock buffer to change clock skew. For hold time you need delay buffer to slow the data.
When hold fail, the chip does not work in any frequency (even 1hz).
can any one tell what all libraries pks tool consists of ? is that timing lib for slow.lib & fast .lib those r for set up hold time of i right.../??? & LEF states only tech files......correct me if i am wrong??? wat all other components pks consists of?
As advice from synopsys, sign-off STA should be four times STA in two corner, slow corner and fast corner. You should run STA by primetime. Use bc-wc analysis mode. Set slow library, check setup time and hold time. Set fast library, check setup time and (...)
To make on chip variation minimum, you should use both stage match and metal match. For hold time check, you can use fast data and slow clock for back-annotated SDF.
hi, can anyone explain me why hold time is not included in the calc of critical freq. is there any particular reason if so please explain me that reason. waiting for reply, with regards, srik.
Hi tut, This weblink doesnt give enough info on how to solve the setup time. It only determine the cause of the setup or hold time violation. I already know the source of my timing violation. I would highly appreciate if u can tell me how to fix the setup and hold time. In asic, to fix (...)
hi, Can someone give me some methods to identify setup time violations after the chip is fabricated... any techniques to know if it is a setup or a hold time violation?? 1. Setup time violation: slow down your chip clock freq., if OK, then it is setup time violation. 2. If (...)
For setup time,it's easy. The system can have a period about (10ns+0.2ns)=10.2ns, which means 98MHz. But for hold time violation 0.8ns, I am rather confused. slow down the system clock has no effect on hold time since hold time compares the same clock edge. (...)