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22 Threads found on Hold Time Slow
Yes, both setup & hold violations are possible in the same path. Setup analysis will be done in the slow corner, where as hold is done in the fast corner. Now, look at this way, the combo path consists of only HVT cells ( which usually gives more delay in slow corner, less delay in fast corner ). This is due to delay (...)
Because hold time check is on the same clock edge. Clock slow or fast won't affect the result.
Hi All, As for the SetUp and hold checks, should I run the PT tool twice each time for either SetUp Or hold check? If the tool is able to read slow and fast SDF and libs together, why not running it only once for all kind of the checks? Thanks!
Jeevan , can you discuss why exactly you need hold anaylsis before CTS...hold fixing is not in true sense an optimization process, its a degradation or relaxation step... since we have realistic clock skew, latency, and delay values POST CTS, thats why we do hold fixing after analyzing the final need and hold violations. (...)
We use slow libraries for setup time and fast libraries for hold time voilation check. Why it os so? SETUP: flop_launch_clk_edge->combo_logic_delay->flop_capture_clk_edge. Setup is defined as the amount of time required for the signal to be valid before the capture clock edge. This is effected by delay (...)
BC***: Best case speed, i.e. high voltage, low temperature, fast nmos, fast pmos NC***: Normal case speed, i.e. typical voltage, typical temperature, typical nmos, typical pmos WC***: Worst case speed, i.e. low voltage, high temperature, slow nmos, slow pmos. I'm not sure what LTCOM is. I'm guessing the COM means commercial grade but it cou
setup time ( Maxtime) violations occurs when things get slower hold time (Mintime) violations occurs when things get faster. So How do things get slower ? - slower PMOS - slower NMOS - Lower Voltage - Higher Temperature or Lower (...)
I'm trying to use a stepper motor for my first time. I have managed to get it spinning using a 16f84a. But it is getting quite hot, is that normal? And what is the correct way to apply hold torque?
While you do timing clouse, you have to make sure that in all the operating conditions your ckt's timings are met and ckt works fine. so to ensure this , we do timing clouser in best case(worst hold check..i.e minimum time) and worst case(worst setup check). While you simulate in bestcase, you will have a smallest delays,(high Vdd, low temperature,
Negative set-up time just means that it is permissible for the signal to arrive after the clock edge and there is usually a corresponding increase in hold time. It can sometimes be seen in situations where there the clock path has a much longer delay than the signal path (between the point where the setup (...)
in the slow.lib(for example) u can find these two parameters: constrained_pin_transition and related_pin_transition what i want to know is how does tool get these two transition time?thank u remark : constrained_pin is D of a DFF related_pin is CK of a DFF
I think this should take your margin into account,maybe different margins for setup/hold,then the risk is different.
Dear All : In DFT, it will add lockup latch where there are different clock domain in one scan chain to avoid hold time violation . But if the skew is greater than half of the cycle , I think lockup latch will not solve the hold time violation . Why don't we add buffer instead of latch ?? Thanks
For setup time you need clock buffer to change clock skew. For hold time you need delay buffer to slow the data.
When hold fail, the chip does not work in any frequency (even 1hz).
can any one tell what all libraries pks tool consists of ? is that timing lib for slow.lib & fast .lib those r for set up hold time of i right.../??? & LEF states only tech files......correct me if i am wrong??? wat all other components pks consists of?
As advice from synopsys, sign-off STA should be four times STA in two corner, slow corner and fast corner. You should run STA by primetime. Use bc-wc analysis mode. Set slow library, check setup time and hold time. Set fast library, check setup time and (...)
To make on chip variation minimum, you should use both stage match and metal match. For hold time check, you can use fast data and slow clock for back-annotated SDF.
The hold time don't affect the frequency. That is, if there is a hold time issue, you can't fix it by slow down the clock. So it's more diffcuity to improve the hold time issue. i think u are incorrect,hold time violations can be (...)
Setup time violations are corrected in two ways. First, extra buffers can be inserted to speed up slow signals. Second, if buffer insertion does not completely fix the setup violation, the placement can be re-optimized. hold-time violations are fixed by inserting delay elements into fast data paths. Excerpt (...)
hi, Can someone give me some methods to identify setup time violations after the chip is fabricated... any techniques to know if it is a setup or a hold time violation??
Hi, Consider a system which works at a clock frequency of 100Mhz. Suppose you have a setup voilation of 0.2ns and hold voilation of 0.8ns calculate the clock frequency at which the system work fine? Hey guys, pls give me equations for tsetup and thold...also along with your answers. Cheers, Gold_kiss