11 Threads found on edaboard.com: How To Implement 3 8 Decoder Using 2 4 Decoder
Are these all the values (77 of them in the list)?
Are the values constant, or are there other values that map to the same values in the second column?
What I'm trying to determine is how many entries in the first column need to be mapped to the second column. As this is a true CAM operation.
As these are decimal numbers they won't necessarily co
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-29-2016 14:09 :: ads-ee :: Replies: 18 :: Views: 317
I am studying AHB and want to implement a simple AHB2APB bridge without split/retry, I have 2 modules inside my bridge 1. AHB Slave + Address decoder and 2. the state machine for APB. i have no clue how to start with the ahb slave and what functionality to implement. it is a single master bridge so i (...)
ASIC Design Methodologies and Tools (Digital) :: 09-28-2013 08:48 :: Maulik Suthar :: Replies: 0 :: Views: 1032
the image below showing how to implement a full adder using a the image F1 is Sum and
F2 is Carry
If the input is 011 that means A is 0, B is 1 and C = 1
If we add 0 0 1 in binary it will give 1 as carry and 0 as sum
Elementary Electronic Questions :: 09-19-2011 11:47 :: Jakes9x :: Replies: 0 :: Views: 943
Can anyone help me the procedures how to implement Huffman encoder and decoder on a text file on FPGA pls?
Digital communication :: 05-17-2010 12:17 :: kude :: Replies: 2 :: Views: 3304
I am trying to do Manchester Encoder and decoder by using AT89c2051 microcontroller in Keil C....
Can any one help me out.... how to Encode and decode? I want to implement the logic 0---->01 and 1------>10...
Please guys.... Its very important to do in Embedded C only....
Thanks in Advance
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-06-2010 22:37 :: harshita :: Replies: 9 :: Views: 5128
i need to implement a vhdl code for a 4 to 16 decoder using 2 to 4 decoder in xilinx.plz can any one help me with the details relating to it or forward links related to my requirement..
thanks in advance
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-30-2008 06:16 :: vijayganesh :: Replies: 9 :: Views: 31622
I have to implement a RS decoder, I would like to know how syndrome generation is performed in the RS decoder and what will be the hardware implementation for the same.
If anyone can provide any support document for the same it will be very beneficial.
ASIC Design Methodologies and Tools (Digital) :: 09-10-2007 07:18 :: elec_student :: Replies: 1 :: Views: 815
Could someone please tell me how to implement a decoder for a
tail-biting convolutional code? I've been working on it all week and
can't figure it out
I'm using a 1/2 rate, constraint length 3 encoder
initialized with the first 3 bits of message. The bits of the message
are then fed through the (...)
Digital communication :: 07-08-2007 15:49 :: sundarmeenakshi :: Replies: 2 :: Views: 4345
I'm doing design in Virtex 5 using 8b/10b decoder IP core. But , the IP core support until virtex 4.
Anybody know the way to edit the EDIF code in order to implement the design in Virtex 5 ?
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-21-2006 20:41 :: choonlle :: Replies: 1 :: Views: 858
My question is, we have a de-interleaver. If we keep more bits than expected after de-mapper, how do we do de-interleaver?
Digital Signal Processing :: 03-17-2006 20:18 :: stevepre :: Replies: 4 :: Views: 1303
I have managed to build a IR transmitter based on PT2248 and an IR decoder using PIC18F452. I have successfully managed to decode the 18 commands and verify the given table.
For additional 63 commands, multiple keying is used on the 6 'continuoous' keys.
What does this mean? how do I implement this (...)
Hobby Circuits and Small Projects Problems :: 04-23-2005 20:57 :: bimbla :: Replies: 1 :: Views: 1413