842 Threads found on edaboard.com: Ibm 130nm cmrf8sf
I am not an expert on ibm 130nm but it sounds like an antenna vioaltion of M3 to a diode not connected to the substrate.
For nets connected to NW contact, where the NW net is not connected to a substrate contact defined by ((RX over BP) not over (NW or JD or PI))
This means for a metal to NWell contact (using P+ SD) that is not also connected
Analog IC Design and Layout :: 12-28-2009 14:22 :: Colbhaidh :: Replies: 4 :: Views: 3737
Hi i am designing an LNA on ibm 130nm and cannot decide which capacitor,inductor or resistor to take for my LNA .I have to work for 2.4 GHz.Ifsomebody knows it.Please help me for it.
Also tell me what is meant if its written that this capacitor is availble withBEOL metallizatin only.
RF, Microwave, Antennas and Optics :: 04-17-2010 01:12 :: s_ss :: Replies: 0 :: Views: 941
Since I can't extract the parasitic capacitance of the pads, I want to know what is the value of PAD parasitic capacitance in ibm 130nm?
Analog Circuit Design :: 07-10-2013 09:02 :: soa :: Replies: 3 :: Views: 409
Hi there, in my circuit I'm using inductors of ibm-130nm (cmos8rf) with M1 ground-plane. When instantiating inductors we can select internal connection o external connection. For what I understand, internal connection should be used when one of the terminals is connected to an AC ground potential, which is my case. I supposed that the layout of suc
Analog IC Design and Layout :: 10-08-2013 17:54 :: jlgr :: Replies: 4 :: Views: 424
For the design of a CML based XOR gate, at low frequency it works fine.
As I increase the frequency ~1GHz, the o/p has a delayed rise time. What parameters do I need to change to get the accurate waveforms?
W/L ratios in the attachment Schematic
Analog IC Design and Layout :: 04-25-2014 00:46 :: gangnam_style :: Replies: 1 :: Views: 243
I am doing a layout of a simple common-centroid differential pair with multipliers and fingers using ibm 130nm cmrf8sf. DRC runs fine. But i get malformed device error:
*ERROR* Device 'nfet(Generic)' on Schematic is unbound to any Layout device.
Any ideas on how to solve this?
Analog IC Design and Layout :: 10-30-2014 12:57 :: artho :: Replies: 1 :: Views: 54
by "assura extraction" I assume you're using RCX. The kit no longer supports RCX, use Cadence QRC. You can find the supported tools here (IC613 is also supported although its not listed):
Analog IC Design and Layout :: 12-31-2009 10:57 :: oermens :: Replies: 3 :: Views: 2873
Guess you know you can get these rules files only by signing an NDA.
You could also try and get the ibm 130nm PDK from the University of Texas at Dallas.
Analog IC Design and Layout :: 12-24-2012 12:26 :: erikl :: Replies: 1 :: Views: 687
I will migrate all my circuits designed in ibm 130nm to TSMC 130nm.
I would like to know if there is someone who has had a similar experience, and if he can help me on the choice of transistors or by giving me some documents?
Analog Circuit Design :: 05-20-2014 09:03 :: fyengui :: Replies: 2 :: Views: 490
I am simulating some inverter output stage using ibm 130nm pdk.
when I want to sweep the w/L ratio and what I did was to put the variable "parameter" in the number of fingers box in the editting instance panel.
It seems incorrect.
Can anyone tell me what should be the correct way to do the sweeping ?
Linux Software :: 07-22-2009 08:58 :: whlinfei :: Replies: 1 :: Views: 897
I am new to cadence and I have to use cadence virtuoso and ibm 130nm pdk to do the simulation.
I don't know how to sweep the w over L ratio and couldn't find any relevant info on the web. Apparently only some gate biasing sweep and gate voltage variable sweeping can be found on the internet.
Thank you so much if you can help me out
Analog IC Design and Layout :: 07-22-2009 09:18 :: whlinfei :: Replies: 4 :: Views: 3857
When I design a simple delayed RZ logic circuit(just simple inverters and Nand gates), I meet following warning. How to solve these problems? (ibm 130nm process)
juction current exceeds 'imelt'
juction current exceeds 'imax'
I checked model files and all imax and imelt definded as following:
bondpad.scs imax = 1e15
divpnp.scs imax = 1e6*
Analog Circuit Design :: 07-28-2009 22:39 :: arong00 :: Replies: 2 :: Views: 1062
I'm also using ibm PDK in 32nm, For my Ports they are set wirth M1 'll' layer and not with "pn"
Normally with "ll" label it should work...
Analog IC Design and Layout :: 12-10-2009 03:54 :: gafsos :: Replies: 4 :: Views: 1932
I am still waiting for MOSIS' approval. And I really want to have the model to begin the design ASAP.
Until you receive the proper TSMC models, you could perhaps start with the ibm 130nm HSPICE level 49 models from MOSIS , or wit
Analog IC Design and Layout :: 03-18-2010 12:58 :: erikl :: Replies: 5 :: Views: 2109
I've got a problem with Assura LVS. I don't understand why all of my digital circuits which used to pass LVS can't pass now. The process I use is ibm 65nm, they just updated the new PDK, so I thought it is due to the new PDK. However, when I used the old PDK that I had used before, it still didn't pass.
The mismatch is about th
Analog IC Design and Layout :: 07-12-2010 20:22 :: jts :: Replies: 5 :: Views: 1104
ibm 130nm has characterized bondpads as part of the pdk
Analog IC Design and Layout :: 09-22-2010 20:09 :: oermens :: Replies: 5 :: Views: 719
i am working on cadence ibm 130nm and using NMOS.
RF, Microwave, Antennas and Optics :: 10-10-2010 23:36 :: s_ss :: Replies: 2 :: Views: 456
Now I face a problem when using the Vncap to consist of a 6*6 cap array.
I already find that the cap should be placed on the RX and BP layer when setting the 3rd terminal of VNcap in the schematic to be substrate. And if I just test a single vncap in the LVS ,it can pass; however when I use a array of vncap, for example 6*6 , the LVS error is
Analog IC Design and Layout :: 01-19-2011 07:55 :: NO1_NANO :: Replies: 0 :: Views: 557
I got the following error while running the Assura DRC. There are other topics that treat this issue, but I´ve not find the solution yet. Please, could someone help me?
I´m using IC6.15 and 130nm ibm CMOS process (cmrf8sf)
Thank you very much,
Analog IC Design and Layout :: 05-26-2011 19:13 :: palmeiras :: Replies: 11 :: Views: 3375
the error is puzzling since this is one of the suggestions provided (valid tied down 2) to fix the original violation and also because it work in the very similar ibm 130nm process. In any case simply split the rectangle in two parts one all inside NW one in the external PW and connect them by M1, that should fix it
Analog IC Design and Layout :: 08-09-2012 13:16 :: dgnani :: Replies: 5 :: Views: 1355
I am a fairly new user using calibre tool for DRC error check. I have not finalized my design and want to perform DRC check on the blocks. Suppose an inverter.. I saw from earlier threads that there is a way to avoid chip edge related error by choosing the cell switch on. Can someone please elaborate on this? Where can I find the cell-sw
Analog IC Design and Layout :: 10-19-2012 16:35 :: zohaibhameed007 :: Replies: 0 :: Views: 272
I would like to create a shield around a differential clock on the metal2 (Virtuoso Layout IC6.1.5 - ibm 130nm). How do I do this ?
Analog IC Design and Layout :: 01-29-2013 03:36 :: ritchyv :: Replies: 2 :: Views: 428
I'm using ARM IP's SRAM memory compiler for ibm 130nm. It is only characterized for nominal voltage and some worst case corners. I'd like to scale VDD significantly since I only need a fraction of its specified performance at full voltage. I do have netlists and full layout view available, but there are no simulation testbenches. Is it feasible to
ASIC Design Methodologies and Tools (Digital) :: 02-24-2013 05:35 :: allanvv :: Replies: 1 :: Views: 230
I am trying to simulate a simple circuit in virtuoso using Spectre. The tecnhology is ibm CMOS 8 RF (I also tried to use ibm 7 RF and got the same error), and the following errors appear. Any Ideas on what is going on an how to fix? I will really appreciate any help.
Error found by spectre during hierarchy f
Analog Circuit Design :: 03-12-2013 12:27 :: edcotrim :: Replies: 1 :: Views: 1002
hello I intend to use PTM models of 32nm for LNA design. I have access to ibm 130nm techfiles only. Please correct me if I am wrong "I understand that for designing LNA, I must have inductors and capacitors of the same 32nm technology" and I cannot use the 130nm inductors or caps with the 32nm transistor". Is this true?? I am saying this (...)
Analog Circuit Design :: 07-10-2013 07:55 :: s_ss :: Replies: 0 :: Views: 205
i use cmrf8sf 130nm, it is a very good kit. the structure gets tricky once updates are installed and you should be careful about the paths defined in .cdsinit, .cdsenv and cds.lib to ensure you are using the latest version of the kit.
Analog IC Design and Layout :: 03-04-2009 15:21 :: oermens :: Replies: 5 :: Views: 1743
hello! can anyone help me step by step to design an LNA on 130nm ibm on cadence?I am designing for WLAn 11g at 2.4 GHZ and bandwidth is 167MHz.I have reached a cascode stage but getting warning like vgs-vbs is -2.74 exceeds lower limit -2.6.Can somebody suggest the reason of this warning and keep hepling throughout my design?
RF, Microwave, Antennas and Optics :: 07-26-2010 11:23 :: patriot :: Replies: 1 :: Views: 663
I'm using ibm cmrf8sf with ic614 & assura410 & EXT914. and there is problem when I run QRC and do post-simulation of a simple inverter, the netlist below is extracted from the av_extracted view which I get from QRC. I think the net07 and \1\:net07 should be connected by a parasitic resistor or directly connected, or that definitely would m
Analog IC Design and Layout :: 11-24-2010 04:25 :: akon_cn :: Replies: 1 :: Views: 1277
Except some academic tryouts, compound semiconductor devices such as GaAs GaN etc. and derivatives are used at those frequencies tu build up VCOs, LNAs etc.
Not quite true. The "academic tryouts" have reached frequencies at > 200GHz now, targeting 500 GHz.
SiGe BiCMOS te
RF, Microwave, Antennas and Optics :: 05-04-2012 04:37 :: volker_muehlhaus :: Replies: 6 :: Views: 947
1. Never used it myself but i think its a set of standard cells for I/O and reference circuits. I don't think they give you layout view, but a blackbox which is filled in by the foundry during fab. Refer to:
1. I'm not sure, see if you have other bindkey sets
Analog Circuit Design :: 04-30-2009 10:46 :: oermens :: Replies: 1 :: Views: 2214
Is there any way I can decide which technology is best for my design? or is it just by random choice that one uses a particular technology. I am confused as to which one to use, CMC's CMOSP18 Design Kit for the 0.18-micron CMOS technology from TSMC or the CMC's CMOSP13 Design kit for the ibm cmrf8sf DM 0.13 micron CMOS technology.
Analog IC Design and Layout :: 07-16-2009 12:46 :: analog2003 :: Replies: 5 :: Views: 1146
SX_StampErrorFloat. Guess: Unconnected substrate or well.
I don't thing so because I have my ring contact for the nwell and pwell.
Have you used cmrf8sf technology from ibm before?
Analog IC Design and Layout :: 08-13-2010 14:24 :: kanounmoez :: Replies: 5 :: Views: 950
I'm extracting a simple circuit block (double-balanced passive mixer), which has only 4 transistors, each has 64um total width, 64 fingers. After I did Calibre PEX extraction (R+C+CC), I noticed the CC term (coupled capacitance) is extremely large, on the order of 70fF, which does not make any sense.
I'm suspecting that Calibre also ext
Analog IC Design and Layout :: 11-24-2010 15:44 :: litwood :: Replies: 1 :: Views: 1889
I am using the ibm 0.13um cmrf8sf design kit DM option. The transistors (pfer & rfet) auto-generated by ibm in layout contain such errors:
1) The auto-generated contact (CA) to finger poly (PC) is less than 0.14um
2) The auto-generated contact (CA) to RX is less than the minimum extension distance.
I use the (...)
Analog IC Design and Layout :: 04-26-2012 10:46 :: JohnLai :: Replies: 2 :: Views: 4493
I am facing the same issue with extraction using Calibre and ibm130nm. Is there a way to fix it? Any help is greatly appreciated.
Analog Circuit Design :: 01-29-2014 14:54 :: siladitya :: Replies: 2 :: Views: 732
Where can I find a ibm TestBench license?
ASIC Design Methodologies and Tools (Digital) :: 06-04-2002 08:18 :: contador :: Replies: 0 :: Views: 1420
Other Design :: 12-30-2002 23:05 :: riz_aj :: Replies: 1 :: Views: 1214
Software Links :: 12-31-2002 00:23 :: riz_aj :: Replies: 0 :: Views: 1297
The JTAG debugger interface to the PowerPC 405 series is proprietary. You will have to contact either ibm or Motorola and sign a NDA before you can get this information.
Professional Hardware and Electronics Design :: 01-24-2003 00:51 :: drwho78 :: Replies: 4 :: Views: 2115
Cadence to use ibm Linux power in EDA
ibm and Cadence Design Systems have announced an agreement to jointly optimise and market electronic design solutions from Cadence using ibm's advanced Linux-based technology.
1. Look at:
Cadence expects shift to Intel-based Lin
Linux Software :: 02-09-2003 07:38 :: jimjim2k :: Replies: 0 :: Views: 1222
I got a old ibm AT power supply without main switch. It starts from motherboard. Now I want use this as my hobby power supply, becauce there are 5.0V, 12V, 3.0V. But I don't know how to put it on.
The model is: DPS-200PB-70 E Rev:00.
Do some of you know how to put it in on mode?
Thanks a lot!
Hobby Circuits and Small Projects Problems :: 02-26-2003 04:47 :: ltg :: Replies: 2 :: Views: 1522
German government moves to ibm Linux
1. -> t
Linux Software :: 04-21-2003 07:51 :: jimjim2k :: Replies: 0 :: Views: 829
ibm and Cadence use supercomputing power of Linux in design
Building on a long-standing relationship to provide the world's leading integrated circuit design solutions, ibm and Cadence Design Systems, Inc. (NYSE:CDN - News) have announced an agreement to jointly optimize and market electronic design solutions from Cadence using (...)
Linux Software :: 04-21-2003 07:53 :: jimjim2k :: Replies: 0 :: Views: 1238
u can get the spec from this satya
ASIC Design Methodologies and Tools (Digital) :: 06-30-2003 23:58 :: satya :: Replies: 1 :: Views: 1164
I need service manual or eletrical schematics for ibm monitor G54
tanks in Advance for your help !
Service Manuals, Requests, Repair Tips :: 07-25-2003 08:21 :: ripmon :: Replies: 1 :: Views: 3448
You should choose PC.
My friend designed a 10bit pipeline ADC on linux environment.
This chip has tape-outed last month.
He used laker for layout. Laker is a better layout tool than virtuso.
Laker has more friendly interface, faster display, and easier to layout.
At our office, we have ultra60 and blade1000, but he still prefer using
ASIC Design Methodologies and Tools (Digital) :: 10-06-2003 01:00 :: jiang :: Replies: 26 :: Views: 4416
I recently acquired 1500 parts of lcd model: LM-JA53-22NFW (Dual Scan Color model - 800x600 RGB) and would like to get greaters information about how create an interface to connect with output standard vga ibm PC.
Exists some integrated circuit specific?
Thanks a lot, Gorkin!
:cry: :( :cry:
Professional Hardware and Electronics Design :: 11-14-2003 11:03 :: gorkin :: Replies: 0 :: Views: 752
Anybody can help me to repair ibm G42 monito, problem is simple out of focus, cannot read the charecters. if possible help to get schematic
Service Manuals, Requests, Repair Tips :: 01-05-2004 06:09 :: makri :: Replies: 1 :: Views: 805
does someone know where i can get the schematic of the folloing hdd.
ibm Deskstar series: IC356120AVVA0-0 120GB 7200 rpm
i can't eccess my hdd and there are important data on it, so i want check wheter there is an error in the electical part.
thanks in advance,
Professional Hardware and Electronics Design :: 01-25-2004 07:38 :: hqqh :: Replies: 3 :: Views: 1098
Sony details 65-nm spending, includes ibm East Fishkill
Sony Corp. and Sony Computer Entertainment Inc. (SCEI) said Monday (February 02, 2004) that they would make an investment of about 120 billion yen (about US$1.1 billion) in the fiscal year from April 2004, which would be divided between three facilities; its own fab, a joint operati
Other Design :: 02-11-2004 13:36 :: jimjim2k :: Replies: 0 :: Views: 1120