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847 Threads found on Ibm 130nm cmrf8sf
I am not an expert on ibm 130nm but it sounds like an antenna vioaltion of M3 to a diode not connected to the substrate. For nets connected to NW contact, where the NW net is not connected to a substrate contact defined by ((RX over BP) not over (NW or JD or PI)) This means for a metal to NWell contact (using P+ SD) that is not also connected
Hi i am designing an LNA on ibm 130nm and cannot decide which capacitor,inductor or resistor to take for my LNA .I have to work for 2.4 GHz.Ifsomebody knows it.Please help me for it. Also tell me what is meant if its written that this capacitor is availble withBEOL metallizatin only. Thnax
Hello all, Since I can't extract the parasitic capacitance of the pads, I want to know what is the value of PAD parasitic capacitance in ibm 130nm? thanks
Hi there, in my circuit I'm using inductors of ibm-130nm (cmos8rf) with M1 ground-plane. When instantiating inductors we can select internal connection o external connection. For what I understand, internal connection should be used when one of the terminals is connected to an AC ground potential, which is my case. I supposed that the layout of suc
Hi, For the design of a CML based XOR gate, at low frequency it works fine. As I increase the frequency ~1GHz, the o/p has a delayed rise time. What parameters do I need to change to get the accurate waveforms? W/L ratios in the attachment Schematic Waveform [URL="obr
Hi, I am doing a layout of a simple common-centroid differential pair with multipliers and fingers using ibm 130nm cmrf8sf. DRC runs fine. But i get malformed device error: *ERROR* Device 'nfet(Generic)' on Schematic is unbound to any Layout device. Any ideas on how to solve this? Thanks.
by "assura extraction" I assume you're using RCX. The kit no longer supports RCX, use Cadence QRC. You can find the supported tools here (IC613 is also supported although its not listed):
Guess you know you can get these rules files only by signing an NDA. You could also try and get the ibm 130nm PDK from the University of Texas at Dallas.
Regarding the mapping of transistors, you need to understand both technologies well. Sometimes you can't map cells 1:1 , but it depends also on the properties of the source cell, which target cell to choose. Migrating schematics in that particular path (ibm -> TSMC) you may face trouble with different symbols, symbol orientation, different number o
Hi all, I am simulating some inverter output stage using ibm 130nm pdk. when I want to sweep the w/L ratio and what I did was to put the variable "parameter" in the number of fingers box in the editting instance panel. It seems incorrect. Can anyone tell me what should be the correct way to do the sweeping ? thank you. Regards, Whli
Hi all, I am new to cadence and I have to use cadence virtuoso and ibm 130nm pdk to do the simulation. I don't know how to sweep the w over L ratio and couldn't find any relevant info on the web. Apparently only some gate biasing sweep and gate voltage variable sweeping can be found on the internet. Thank you so much if you can help me out
When I design a simple delayed RZ logic circuit(just simple inverters and Nand gates), I meet following warning. How to solve these problems? (ibm 130nm process) juction current exceeds 'imelt' juction current exceeds 'imax' I checked model files and all imax and imelt definded as following: bondpad.scs imax = 1e15 divpnp.scs imax = 1e6*
Hello, I'm also using ibm PDK in 32nm, For my Ports they are set wirth M1 'll' layer and not with "pn" Normally with "ll" label it should work... BR g@fsos
I am still waiting for MOSIS' approval. And I really want to have the model to begin the design ASAP. Until you receive the proper TSMC models, you could perhaps start with the ibm 130nm HSPICE level 49 models from MOSIS , or wit
Hi everyone, I've got a problem with Assura LVS. I don't understand why all of my digital circuits which used to pass LVS can't pass now. The process I use is ibm 65nm, they just updated the new PDK, so I thought it is due to the new PDK. However, when I used the old PDK that I had used before, it still didn't pass. The mismatch is about th
ibm 130nm has characterized bondpads as part of the pdk
Hi, i am working on cadence ibm 130nm and using NMOS.
Now I face a problem when using the Vncap to consist of a 6*6 cap array. I already find that the cap should be placed on the RX and BP layer when setting the 3rd terminal of VNcap in the schematic to be substrate. And if I just test a single vncap in the LVS ,it can pass; however when I use a array of vncap, for example 6*6 , the LVS error is
Hi everyone, I got the following error while running the Assura DRC. There are other topics that treat this issue, but I´ve not find the solution yet. Please, could someone help me? I´m using IC6.15 and 130nm ibm CMOS process (cmrf8sf) Thank you very much, Regards, (...)
I am using ibm .18u technology and keep getting this DRC error related to my nwells and have no clue how to fix it. DRC error message: (((NW not cover by GRLOGIC) or (NW touching BB)) touching ((PC over RX)) not over DN must be tied down by the time M1 is complete. valid tie down 1 : pdiff in NW is connected to ndiff in substrate by m1 val
Hi all, I am a fairly new user using calibre tool for DRC error check. I have not finalized my design and want to perform DRC check on the blocks. Suppose an inverter.. I saw from earlier threads that there is a way to avoid chip edge related error by choosing the cell switch on. Can someone please elaborate on this? Where can I find the cell-sw
Hi, I would like to create a shield around a differential clock on the metal2 (Virtuoso Layout IC6.1.5 - ibm 130nm). How do I do this ? Thanks
I'm using ARM IP's SRAM memory compiler for ibm 130nm. It is only characterized for nominal voltage and some worst case corners. I'd like to scale VDD significantly since I only need a fraction of its specified performance at full voltage. I do have netlists and full layout view available, but there are no simulation testbenches. Is it feasible to
Hello everyone! I am trying to simulate a simple circuit in virtuoso using Spectre. The tecnhology is ibm CMOS 8 RF (I also tried to use ibm 7 RF and got the same error), and the following errors appear. Any Ideas on what is going on an how to fix? I will really appreciate any help. Thanks! Evandro Error found by spectre during hierarchy f
hello I intend to use PTM models of 32nm for LNA design. I have access to ibm 130nm techfiles only. Please correct me if I am wrong "I understand that for designing LNA, I must have inductors and capacitors of the same 32nm technology" and I cannot use the 130nm inductors or caps with the 32nm transistor". Is this true?? I am saying this (...)
Hello, I've designed a digital core with ARM front end standard cell and an analog circuit in cadence Virtuoso in ibm 130nm. I wanted to do the mixed mode simulations in virtuoso. However, the ARM front end standard cells doesn't provide any information inside. Could someone please help me in doing simulations with front end standard cells.
i use cmrf8sf 130nm, it is a very good kit. the structure gets tricky once updates are installed and you should be careful about the paths defined in .cdsinit, .cdsenv and cds.lib to ensure you are using the latest version of the kit.
hello! can anyone help me step by step to design an LNA on 130nm ibm on cadence?I am designing for WLAn 11g at 2.4 GHZ and bandwidth is 167MHz.I have reached a cascode stage but getting warning like vgs-vbs is -2.74 exceeds lower limit -2.6.Can somebody suggest the reason of this warning and keep hepling throughout my design?
Hi, I'm using ibm cmrf8sf with ic614 & assura410 & EXT914. and there is problem when I run QRC and do post-simulation of a simple inverter, the netlist below is extracted from the av_extracted view which I get from QRC. I think the net07 and \1\:net07 should be connected by a parasitic resistor or directly connected, or that definitely would m
Hello everyone, I'm trying to design a VCO in the 50 - 70 GHz range using the ibm 0.13um cmrf8sf and I've got several questions: - The transition frequency for the transistors in this process is about 90 GHz. Do you think they will present enough gain at the band of interest? - Although I'm more used to single transistor topologies, I've
ARM: 1. Never used it myself but i think its a set of standard cells for I/O and reference circuits. I don't think they give you layout view, but a blackbox which is filled in by the foundry during fab. Refer to: ibm: 1. I'm not sure, see if you have other bindkey sets
i don't think anyone here really knows who CMC are (other than myself maybe)... ibm cmrf8sf (cmosp13 in CMC terms) is great, I just submitted a fab in it. easy to set up, pcells for everything, mosis is great with support. tsmc .18 (cmosp18) is good if you're new to cadence, its not a very complicated kit but not very robust either. no pcells, c
SX_StampErrorFloat. Guess: Unconnected substrate or well. I don't thing so because I have my ring contact for the nwell and pwell. Have you used cmrf8sf technology from ibm before?
Hello, I'm extracting a simple circuit block (double-balanced passive mixer), which has only 4 transistors, each has 64um total width, 64 fingers. After I did Calibre PEX extraction (R+C+CC), I noticed the CC term (coupled capacitance) is extremely large, on the order of 70fF, which does not make any sense. I'm suspecting that Calibre also ext
Dear Folks, I am using the ibm 0.13um cmrf8sf design kit DM option. The transistors (pfer & rfet) auto-generated by ibm in layout contain such errors: 1) The auto-generated contact (CA) to finger poly (PC) is less than 0.14um 2) The auto-generated contact (CA) to RX is less than the minimum extension distance. I use the (...)
Hi, I am facing the same issue with extraction using Calibre and ibm130nm. Is there a way to fix it? Any help is greatly appreciated. Thanks!!
Hello... Where can I find a ibm TestBench license? Thanks...
The JTAG debugger interface to the PowerPC 405 series is proprietary. You will have to contact either ibm or Motorola and sign a NDA before you can get this information.
Hi Cadence to use ibm Linux power in EDA ibm and Cadence Design Systems have announced an agreement to jointly optimise and market electronic design solutions from Cadence using ibm's advanced Linux-based technology. 1. Look at: Cadence expects shift to Intel-based Lin
Hi, I got a old ibm AT power supply without main switch. It starts from motherboard. Now I want use this as my hobby power supply, becauce there are 5.0V, 12V, 3.0V. But I don't know how to put it on. The model is: DPS-200PB-70 E Rev:00. Do some of you know how to put it in on mode? Thanks a lot! Best Regards, ltg
Hi German government moves to ibm Linux 1. -> t tnx
Hi ibm and Cadence use supercomputing power of Linux in design Building on a long-standing relationship to provide the world's leading integrated circuit design solutions, ibm and Cadence Design Systems, Inc. (NYSE:CDN - News) have announced an agreement to jointly optimize and market electronic design solutions from Cadence using (...)
HI , u can get the spec from this satya
I need service manual or eletrical schematics for ibm monitor G54 model 6546-OBN tanks in Advance for your help !
Hi~~everyone.. I've used SUN ultra60 for analog layout design at my office. However, I got a second job at home...... I've wanted to buy a Sun blade2000, but it's too expensive to get it (around $20000) so I got a IC50 for Linux to use my ibm PC at my home. (P4 1.7Ghz, RDRAM 512MB, VideoRAM 64MB) However, the performance at ibm PC was so t
Hello all! I recently acquired 1500 parts of lcd model: LM-JA53-22NFW (Dual Scan Color model - 800x600 RGB) and would like to get greaters information about how create an interface to connect with output standard vga ibm PC. Exists some integrated circuit specific? Thanks a lot, Gorkin! :cry: :( :cry:
Anybody can help me to repair ibm G42 monito, problem is simple out of focus, cannot read the charecters. if possible help to get schematic
hello, does someone know where i can get the schematic of the folloing hdd. ibm Deskstar series: IC356120AVVA0-0 120GB 7200 rpm i can't eccess my hdd and there are important data on it, so i want check wheter there is an error in the electical part. thanks in advance, hqqh