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6 Threads found on edaboard.com: Idelay
Hi Everyone, I'm fairly new to FPGA programming and this is my first post on the forum. I'm currently building a new camera using an Artix-7 FPGA and the Vivado design suite (using verilog). The image sensor supplies its data via 8 LVDS DDR lines and 1 LVDS clock. So far, the project is going well. I've managed to get an image off the sensor and
Not sure what you want to do. This is something else other than propagation delays. Xilinx FPGAs provide adjustable idelay and ODELAY primitives in the device's I/O blocks. They are most often used to make small adjustments to I/O timing, but with some imagination you can find other creative uses. It's a bunch of delay taps that you can adjust on
in virtex 4 idelay element- part of the deserializer. In this case, it was possible to configure it so that the delay was used for deserializer, bat the signal passes through from input to output O without delay. in virtex 5 a delay element separate. The question of whether I can use deserializer with delay, but clocked scheme without delay.
Can you please tell me what are the components in the following portion of the starrcxt extracted netlist : *|I (I35/idelay/I71/I138/XI0/n1_2:F15613 I35/idelay/I71/I138/I0/MNA1 SRC B 0 146.41 9.185) // $llx=146.34 $lly=8.915 $urx=146.48 $ury=9.455 $lvl=182 So here what components denote? e.g SRC ,B ,0,146.41 what these values and names denot
Hi, I am wondering why Xilinx MIG2.0 doesn't support dual-rank DIMM? based on my testing, the idelay taps for both ranks are very close. thank you. adam
Yes, some Xilinx FPGAs provide adjustable idelay and IODELAY primitives in the device's I/O blocks. They are most often used to make small adjustments to I/O timing, but with some imagination you can find other creative uses. For details, refer to your FPGA User Guide, and the special ISE Libraries Guide for your specific FPGA. Those delays requ


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