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52 Threads found on edaboard.com: Incisive
Hi, I want to do accurate power estimation using cadence tools on a simple design with 8 flipflops and a fulladder involved. the only cadence tools avaialbe with me is, incisive entreprsise and genus. i learned to generate power report, but this time i want to keep invovle forward saif, backward saif files (came to know from internet) for
Xilinx ISE is old and so is ISIM, you should refrain from using them. Better would be to use Vivado and its integrated Vivado Simulator. While questa, incisive are much better but Xilinx is giving Vivado for free (free version). You still didn't mention if you have funds at you disposal. If you have go for VCS Synopsys. Vivado Simulator supports
Hi. Does anyone know what is difference between base and hotfix in cadence incisive tool? Can we use just hotfix type not base?
hi, I am new user of cadence incisive unified simulator. I want to run a mixed signal simulation. I am able to run a mixed signal simulation of a design consisting of a verilog module and an analog schematic module, when using cells only from analogLib in the schematic. The problem is when I use the cell from the foundry library there are errors in
Hi All, I am looking for specific commands in the ncsim tool where the user can stop the simulation when it is on going - check the result and start it from the point it had ended the last simulation on. Will breakpoint work in this tool. Regards Limitless
Hi All, Could someone share incisive/NCsim Training Materials from Cadence? Thank you!
Can you guide me how to run ovm and uvm in Cadence incisive and Synopsys VCS.?
i Ma M.Tech Student.. I would like to do project in Cadence incisive.. May i know which topic is best to complete within 6 months..?
Hello Everyone i am getting a warning because of $shm_probe failed. ncsim: *W,SHMPFL: $shm_probe failed. Can anyone tell me how to remove that warning. Thanks And Regards Mukesh Goyal
The short answer is yes you can. Though you will require a mixed language simulator that has full SV support, like Questa, Riviera, incisive, etc. Most of those tools are $20K-$30K tools. I've only run across one free SV tutorial for someone without a company email address. It was posted by the creator of the tutorial.
ModelSim / VCS / incisive all support UPF, to varying extents, providing you have the right license, for power-aware simulation. They don't model voltages like an analog simulator, but you can see why power domain signals are in.
Hi, I'm running post simulation with incisive tool, but always be headache to deal with those glitches for pads. The pad always has big delay while the signals period is smaller than it. I have tried to adjust pulse_r/e parameters to let signals go through pad and filter those small glitches, but this step is painful and frustrated me always. Some
All tools like cadence incisive, synopsys vcs, mentor graphics modelsim support transistor (switch level primitives) as defined in verilog standard. See those primitives here
Modelsim is sort of an industry defacto standard. Xilinx ISIM is for Xilinx parts only and is still not as good as Modelsim incisive is a Linux/Unix based simulator from Cadance Aldec is a another PC based simulator that competes directly with Modelsim on features. VCS is synopsys' simulator which is very fast and is Unix based (funny how Googl
Hi everyone, please help me with the next problem: I'm designing a digital IC based on FPGA-verified source code using Cadence tools: Encounter for P&R and optimization and incisive simulator (NCSim may be the second name) for checking the resulting waveforms. After P&R, in post-route stage, I optimized design using the next commands: optDe
hello there i have a problem while i try to run ifv i source the ifv_setup which located at: ifv/bin folder and there what it says: ifv_setup : (c) Copyright 1995-2009 Cadence Design Systems, Inc. bash: /home/edatools/INCISIV-10.20.026/tools/ifv/bin/ifv_setup: line 11: syntax error near unexpected token ``/bin/uname`' bash: /home/edatools/I
Hi All, I'm using Cadence's incisive tool to perfom simulation and code-coverage analysis. My desgin has 2 process FSM modelling style (means combinational and sequential logic defined in two separate process). Problem is not able to do FSM extraction getting below message from log file : Extracting FSMs for coverage:
incisive belong to the simulator tool!
AMS is more accurate while incisive simulator not so good for mix-signal simulation !
Hi, when i run the simulation i am getting the following error VPI TUINVLD can anyone please if you know the meaning explain the error i am not getting any info on the same thanks kiran
I can only help with some SPMN stands for specman EMGR for enterprice manager IUS is the incisive unified simulator but I can not give informations about the repeating sections and the general idea behind it regards
I want to inquire the price range of the following software for group uses. ==================================== Matlab (multiple license) Cadence EDA software RTL Compiler, SoC Encounter, Conformal Low Power, incisive Enterprise Simulator, QRC, Encounter Timing System, Encounter Power System Cadence RF spectre, C
what the purpose of "Verilog-XL" tool from Cadence? the options available in Verilog-XL's are: 1. incisive verification environment 2. incisive P2C Methodology 3. incisive Design Team simulator 4. Affirma simulation analysis environment is it the option only for file and its compiling, elaborating and simulation or can we do the .vhd
Can anyone send me a userguide for incisive simulator
can anyone help me out I am facing a problem while generating TCF files in incisive Simulator. I am getting this error when I am generating TCF files in ncsim console window. using the command dumptcf -flatformat -internal -scope pcixp_test -output dump.tcf -verbose actual error is +w, TCFNOP : pcixp_test.pcixp_test1.M0.FIFO was no
While I was installing Cadence incisive Unified Simulator (IUS) 5.6, I got this message: " Checking data files... Executing control programs (pre-load) ... sort: open failed: +3: No such file or directory expr: syntax error " I was installing on Linux Centos 5.3. I think this arises from the following line in the load_pkgs shell s
Not to worry. Just as the business/financial world still uses COBOL, an ancient computer programming language that is no longer taught in university, the ASIC/EDA-world will continue to use ABEL, Altera-HDL, e, VERA, etc. Specman is often bundled/discounted with incisive Enterprise Simulator (IES), but it is not a 'free' tool. It's a Cadence p
Which simulator are you using (Questasim, VCS, or incisive)? Some simulators don't support the full Systemverilog language. I'm pretty sure the argument of $size() is known at compile/elaboration time. Therefore, the output of $size() inherits the constant/static property, but some simulators don't recognize this. But I might be overlooking
Take a look at Click TUTORIALS and read about pointers. simple and incisive. :idea:
Previously it was not like this.. I used PROMPT> hal asdfasdfasdf.vhd hal: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems, Inc. incisive HDL analysis hal: *W,DLNOHV: Unable to find an 'hdl.var' file to load in. hal: *E,VHDSNP: To use HAL with a VHDL file 'asdfasdfasdf.vhd', you must generate a snapshot. hal: *E,VHDS
IP or SoC business? Maybe Cadence incisive Flow or Synopsys Discoverly Flow may help you.
Hi incisive, How can you derive these numbers such as "Algorithm Level 75%" ? Is there any document or book that deals with how to estimate power reduction on different design levels?
For some unknown reasons, the incisive could not installed in the Linux 2.6 kernel. Try to install the incisive in 2.4 kernel and tar all files and untar the file in 2.6 kernel. Too many Linux distributions create a lot of troubles to install EDA in the linux OS.
hi, I am new to SystemC. We are trying Cadence incisive Unified simulator to run SystemC programs. but we are getting this error Could not load SystemC model library libncsc_model (./libncsc_model.so: undefined symbol: _ZN8stimulus4testEv). ncsc_run: *E,TBELABF: ncelab returned non-zero exit status could you please help me in thi
LDV was no longer supported by Cadence. It was replaced by incisive.
command === "simvision&" and then load the .trn and select the required signals to view and open the waveform browser. also can use "signalscan&" Signalscan is quite old and has been replaced by Simvision, a very powerful tool indeed. Regards Ajeetha, CVC
Dose anyone knows which one is incisive with specman elitte
Hi, Has anyone used this new feature from Mathworks MATLAB? "provides a bidirectional link between MATLAB and Simulink and incisive platform simulators from Cadence Design Systems." I've used MATLAB and incisive Unified Simulator but not the two together. I'm curious as to what have been
Burst cycle w r t microprocessors is particularly used when data is transfered between cache memories. group of data at a particular instruction. Do u have any example of that ?
to jackson_peng: I have cadence incisive platform which surpport systemverilog and E language, which one is better? Hi, SV is now an IEEE standard and all 3 major vendors have varied level of support for it today. AFAIK, Cadence has the least for SV-Testbench against Mentor/SNPS. You need to check with your tool docume
Hi incisive, Your meaning specify the hierachical timing check in the Verilog simulator or select different ways to do timing check in simulator? Please clear it.
Hi incisive, 1. Simulation based on cycle is faster than simulation based on event. 2. It is suitable to the regression test. 3. It is suitable to the 2-value logic. Good Luck
What do you think of incisive Unified Simulator of Cadence vs VCS of synopsys? Thanks!
I think both Specman and SystemC will be driven by Cadence. Best part is we can think of getting Specman along with incisive package. Cheers, Gold_kiss
It's incisive Unified Simulator(IUS), you can ask cadence to get it
for your ref .. I am also checking it now.... --------------------------------- The Cadence incisive? Unified Simulator, part of the incisive platform, provides everything you need to verify today's toughest designs. Its single-kernel architecture na
Any user manual, tutorial, training on using these PSL (property based language) tool from companies : @HDL, Safelogic, Cadence incisive, RealIntent.
anyone can share Cadence incisive?? I need Insicive SPW for simulation of cdma2000, I couldn't find it at all. :(
seem SPW now is part of incisive, don't know where can get it?
What is incisive ? It is included in Cadence LDV. What is defference form NC-SIM ? Anybody knows that ?